DATASHEET NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at ISL28617 1-888-INTERSIL or www.intersil.com/tsc FN6562 40V Precision Instrumentation Amplifier with Differential ADC Driver Rev 3.00 May 27, 2015 The ISL28617 is a high performance, differential input, Features differential output instrumentation amplifier designed for precision analog-to-digital applications. It can operate over a • Rail-to-rail differential output ADC driver supply range of 8V (±4V) to 40V (±20V) and features a • High voltage interface to low voltage circuits differential input voltage range up to ±34V. The output stage • Wide operating voltage range . . . . . . . . . . . . . . .±4V to ±20V has rail-to-rail output drive capability optimized for differential ADC driver applications. Its versatility and small package • Low input offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30µV makes it suitable for a variety of general purpose applications. • Excellent CMRR and PSRR. . . . . . . . . . . . . . . . . . . . . . .120dB Additional features not found in other instrumentation • Closed loop -3dB BW. . .0.3MHz (A =1k) to 5MHz (A =0.1) V V amplifiers enable high levels of DC precision and excellent AC • Operating temperature range. . . . . . . . . . . .-40°C to +125°C performance. • Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ld TSSOP The gain of the ISL28617 can be programmed from 0.1 to 10,000 via two external resistors, R and R . The gain Applications IN FB accuracy is determined by the matching of R and R . The IN FB gain resistors have Kelvin sensing, which removes gain error • Precision test and measurement due to PC trace resistance. The input and output stages have • High voltage industrial process control individual power supply pins, which enable input signals riding • Signal conditioning amplifier for remote powered sensors on a high common mode voltage to be level shifted to a low voltage device, such as an A/D converter. The rail-to-rail output • Weigh scales stage can be powered from the same supplies as the ADC, • ECG and biomedical sense amplifiers which preserves the ADC maximum input dynamic range and 140 eliminates ADC input overdrive. AV = 1000 120 Related Literature 100 AV = 100 •AN1753, “ISL28617VYXXEV1Z User’s Guide” Evaluation )Bd 80 AV = 10 board with bulk metal foil resistors for high precision. ( R R 60 •AN1748, “ISL28617SMXXEV1Z User’s Guide” Evaluation MC AV = 1 board with standard resistors for low cost, medium 40 precision. 20 AV = 0.1 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 1. CMRR R = 121k F FULL BRIDGE STRAIN GAUGE AMPLIFIER AND DIFFERENTIAL ADC DRIVER IN+ ++25T0VOV BRIDGE RIN +-+-RRRRIINNIINNS SEENNSSVEECICSL286V1C7O +VFB+VOUT R C +IN CONVVDAED-DRTER --52TV0OV EXCITATION RFB +-+-RRRRFFFFBBBB S SEENNVSSEEEE GNDVEOVCMO-VFB-VOUT R -IN VREF IGSLN2D6132 +5V IN- VREF ISL21090 AV = R /R RANGE FROM 0.1 TO 10,000 FB IN FIGURE 2. BASIC APPLICATION CIRCUIT FN6562 Rev 3.00 Page 1 of 20 May 27, 2015

ISL28617 ISL28617 Pin Descriptions (24 LD TSSOP) TOP VIEW PIN NAME PIN NUMBER DESCRIPTION NC 1 24 IN+ NC 1 No Internal Connection DNC 2 23 IN- DNC 2, 3, 22 For internal use; Do Not Connect. DNC 3 22 DNC +RFB 4 Feedback Resistor, RFB+ pin +R SENSE 5 +R , Positive Sense pin connects to the +R 4 21 +R FB FB FB IN resistor R + terminal to form the R + FB FB +R SENSE 5 20 +R SENSE Kelvin connection. FB IN -R SENSE 6 -R , Negative Sense pin connects to the FB FB -R SENSE 6 19 -R SENSE FB IN resistor R - terminal to form the R - FB FB Kelvin connection. -R 7 18 -R FB IN -R 7 Feedback Resistor, Negative Terminal. FB GND 8 17 V CMO GND 8 Ground Pin is capacitively coupled to the V 9 16 V internal ESD circuit and should be CC EE connected to power supply common or V 10 15 V signal GND. CO EO V 9 Positive Supply for Input Stage and +V 11 14 -V CC FB FB Feedback Amp. +VOUT12 13 -VOUT V 10 Positive Supply for Output Stage. CO +V 11 Positive Output Feedback FB +V 12 Positive Output OUT -V 13 Negative Output OUT -V 14 Negative Output Feedback FB V 15 Negative Supply for Output Stage. EO V 16 Negative Supply for Input Stage and EE Feedback Amp. V 17 Output Common Mode Reference input. CMO -R 18 Input Resistor, Negative Terminal. IN -R SENSE 19 -R , Negative Sense pin connects to the IN IN resistor R - terminal to form the R - IN IN Kelvin connection. +R SENSE 20 +R , Positive Sense pin connects to the IN IN resistor R + terminal to form the R + IN IN Kelvin connection. +R 21 Input Resistor, Positive Terminal. IN IN- 23 Negative Input IN+ 24 Positive Input Ordering Information PART NUMBER PART TEMP RANGE PACKAGE PKG. (Notes1, 2, 3) MARKING (°C) (RoHS Compliant) DWG. # ISL28617FVZ 28617 FVZ -40 to +125 24 Ld TSSOP M24.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28617. For more information on MSL please see tech brief TB363. FN6562 Rev 3.00 Page 2 of 20 May 27, 2015

ISL28617 Simplified Block Diagram +15V IN+ IN+ VCC ISL28617 VCO +RINSENSE VCC +RIN RIN -RIN -RINSENSE VEE IN- IN- +VOUT +OUT RL +VFB -VOUT -OUT +RFBSENSE VCC VCMO +RFB RFB -RFB -RFBSENSE VEE -VFB VEE GND VEO -15V GND FIGURE 3. SIMPLIFIED BLOCK DIAGRAM FN6562 Rev 3.00 Page 3 of 20 May 27, 2015

ISL28617 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage (VCC to VEE or GND) . . . . . . . . . . . . . . . . . . . . 42V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Maximum Supply Voltage (VCO to VEO or GND). . . . . . . . . . . . . . . . . . . . 42V 24 Ld TSSOP (Notes4, 5) . . . . . . . . . . . . . . 74 28 Maximum Voltage (VCO to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.5V, -40V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Maximum Voltage (VEO to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V, +40V Maximum Junction Temperature (TJMAX). . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Max/Min Input Current for Input Voltage >V or <V . . . . . . . . . . . . . ±10mA CC EE Maximum Input Current (±R , ±R , ±R SENSE, ±R SENSE) . . . .±5mA IN FB IN FB Recommended Operating Conditions Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . ..(VEE - 0.5V) to (VCC + 0.5V) Ambient Temperature Range (TA) . . . . . . . . . . . . . . . . . . .-40°C to +125°C Output Short-circuit Duration (1 Output at a Time). . . . . . . . . . . . . . Continuous V , V Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . .±4V to ±20V CC EE ESD Rating V , V Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . ±1.5V to ±20V CO EO Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA 5. For  , the “case temp” location is taken at the package top center. JC Electrical Specifications V = V =15V, V = V = -15V, V = 0V, R = 10kΩR = R = 30.1kΩT = +25°C, unless otherwise CC CO EE EO CM L FB IN A specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. MIN MAX PARAMETER DESCRIPTION TEST CONDITIONS (Note6) TYP (Note6) UNIT INPUT DC SPECIFICATIONS V IN IN+, IN- Common Mode Input Voltage Range V +3V V -3V V CMIR EE CC V IN Input Offset Voltage -100 ±30 100 µV OS -275 275 µV TCV IN Input Offset Voltage Temperature Coefficient -2.75 ±0.3 2.75 µV/°C OS I IN Input Bias Current -1 ±0.2 1 nA B -1.3 1.3 nA I IN Input Offset Current -0.75 ±0.2 0.75 nA OS -1 1 nA I Input Resistor Drive Current (Note7) 87 102 117 µA RIN R CM Common Mode Input Resistance 80 GΩ IN CMRR Common Mode Rejection Ratio V +3V < V < V -3V 110 120 dB EE CM CC G = 1 107 dB V +3V < V < V -3V 130 150 dB EE CM CC G = 100 110 dB FEEDBACK DC SPECIFICATIONS V FB +FB, -FB Common Mode Input Voltage Range V + 3V V - 3V V CMIR EE CC V FB Feedback Input Offset Voltage -1600 ±400 1600 µV OS -3000 3000 µV I V Input Bias Current at V ± Inputs 15 nA B FB+,- FB OUTPUT DC SPECIFICATIONS V Output Voltage Low, V to V V = +15V, V =-15V, 150 200 mV OL OUT - CC EE V = +4V, V =-4V CO EO 200 mV R = R = 121kΩI = 1.5mA IN F OUT FN6562 Rev 3.00 Page 4 of 20 May 27, 2015

ISL28617 Electrical Specifications V = V =15V, V = V = -15V, V = 0V, R = 10kΩR = R = 30.1kΩT = +25°C, unless otherwise CC CO EE EO CM L FB IN A specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN MAX PARAMETER DESCRIPTION TEST CONDITIONS (Note6) TYP (Note6) UNIT V Output Voltage High, V to V V = +15V, V =-15V, 150 200 mV OH + OUT CC EE V = +4V, V =-4V CO EO 200 mV R = R = 121kΩI = 1.5mA IN F OUT I Output Short-circuit Current R = 0Ωto GND ±45 mA SC L -20 20 mA I Total Internal Offset Error Current (Note8) -17 ±5 17 nA ERR -90 90 nA E Gain Error (Notes9, 10) V = -10V to +10V, R = 121kΩ G OUT F ±0.003 % G = 1 G = 100 ±0.004 % V = -2.5V to +2.5V, R = 30.1kΩ OUT F ±0.0005 % G = 1 OUTPUT COMMON MODE SPECIFICATIONS V CMIR Output Common Mode Control Input Voltage V +3V V -3V V CMO EE CC Range V CM Output Common Mode Offset Voltage from -1.3 ±0.5 1.3 mV OS V Input CMO -4.75 4.75 mV I V Input Bias Current at V Input -0.6 ±0.2 0.6 µA B CMO CMO -1.75 1.75 µA POWER SUPPLY SPECIFICATIONS I Supply Current, V to V R = OPEN 2.05 2.2 mA CC CC EE L 2.85 mA I Supply Current, V to V R = OPEN 2.25 2.6 mA CO CO EO L 2.85 mA V toV Input Supply Voltage Dual Supply ±4 ±20 V CC EE Single Supply 8 40 V V to V Output Supply Voltage Dual Supply ±1.5 ±20 V CO EO Single Supply 3 40 V PSRR V to V Power Supply Rejection Ratio V to V = ±4V to ±20V dB CC EE CC EE 123 130 G = 100 118 dB PSRR V to V Power Supply Rejection Ratio V to V = ±4V to ±20V 110 120 dB CO EO CO EO 110 dB AC SPECIFICATIONS e Input Noise Voltage Density f = 1kHz 8.6 nV/√Hz N e rms Input rms Noise Voltage f = 0.1 to 10Hz 85 nVrms N i Input Noise Current Density f = 1kHz 150 fA/√Hz N i IERR Total Internal Noise Current Density f = 1kHz 2.6 pA/√Hz N i IERR rms 0.1 to 10Hz Total Internal rms Noise Current f = 0.1 to 10Hz 4 pArms N FN6562 Rev 3.00 Page 5 of 20 May 27, 2015

ISL28617 Electrical Specifications V = V =15V, V = V = -15V, V = 0V, R = 10kΩR = R = 30.1kΩT = +25°C, unless otherwise CC CO EE EO CM L FB IN A specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) MIN MAX PARAMETER DESCRIPTION TEST CONDITIONS (Note6) TYP (Note6) UNIT -3dB BW -3dB Bandwidth vs Closed Loop Gain, R = 30.1kΩR = 301kΩG = 0.1 5.5 MHz FB IN R = 30.1k FB R = 30.1kΩR = 30.1kΩG = 1 2.6 MHz FB IN R = 30.1kΩR = 3.01kΩG = 10 2.2 MHz FB IN R = 30.1kΩR = 301ΩG = 100 2.0 MHz FB IN R = 30.1kΩR = 30.1ΩG = 1000 0.3 MHz FB IN -3dB BW -3dB Bandwidth vs Closed Loop Gain, R = 121kΩR = 1.21MΩG = 0.1 5.0 MHz FB IN R = 121k FB R = 121kΩR = 121kΩG = 1 1.4 MHz FB IN R = 121kΩR = 12.1kΩG = 10 0.5 MHz FB IN R = 121kΩR = 1.21kΩG = 100 0.45 MHz FB IN R = 121kΩR = 121ΩG = 1000 0.4 MHz FB IN SR Slew Rate 4 V/µs t Settling Time to 0.01% V = +2.4V, R = 30.1kΩ 3 µs S OUT F V = +9.6V, R = 121kΩ 11 µs OUT F NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Compliance to datasheet limits is assured by Design simulation. 8. V = A *V + V + I * R . OS,OUT V OS,IN OS,FB ERR FB 9. Differential Gain(A ) = R /R . V FB IN 10. ±V , clipping ~ I *R . OUT RF FB FN6562 Rev 3.00 Page 6 of 20 May 27, 2015

ISL28617 Typical Performance Curves V = V =15V, V = V = -15V, V = 0V, R = Open, unless otherwise specified. CC CO EE EO CM L 3 3 A) A) m m T ( T ( N N E E R R R 2 R 2 U U C C Y Y L L P P P P U U S S 1 1 0 10 20 30 40 50 0 10 20 30 40 50 SUPPLY VOLTAGE (VCC - VEE) SUPPLY VOLTAGE (VCO - VEO) FIGURE 4. ICC vs SUPPLY VOLTAGE (VCC - VEE) FIGURE 5. ICO vs SUPPLY VOLTAGE (VCO - VEO) 20 20 15 10 10 5 )A )A n 0 n 0 ( Irer -5 ( Irre -10 -10 -15 -20 -20 -15 -10 -5 0 5 10 15 0 5 10 15 20 25 30 35 40 45 50 VCM (V) VSUP (VCC - VEE) FIGURE 6. IERR vs INPUT COMMON MODE VOLTAGE FIGURE 7. IERR vs SUPPLY VOLTAGE (VCC - VEE) 1000 1000 800 800 600 600 400 400 )V 200 )V 200 µ( B 0 µ( B 0 FSO -200 FSO -200 V V -400 -400 -600 -600 -800 -800 -1000 -1000 -15 -10 -5 0 5 10 15 0 5 10 15 20 25 30 35 40 45 50 VCM (V) VSUP (VCC - VEE) FIGURE 8. V vs INPUT COMMON MODE VOLTAGE FIGURE 9. V vs SUPPLY VOLTAGE (V - V ) OSFB OSFB CC EE FN6562 Rev 3.00 Page 7 of 20 May 27, 2015

ISL28617 Typical Performance Curves V = V =15V, V = V = -15V, V = 0V, R = Open, unless otherwise specified. CC CO EE EO CM L 1000 1000 800 800 600 600 400 400 )Ap( SO -2200000 )Ap( ISO -2200000 I -400 -400 -600 -600 -800 -800 -1000 -1000 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 VSUP (VCC - VEE) VSUP (VCC - VEE) FIGURE 10. IOS vs SUPPLY VOLTAGE (VCC - VEE) FIGURE 11. IOS vs SUPPLY VOLTAGE (VCC - VEE) 1000 1000 800 800 600 +IB 600 +IB 400 400 200 200 )A )A p 0 p 0 ( IB -200 -IB ( IB -200 -IB -400 -400 -600 -600 -800 -800 -1000 -1000 -15 -10 -5 0 5 10 15 0 5 10 15 20 25 30 35 40 45 50 VCM (V) VSUP (VCC- VEE) FIGURE 12. I vs INPUT COMMON MODE VOLTAGE FIGURE 13. I vs SUPPLY VOLTAGE (V - V ) B B CC EE 100 100 80 80 60 60 40 40 )V 20 V) 20 µ(N 0 µ(N 0 I SO -20 I OS -20 V V -40 -40 -60 -60 -80 -80 -100 -100 -15 -10 -5 0 5 10 15 0 5 10 15 20 25 30 35 40 45 50 VCM (V) VSUP (VCC - VEE) FIGURE 14. VOS IN vs INPUT COMMON MODE VOLTAGE FIGURE 15. VOS IN vs SUPPLY VOLTAGE (VCC - VEE) FN6562 Rev 3.00 Page 8 of 20 May 27, 2015

ISL28617 Typical Performance Curves V = V =15V, V = V = -15V, V = 0V, R = Open, unless otherwise specified. CC CO EE EO CM L 5 15 4 3 10 2 V) 5 )Aµ( OM 01 T V (CM 0 VVCCCO == ++150VV; ;V VEEOE = = 0 -V10V BICV --21 INPU -5 RVCFBM O= =1 220.5kV; RIN = 120 -3 -10 -4 -5 -15 -15 -10 -5 0 5 10 15 -6 -4 -2 0 2 4 6 VCMO (V) VOUT+ TO VOUT- (V) FIGURE 16. IB vs V INPUT VOLTAGE RANGE FIGURE 17. COMMON MODE RANGE vs OUTPUT VOLTAGE VCMO CMO 15 80 AV = 1000 RIN = 30.1, RFB = 30.1k 10 60 RIN = 301 AV = 100 RFB = 30.1k V) 5 40 PUT V (CM 0 VVRCCFCOB === ++31300VkV;; ;RV VEINEO E= = =3 0 0-V1.10V GAIN (dB) 20 AAVV == 110 RIRN IN= =3 03..10k1,k R, FRBF =B =3 03.01.k1k IN -5 VCMO = 1.5V 0 AV = 0.1 -10 -20 RIN = 301k, RFB = 30.1k -15 -40 -4 -3 -2 -1 0 1 2 3 4 10 100 1k 10k 100k 1M 10M 100M VOUT+ TO VOUT- (V) FREQUENCY (H z) FIGURE 18. COMMON MODE RANGE vs OUTPUT VOLTAGE FIGURE 19. CLOSED LOOP GAIN (RFB = 30.1k) vs FREQUENCY) 80 160 AV = 1000 RIN = 121, RFB = 121k 140 AV = 1000 AV = 100 60 RIN = 1.21k 40 AV = 100 RFB = 121k )Bd 120 N (dB) 20 AV = 10 RIN = 12.1k, RFB = 121k ( RRSP 18000 GAI 0 AV = 1 RIN = 121k, RFB = 121k EVITISO 4600 AV = 0.1 AV = 1 AV = 0.1 P -20 20 AV = 10 RIN = 1.21M, RFB = 121k -40 0 10 100 1k 10k 100k 1M 10M 100M 1 10 10 0 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 20. CLOSED LOOP GAIN (RFB = 121k) vs FREQUENCY FIGURE 21. POSITIVE PSRR VEE AND VCC (RF = 30.1k) FN6562 Rev 3.00 Page 9 of 20 May 27, 2015

ISL28617 Typical Performance Curves V = V =15V, V = V = -15V, V = 0V, R = Open, unless otherwise specified. CC CO EE EO CM L 160 160 ) Bd( RRSP EVITAGE 111024468000000 AV = 0.1 AV = 1000A V = 1 AV = 100 ) Bd( RRSP EVITISO 111468024000000 AV = 0.1 AV = 1A0V0 0= 1 AV = 100 N P 20 AV = 10 20 AV = 10 0 0 1 10 10 0 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 22. NEGATIVE PSRR VEE AND VCC (RF = 30.1k) FIGURE 23. POSITIVE PSRR VEE AND VCC (RF = 121k) 160 180 AV = 1000 140 160 AV = 100 ) Bd 120 AV = 100 )B 140 AV = 1000 ( RR 100 d( R 120 S R 100 P EVITAGE 468000 AV = 0.1 AV = 1 SP EVITISO 6800 AV = 0.1 AV = 1 N 20 AV = 10 P 40 AV = 10 20 0 0 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 24. NEGATIVE PSRR VEE AND VCC (RF = 121k) FIGURE 25. POSITIVE PSRR VE0 AND VC0 (RF = 30.1k) 180 200 160 AV = 100 180 AV = 1000 ) B 140 AV = 1000 ) B 160 d( RRS 110200 d( RRS 112400 AV = 100 P EVITA 6800 AV = 0.1 AV = 1 P EVIT 10800 G IS 60 EN 2400 AV = 10 OP 2400 AV = 0.1 AV = 1 AV = 10 0 0 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 26. NEGATIVE PSRR V AND V (R = 30.1k) FIGURE 27. POSITIVE PSRR V AND V (R = 121k) EO CO F EO CO F FN6562 Rev 3.00 Page 10 of 20 May 27, 2015

ISL28617 Typical Performance Curves V = V =15V, V = V = -15V, V = 0V, R = Open, unless otherwise specified. CC CO EE EO CM L 160 140 AV = 1000 AV = 1000 140 120 ) Bd 120 AV = 100 )Bd 100 AV = 100 ( RRSP EVITAGEN 104680000 AV = 0.1 AV = 1 AV = 10 ( k1.03 = R RRMCBF 468000 AV = 0.1 AV = 1 AV = 10 20 20 0 0 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 28. NEGATIVE PSRR VE0 AND VCO (RF = 121k) FIGURE 29. CMRR RF = 30.1k 140 1000 10 120 AV = 1000 √Hz) INP ) Bd( k12 18000 AV = 100 TAGE (nV/ 100 iN 1 UT NOISE 1 = OL CU R RBF 60 AV = 0.1 OISE V 10 0.1 RREN RMC 40 AV = 1 UT N eN T (pA 20 AV = 10 INP /√Hz 0 1 0.01 ) 1 10 100 1k 10k 100k 1M 0.1 1 10 100 1k 10k 100 k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 30. CMRR R = 121k FIGURE 31. INPUT VOLTAGE AND CURRENT NOISE F FN6562 Rev 3.00 Page 11 of 20 May 27, 2015

ISL28617 INPUT FEEDBACK OUTPUT STAGE STAGE STAGE VCO VCC 0.1µF 0.1µF A5 +VOUT I1, I3 + I1 I2 I3 I4 I2, I4 -A6 -VOUT IN- 500Ω VFB- IN+ 500Ω VFB+ + + + + A1 Q1 Q2 A2 A3 Q3 Q4 A4 - - - - VCMO 100µA 100µA VEE IS1 IS2 IS3 IS4 VEO 0.1µF 0.1µF +RIN RIN -RIN +RFB RFB -RFB GND +RINSENSE -RINSENSE -RFBSENSE +RFBSENSE GAIN RESISTORS AND KELVIN CONNECTIONS FIGURE 32. ISL28617 FUNCTIONAL BLOCK DIAGRAM FN6562 Rev 3.00 Page 12 of 20 May 27, 2015

ISL28617 Applications Information A change in the input differential voltage causes an equivalent voltage drop across the input gain resistor R and the resulting IN “General Description” section: contains the ISL28617 functional current flow through R , causes an imbalance in Q1 and Q2 IN and performance objectives and description of operation. collector currents I and I , given by Equations1 and 2: 1 2 “Designing with the ISL28617” on page14 section: contains the I1 = 100A+VIN+–VIN-RIN (EQ. 1) application circuit design equations and guidelines for achieving the desired DC and AC performance levels. I2 = 100A–VIN+–VIN-RIN (EQ. 2) “Estimating Amplifier DC and Noise Performance” on page17 section: provides equations for predicting DC offset voltage and Feedback G Amplifier M noise of the finished design. The feedback amplifiers A3 and A4 form a differential General Description transconductance amplifier identical to the input stage. The input terminals (V , V ) connect to the ISL28617 differential FB+ FB- output terminals (+V , -V ), so that the output voltage also The ISL28617 Instrumentation Amplifier was developed to OUT OUT appears across the feedback gain resistor R . accomplish the following: FB Operation is the same as the input G stage and the differential • Provide a fully differential, rail-to-rail output for optimally M currents I and I are given by Equations3 and 4: driving ADCs. 3 4 • Limit the output swing to prevent output overdrive. I3 = 100A–+VOUT–-VOUTRFB (EQ. 3) • Allow any gain, including attenuation. I = 100A++V –-V R (EQ. 4) 4 OUT OUT FB • Maximize gain accuracy by removing on-chip component tolerances and external PC board parasitic resistance. Error Amplifier A5, Output Amplifier A6 • Enable user control of amplifier precision level with choice of (Figure32) external resistor tolerance. Amplifiers A5 and A6 act together to form a high gain, • Maintain CMRR>100dB and remove CMRR sensitivity to gain differential I/O trans impedance amplifier. Differential current resistor tolerance. amplifier A5 sums the differential currents (I + I and I + I ) 1 3 2 4 • Provide a level shift interface from bipolar analog input signal from the input and feedback G amplifiers. From that M sources to unipolar and bipolar ADC output terminations. summation, a differential error voltage is sent to A6, which generates the rail-to-rail differential output drive to the +V and Functional Description OUT -V pins. OUT Figure32 shows the functional block diagram for the ISL28617. The external connection of the output pins to the feedback Input G Amplifier amplifier closes a servo loop where a change in the differential M input voltage is converted into differential current imbalances at The input stage consists of high performance, wide band I and I (Equations1 and 2) at the summing node inputs to A5. 1 2 amplifiers A1, A2, GM drive transistors Q1, Q2 and input gain Current I1 sums with current I3 from the feedback stage and I2 resistor RIN. Current drive for Q1 and Q2 emitters are provided by sums with I4. A5 senses the difference between current pairs I1, matched pair of 100µA current sinks. A unity gain buffer from I and I , I . A difference voltage is generated, amplified and fed 3 2 4 each input (IN+, IN-) to the terminals of the input resistor, RIN, is back to the feedback amplifier, which creates correction currents formed by the connection of the Kelvin resistor sense pins and at I and I to match the currents at I andI (Equations3 and 4). 3 4 1 2 drive pins to the terminals of the input resistor, as shown in Figure32. In this configuration, the voltage across the input Therefore, at equilibrium: resistor RIN is equal to the input differential voltage across IN+ I1= I3and I2= I4 (EQ. 5) and IN-. The input GM stage operates by creating a current difference in Combining Equations1 and 3, (and their complements I2 and I4) the collector currents Q1 and Q2 in response to the voltage and solving for VOUT as a function of VIN, RIN and RFB, yields difference between the IN+ and IN- pins. When the input voltage Equation6: applied to the IN+ and IN- pins is zero, the voltage across the VOUT= VINRFBRIN (EQ. 6) terminals of the gain resistor R , is also zero. Since there is no IN Where V = +V –-V  and V = IN+–IN- current flow through the gain resistor, transistors Q1 and Q2 OUT OUT OUT IN collector currents I and I are equal. 1 2 Equation6 can be rearranged to form the gain, see Equation7: Gain = V V = R R (EQ. 7) OUT IN FB IN Which is general form of the gain equation for the ISL28617. FN6562 Rev 3.00 Page 13 of 20 May 27, 2015

ISL28617 Designing with the ISL28617 Setting the Input Gain Resistor R IN (Figures32, 33) To complete a working design, the following procedure is recommended: The input gain resistor RIN is scaled to the feedback resistor according to the gain shown by Equation9: 1. Define the output voltage swing (EQ. 9) R = R Gain 2. Set the feedback resistor value, R IN FB FB 3. Set the input gain resistor value, RIN The input GM stage uses the same differential current source 4. Set the V , V power supply voltages arrangement as the feedback stage. Therefore, the amount of CO EO overdrive margin (50%, 80%) included in the calculation for R 5. Set the V and V supply voltages FB CC EE is also included in the calculation for R . IN The gain of the instrumentation amplifier is set by the resistor ratio R /R (Equation7) and the maximum output swing is set Input Stage Overdrive Considerations FB IN by the absolute value of the feedback resistor R (Equation8). FB (Figure34) V and V supply power to the rail-to-rail output stage and CO EO define the maximum output voltage swing at the ±V There are a few cases where the input stage can be overdriven, OUT differential output pins. Power supply pins V and V power the which must be considered in the application. An input signal that CC EE feedback amplifiers, which require an additional ±3V beyond the exceeds the maximum dynamic range of the gain resistor RIN, V and V voltages to maintain linear operation of the calculated previously, can cause the ESD diodes to conduct. CO EO feedback G stage. When this occurs, a low impedance path from the inputs to the M input gain resistor R will result in signal distortion. IN Setting the Feedback Gain Resistor R FB High-speed input signals that remain within the maximum (Figures32, 33) dynamic range of the input stage can cause distortion if the input Resistor R defines the maximum differential voltage at output slew rate exceeds the input stage slew rate (~4V/µs). When the FB terminals +VOUT to -VOUT. External resistor RFB and the differential input slews at a faster rate than the GM stage can follow, the 100µA current sources define the maximum dynamic range of voltage difference appears across the input ESD diodes from the feedback stage, which defines the maximum differential each input and resistor RIN. When the voltage difference is large output swing of the output stage. Overload circuitry allows enough to cause the diodes to conduct, the input terminals are >100µA to flow through RFB to maintain feedback, but linearity is shunted to RIN through the 500Ωinput protection resistors, degraded. Therefore, it is a good practice to keep the maximum causing distortion during the rise and fall times of the transient linear dynamic range to within ±80% of the maximum I*R across pulse. The distortion will last until the resistor voltage catches up the resistor. to the input voltage. (EQ. 8) V DIFF = ±80 R OUT A FB 500Ω In cases where large pulse overshoot is expected, the maximum IN- current in Equation8 could be reduced to 50% for additional VCC margin (see “AC Performance Considerations” on page16). The penalty for increasing the feedback resistor value is higher DC 500Ω IN+ + + offset voltage and noise. A1 Q1 Q2 A2 - RIN - Output voltages that exceed the maximum dynamic range of the ESD ESD feedback amplifier can degrade phase margin and cause PROTECTION PROTECTION instability. The plot in Figure33 shows the maximum differential output voltage swing vs resistor value for R and R using the FB IN 100µA 100µA 80% and 50% current source levels. V) 35 ± E ( 30 VEE G AN 25 FIGURE 34. INPUT STAGE ESD PROTECTION DIODES R GE 20 VOUT (V) AT 80% Setting the Power Supply Voltages A LT 15 The ISL28617 power supplies are partitioned so that the input stage O C V 10 and feedback stages are powered from a separate pair of supply AMI 5 VOUT (V) AT 50% pins (VCC, VEE) than the differential output stage (VCO,VEO). This N partitioning provides the user with the ability to adapt the ISL28617 Y D 0 to a wide variety of input signal power sources that would not be 0 50 100 150 200 250 300 350 400 possible if the supplies were strapped together internally (V = V RFB, RIN VALUE (kΩ) CC CO and V = V ). However, powering the input and output supplies EE EO FIGURE 33. R , R vs DYNAMIC RANGE FB IN from unequal supplies has restrictions that are described in the next section. FN6562 Rev 3.00 Page 14 of 20 May 27, 2015

ISL28617 Powering the Input and Feedback Stages Power Supply Voltages by Application (V , V ) CC EE The ISL28617 can be adapted to a wide variety of The input pins IN+, IN- cannot swing rail-to-rail, but have a instrumentation amplifier applications where the signal source is maximum input voltage range given by Equation10: powered from supply voltages that are different from the supply voltages powering downstream circuits. The following examples (EQ. 10) V +3VV IN+V V –3V EE CMIR IN CC are included as a guide to the proper connection and voltages Where VIN = maximum differential voltage IN+ to IN- applied to the supply pins V , V , V and V . CC EE CO EO This requires the sum of the common mode input voltage and There are a common set of requirements across all power the differential input voltage to remain within 3V of either the V applications: CC or V rail, otherwise distortion will result. EE 1. A common ground connection from the input supplies, (V , CC The feedback pins VFB+ and VFB- have the same input common VEE) to the output supplies (VCO, VEO) is required for all mode voltage constraint as the input pins IN+ and IN-. The powering options. maximum input voltage range of the feedback pins is given by 2. The signal input pins IN+ and IN- cannot float and must have Equation11: a DC return path to ground. VEE+3VVCMIRFBVCC–3V (EQ. 11) 3. The input and output supplies cannot both be operated in single supply mode due to the 3V feedback amplifier Where V FB = +V –-V +V CMIR OUT OUT CMO common mode headroom requirement in Equation11. To maintain stability, it is critical to respect the ±3V requirement The following are typical power examples: in Equation11. EXAMPLE 1: BIPOLAR INPUT TO SINGLE SUPPLY Powering the Rail-to-rail Output Stage OUTPUT (V , V ) The ISL28617 is configured as a 5V ADC driver in a high-gain CO EO sensor bridge amplifier powered from a ±10V excitation source. The output stage (A6) is of rail-to-rail design and is powered by the The sensor signal output is at a much lower voltage level. In this V and V pins. The differential output pins +V and -V CO EO OUT OUT application, the ISL28617 must extract the low-level bipolar connect to the V + and V - pins to close the output feedback FB FB sensor signal and shift the level to the 0V to +5V differential loop. The feedback stage is powered from V and V pins. The CC EE rail-to-rail signal needed by the ADC. The following powering V + and V - have a common mode input range 3V below the V FB FB CC option is recommended: rail and 3V above the and V rail. If the output voltage exceeds the EE feedback common mode input voltage, loop instability will result. • V = +10V, V = -10V CC EE Therefore, the voltages at the ±V pins should always be 3V OUT • V = +5V, V = GND away from either rail, as shown in Equation12: CO EO • V = +2.5V V +3VV V –3V CMO EE OUT CC Where V = +V or -V (EQ. 12) • VCC and VEE power supply common connects to GND OUT OUT OUT EXAMPLE 2: HIGH VOLTAGE BIPOLAR I/O BUFFER Rail-to-rail Differential ADC Driver The ISL28617 is configured as a high impedance buffer The differential output stage of ISL28617 is designed to drive the instrumentation amplifier in a ±15V industrial sensor application. In differential input stage of an ADC. In this configuration, the V this application, the ISL28617 must extract and amplify the high CO and V power supply pins connect directly to the ADC power impedance sensor signal and send it downstream to a differential EO supply pins. This output swing arrangement is ideal for driving ADC operating from ±15V supplies. The following powering options rail-to-rail ADC drive without the possibility of overdriving the ADC are recommended: input. 1. Input and output supplies are strapped to the same supplies and The output stage is capable of rail-to-rail operation when V and rail-to-rail input to the ADC is not required. CO VEO are powered from a single supply or from split supplies. It - VCC = VCO = +15V has a single supply voltage range (V ) from 3V to 15V (with V CO EO - V = V = -15V EE EO at GND) and a ±1.5V to ±15V split supply voltage range. Under all - V = GND power supply conditions, V must be greater than V by 3V and CMO CC CO - V , V power supply common connects to GND V must be less than V by 3V to maintain the rail-to-rail output CC EE EE EO drive capability. and VOUT = ±12V The V pin is an input to a very low bias current terminal and 2. ±15V Rail-to-rail output is required, then: CMO sets the output common mode reference voltage when driving a - V = +18V, V = -18V CC EE differential input ADC, such that the output would have a ± input - V = +15V, V = -15V CO EO signal span centered around an external DC reference voltage - V = GND applied to the V pin. CMO CMO - V and V power supply common connects to GND CC EE FN6562 Rev 3.00 Page 15 of 20 May 27, 2015

ISL28617 The V and V power supply pins connect to the ADC (±15V) power AC Compensation Techniques CO EO supply pins. Rail-to-rail output swing requires that V =V +3V and CC CO The input compensation with a low pass filter (Figure35) can be V = V -3V, or ±18V. EE EO an effective way to block high frequency signals from the EXAMPLE 3: GAINS LESS THAN 1 differential amplifier inputs. It does not change the gain peaking behavior of the feedback loop, but it does block signals from The ISL28617 is configured to a gain of 0.2V/V driving a creating overdrive instability. This method is useful after other rail-to-rail 3V ADC. In this application, the maximum input corrective measures have been implemented and when there is dynamic range is ±15V. little control over the input signal frequency content. - V = +18V, V = -18V CC EE - V = +3V, V = GND CO EO R/2 IN- 500Ω - V = +1.5V CMO - V , V power supply common connects to GND DIFFERENTIAL CC EE INPUT SIGNAL In this attenuator configuration, the input signal range is ±15V, C which requires an additional ±3V of input overhead from the R/2 IN+ 500Ω input supplies. Thus, V and V = ±18V. CC EE COMMON AC Performance Considerations MODE ERROR TRACE The ISL28617 closed loop frequency response is formed by the CAPACITANCE feedback GM amplifier and gain resistor RFB and has the GND characteristics of a current feedback amplifier. Therefore, the -3dB gain does not significantly decrease at high gains as is the case with the constant gain-bandwidth response of the classic FIGURE 35. INPUT DIFFERENTIAL LOW PASS FILTER AND voltage feedback amplifier. PARASITIC CAPACITANCE There are four behaviors of current feedback amplifiers that Input Common Mode Rejection must be considered: Considerations • Frequency response increases with decreasing values of R . FB The ISL28617 is capable of a very high level (120dB) of CMRR Acomparison of the G = 100, -3db response (Figures19, 20) R at 30.1kΩvs 121kΩshows almost a 4x decrease from performance from DC to as high as 1kHz. (Figure1; CMRR vs FB 2MHz to 0.5MHz. Frequency). This high level of performance over frequency is made possible by the high common mode input impedance • Gain peaking tends to increase with decreasing values of RFB. (80GΩ but requires careful attention to the matching of the • Wide band applications at gains less than 1 (Figures19, 20) IN+and IN- external impedances to GND. can have high gain peaking resulting in high levels of A mismatch in the series impedance in conjunction with parasitic overshoot with pulsed input signals. capacitance at the IN+ and IN- terminals (Figure35) will cause a • Parasitic capacitance at the feedback resistor terminals common mode amplitude imbalance that will show up as a (+R ,-R ) and the Kelvin sense terminals (+R SENSE, differential input signal, rapidly degrading CMRR as the common FB FB FB -R SENSE) will result in increasing levels of peaking and mode frequency increases. FB transient response overshoot. Maximum CMRR performance is achieved with attention to To minimize peaking external PC parasitic capacitance should be balancing external components and attention to PC layout. minimized as much as possible. The ISL28617 is designed to be Layout Guidelines stable with PC board parasitic capacitance up to 20pF and feedback resistor values down to 30.1kΩ. At gains less than 1, The ISL28617 is a high precision device with wide band AC the maximum parasitic capacitance may have to be limited performance. Maximizing DC precision requires attention to the further to avoid additional compensation. layout of the gain resistors. Achieving good AC response requires Uncorrected gain peaking and high overshoot in the feedback attention to parasitic capacitance at the gain resistor terminals stage can cause loss of feedback loop stability if the transient and CMRR performance over frequency is ensured with causes the feedback voltage to exceed the common mode input symmetrical component placement and layout of the input range of the feedback amplifier or the maximum linear range of differential signals to the IN+ and IN- terminals. the feedback resistor R . Corrective actions include increasing FB To ensure the highest DC precision, the location of the gain the size of the feedback resistor (see Figure33) and rescaling resistors and PC trace connections to the Kelvin connections are the input gain resistor R , or adding input frequency IN most important. Proper Kelvin connections remove trace compensation described in the next section. resistance errors so that the amplifier gain accuracy and gain temperature coefficients are determined by the gain resistor The penalty of increasing the R (and R rescaling) is increased FB IN noise, so this is generally not the corrective action of choice. matching tolerance. Interconnect constraints preclude mounting the gain resistors next to each other, so they should be located on either side of the ISL28617 and as close to the device as FN6562 Rev 3.00 Page 16 of 20 May 27, 2015

ISL28617 possible. The Kelvin connections are formed at the junction of Equation15 converts the output offset error range (Equation13) the sense pins (±RINSENSE, ±RFBSENSE) and the gain resistor to an input referred error range [VOS(RTI)] and enables a current drive terminals (±RIN, ±RFB) terminals. This junction comparison with the DC component of the input signal. should be made at the terminal pads directly under the ends of (EQ. 15) each resistor. V RTI= V +V A +I R A  OS OS(I) OS(FB) V ERR FB V Reduced trace lengths that maintain DC accuracy are also important for minimizing the capacitance that can degrade AC Similarly, Equation16 shows the typical DC offset value stability. This is especially true at gains less than 1. Layout (Equation14) referred to the input. techniques for precision applications using larger size precision gain resistors at very low gains (G=0.1V/V) include removing a V RTITYP=√V 2+V A 2 +I R A 2 OS OS(I) OS(FB) V ERR FB V section of the underlying PC ground plane directly under the gain (EQ. 16) resistor terminals and body. Layout guidelines for high CMRR include matching trace lengths NOTE: These results are summarized in Table1. and symmetrical component placement on the circuit that Calculating Noise Voltage connects the signal source to the IN+ and IN- pins. This ensures matching of the IN+ and IN- input impedances (Figure35). The calculation of noise spectral density at the output [eN(RTO)] from all noise sources is given by Equations17 and 18: Power Supply Decoupling 2 2 e RTO= √A e I +2A i I500 + Standard power supply decoupling consists of a single 0.1µF N V N V N 2 2 2 50Vceramic capacitor at the power supply terminals located as AV 4kTRIN+4kTRFB+RFBiNIERR +eNFB  close to the device as possible. In applications where the input (EQ. 17) and output supplies are strapped to the same voltage (V = V , EE EO V = V ) the connection point should be as close to the device Then converts the output noise to the input referred value when CC CO as possible, with a single 0.1µF 50V ceramic capacitor at the evaluating the input signal to noise ratio. junction. Applications using separate supplies require 0.1µF 50V e RTI=e RTOA (EQ. 18) ceramic decoupling capacitors at each power supply terminal. N N V Table2 provides examples of the noise contribution of each Estimating Amplifier DC and source by circuit gain and output voltage span. In a high-gain Noise Performance configuration, the input noise is the dominant noise source. In a low-gain configuration, the noise voltage from the product of the The gain resistor ohmic values and ratios are all that is required internal noise current, I and the feedback resistor, R N(err) FB to estimate DC offset and noise. The following sections illustrate dominates. The contribution of the internal noise current, I N(err) methods to calculate DC offset and noise performance. These increases in proportion to R but the corresponding increase in FB, estimates are useful for optimizing resistor values for noise and output voltage with R keeps the ratio of this noise voltage to FB DC offset. output voltage constant. Calculating DC Offset Voltage Output offset voltage, like output noise, has several contributors. Also similar to output noise, the major offset contributor depends on the gain configuration. In high-gain, V dominates, while in OS(I) low-gain, offset due to I dominates. ERR The summation of DC offsets to arrive at total DC offset error is performed in two ways. Equation13 is a simple addition of the DC offsets appearing at the output and is useful when defining the minimum to maximum range of offset that can be expected. The drawback is that the result defines the corner of the corner of the error box and not a typical value given that these sources are uncorrelated. V RTO= A V +V +I R  (EQ. 13) OS V OS(I) OS(FB) ERR FB Equation14 expresses the total DC error as the rms, or square root of the sum of the squares to provide an estimate of a typical value. 2 2 2 V RTOTYP=√A V  +V  +I R   OS V OS(I) OS(FB) ERR FB (EQ. 14) FN6562 Rev 3.00 Page 17 of 20 May 27, 2015

ISL28617 TABLE 1. COMPUTING TYPICAL OUTPUT OFFSET VOLTAGE RANGES TYPICAL TYPICAL A x V (I) V (FB) I (5nA) x R V (RTO) V (RTI) V (RTO) V (RTI) V OS OS ERR FB OS OS OS OS R R (µV) (µV) (µV) (µV) (µV) (µV) (µV) IN FB A V (kΩ) (kΩ) (Note11) (Note11) (Note11) (Equation13) (Equation15) (Equation14) (Equation16) V O(LIN) 1 ±2.5 30 30 ±30 ±400 ±150 ±580 428 1 ±10 120 120 ±15 ±400 ±600 ±1015 721 100 ±2.5 0.3 30 ±1500 ±400 ±150 ±2000 ±20 1560 15.6 100 ±10 1.2 120 ±1500 ±400 ±600 ±2500 ±25 1669 16.7 NOTE: 11. Chosen for illustration purposes and does not reflect actual device performance. TABLE 2. 1kHz INPUT NOISE AND THERMAL NOISE CONTRIBUTIONS e (RTO) e (RTI) N N OUTPUT INPUT 2 x A x i REFERRED REFERRED V N(I) R R A x e (I) x 500 A x √(4kT x R √(4kT x R R x i (I ) e (FB) NOISE NOISE IN FB V N V IN) FB) FB N ERR N A (kΩ) (kΩ) (nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) V 1 30 30 8.6 0.15 22.3 22.3 78 8.6 86 1 120 120 8.6 0.15 44.6 44.6 300 8.6 307 100 0.3 30 860 15 223 22.3 78 8.6 892 8.9 100 1.2 120 860 15 446 44.6 300 8.6 1015 10.15 NOTE: 12. e and i values are chosen for illustration purposes and may not reflect actual device performance. N N FN6562 Rev 3.00 Page 18 of 20 May 27, 2015

ISL28617 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE May 27, 2015 FN6562.3 The units of the Y axis on Figures8, 9, 14, 15 changed from "mV" to “µA” and Figure16 changed from "mA" to "µA. On page15, under EXAMPLE 1, added the following after the first sentence: “The sensor signal output is at a much lower voltage level”. November 17, 2014 FN6562.2 Corrected Typo under “Recommended Operating Conditions” on page4 from “V to V ”. E+ EO Removed Important note (All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T ) on page4 as Note6 covers this. J C A Updated About Intersil verbiage. October 17, 2013 FN6562.1 Added a description to the “Related Literature” on page1. “Thermal Information” on page4: Added theta jc (top) = 28C/W. Added two new graphs for common mode range vs output voltage (Figure 17 and 18). May 25, 2012 FN6562.0 Initial release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2012-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6562 Rev 3.00 Page 19 of 20 May 27, 2015

ISL28617 Package Outline Drawing M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 24 13 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 C B A 1 12 +0.05 0.65 B 0.15 -0.06 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90+0.15 -0.10 1.20 MAX GAUGE SEATING PLANE PLANE 0.25 0.25+0.05 5 -0.06 0°-8° 0.10C 0.10MCBA 0.05 MIN 0.15 MAX 0.60± 0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN6562 Rev 3.00 Page 20 of 20 May 27, 2015