DATASHEET ISL28113, ISL28213, ISL28413 FN6728 Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifier Rev 8.00 April 8, 2015 The ISL28113, ISL28213 and ISL28413 are single, dual and Features quad channel general purpose micropower, rail-to-rail input and output operational amplifiers with supply voltage range of • Low current consumption. . . . . . . . . . . . . . . . . . . . . . . .130µA 1.8V to 5.5V. Key features are a low supply current of 130µA • Wide supply range. . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V maximum per channel at room temperature, a low bias • Gain bandwidth product . . . . . . . . . . . . . . . . . . . . . . . . . .2MHz current and a wide input voltage range, which enables the ISL28x13 devices to be excellent general purpose operational • Input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . .20pA, Max. amplifiers for a wide range of applications. • Operating temperature range. . . . . . . . . . . .-40°C to +125°C The ISL28113 is available in the SC70-5 and SOT23-5 • Packages packages, the ISL28213 is in the MSOP8, SOIC8, SOT23-8 - ISL28113 (Single) . . . . . . . . . . . . . . . . . . .SC70-5, SOT23-5 packages and the ISL28413 is in the TSSOP14, SOIC14 - ISL28213 (Dual). . . . . . . . . . . . . . MSOP8, SOIC8, SOT23-8 packages. All devices operate across the extended - ISL28413 (Quad) . . . . . . . . . . . . . . . . . . . SOIC14, TSSOP14 temperature range of -40°C to +125°C. Applications Related Literature • Power supply control/regulation • See AN1519 for “ISL28213/14SOICEVAL2Z Evaluation Board User’s Guide” • Process control • See AN1520 for “ISL28113/14SOT23EVAL1Z Evaluation • Signal gain/buffers Board User’s Guide” • Active filters • See AN1542 for “ISL28213/14MSOPEVAL2Z Evaluation • Current shunt sensing Board User’s Guide” • Transimpedance amps RF 100kΩ LOAD +5V RIN- IN- - RSENSE 10kΩ V+ VOUT ISL28x13 RIN+ IN+ + V- 10kΩ GAIN = 10 RREF+ 100kΩ VREF SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER FIGURE 1. TYPICAL APPLICATION FN6728 Rev 8.00 Page 1 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Ordering Information PART NUMBER PART PACKAGE PKG. (Note4) MARKING (RoHS Compliant) DWG.# ISL28113FEZ-T7 (Notes1, 2) BJA (Note5) 5 Ld SC-70 P5.049 ISL28113FEZ-T7A (Notes1, 2) BJA (Note5) 5 Ld SC-70 P5.049 ISL28113FHZ-T7 (Notes1, 2) BCYA (Note5) 5 Ld SOT-23 P5.064A ISL28113FHZ-T7A (Notes1, 2) BCYA (Note5) 5 Ld SOT-23 P5.064A ISL28213FUZ (Note2) 8213Z 8 Ld MSOP M8.118A ISL28213FUZ-T7 (Notes1, 2) 8213Z 8 Ld MSOP M8.118A ISL28213FBZ (Note2) 28213 FBZ 8 Ld SOIC M8.15E ISL28213FBZ-T7 (Notes1, 2) 28213 FBZ 8 Ld SOIC M8.15E ISL28213FBZ-T13 (Notes1, 2) 28213 FBZ 8 Ld SOIC M8.15E ISL28213FHZ-T7 (Notes1, 3) BEKA (Note5) 8 Ld SOT-23 P8.064 ISL28213FHZ-T7A (Notes1, 3) BEKA (Note5) 8 Ld SOT-23 P8.064 ISL28413FVZ (Note2) 28413 FVZ 14 Ld TSSOP MDP0044 ISL28413FVZ-T7 (Notes1, 2) 28413 FVZ 14 Ld TSSOP MDP0044 ISL28413FVZ-T13 (Notes1, 2) 28413 FVZ 14 Ld TSSOP MDP0044 ISL28413FBZ (Note2) 28413 FBZ 14 Ld SOIC MDP0027 ISL28413FBZ-T7 (Notes1, 2) 28413 FBZ 14 Ld SOIC MDP0027 ISL28413FBZ-T13 (Notes1, 2) 28413 FBZ 14 Ld SOIC MDP0027 ISL28113SOT23EVAL1Z Evaluation Board ISL28213MSOPEVAL2Z Evaluation Board ISL28213SOICEVAL2Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page forr ISL28113, ISL28213, ISL28413. For more information on MSL please see Techbrief TB363. 5. The part marking is located on the bottom of the part. Pin Configurations ISL28113 ISL28113 ISL28213 (5 LD SC-70) (5 LD SOT-23) (8 LD MSOP, 8 LD SOIC, 8 LD SOT-23) TOP VIEW TOP VIEW TOP VIEW IN+ 1 5 VS+ OUT 1 5 VS+ OUT_A 1 8 VS+ VS- 2 VS- 2 IN-_A 2 7 OUT_B IN- 3 4 OUT IN+ 3 4 IN- IN+_A 3 6 IN-_B VS- 4 5 IN+_B FN6728 Rev 8.00 Page 2 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Pin Configurations (Continued) ISL28413 (14 LD TSSOP, 14 LD SOIC) TOP VIEW OUT_A 1 14 OUT_D IN-_A 2 13 IN-_D IN+_A 3 12 IN+_D VS+ 4 11 VS- IN+_B 5 10 IN+_C IN-_B 6 9 IN-_C OUT_B 7 8 OUT_C Pin Descriptions PIN NUMBER 8 LD MSOP, 5 LD 5 LD 8LD SOIC, 14 LD TSSOP, PIN NAME SC-70 SOT-23 8LDSOT-23 14 LD SOIC DESCRIPTION OUT 4 1 V+ OUT_A 1 1 OUT OUT_B 7 7 Output OUT_C 8 V- CIRCUIT 1 OUT_D 14 VS- 2 2 4 11 V+ CAPACITIVELY Negative supply voltage TRIGGERED ESDCLAMP V- CIRCUIT 2 IN+ 1 3 V+ IN+_A 3 3 IN+_B 5 5 Positive Input IN- IN+ IN+_C 10 IN+_D 12 IN- 3 4 V- Negative Input CIRCUIT 3 IN-_A 2 2 IN-_B 6 6 IN-_C 9 IN-_D 13 VS+ 5 5 8 4 Positive supply voltage See “CIRCUIT 2” FN6728 Rev 8.00 Page 3 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Absolute Maximum Ratings Thermal Information (TA = +25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs 5 Ld SC-70 (Notes 6, 7) . . . . . . . . . . . . . . . . 250 N/A Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA 5 Ld SOT-23 (Notes 6, 7) . . . . . . . . . . . . . . . 225 N/A Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V 8 Ld MSOP (Notes 6, 7). . . . . . . . . . . . . . . . 180 100 Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V 8 Ld SOIC Package (Notes 6, 7) . . . . . . . . . 126 90 ESD Rating 8 Ld SOT-23 (Notes 6, 7) . . . . . . . . . . . . . . . 240 168 Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000V 14 Ld TSSOP Package (Notes 6, 7) . . . . . . 120 40 Machine Model 14 Ld SOIC Package (Notes 6, 7). . . . . . . . 90 50 ISL28113, ISL28213. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V Ambient Operating Temperature Range. . . . . . . . . . . . . .-40°C to +125°C ISL28413. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2000V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is the top of the package. Electrical Specifications VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C, unless otherwise specified. MIN MAX PARAMETER DESCRIPTION TEST CONDITIONS (Note8) TYP (Note8) UNIT DC SPECIFICATIONS VOS Input Offset Voltage -4 0.5 4 mV -5 5 mV TCVOS Input Offset Voltage Temperature -40°C to +125°C 5 µV/°C Coefficient IOS Input Offset Current 1 30 pA IB Input Bias Current ISL28113 -20 3 20 pA -100 100 pA ISL28213, ISL28413 -20 3 20 pA -50 50 pA Common Mode Input - 0.1V +5.1V V Voltage Range ZIN Input Impedance 1012 Ω CIN Input Capacitance 1 pF CMRR Common Mode Rejection Ratio VCM = -0.1V to 5.1V 72 dB -40°C to +125°C 70 dB PSRR Power Supply Rejection Ratio VS = 1.8V to 5.5V 71 dB -40°C to +125°C 70 dB VOH Output Voltage Swing, High RL = 10kΩ 4.985 4.993 V 4.98 V VOL Output Voltage Swing, Low RL = 10kΩ 13 15 mV 20 mV V+ Supply Voltage 1.8 5.5 V IS Supply Current per Amplifier RL = OPEN 90 130 µA 170 µA FN6728 Rev 8.00 Page 4 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Electrical Specifications VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C, unless otherwise specified. (Continued) MIN MAX PARAMETER DESCRIPTION TEST CONDITIONS (Note8) TYP (Note8) UNIT ISC+ Output Source Short Circuit Current RL = 10Ω to V- -22 mA ISC- Output Sink Short Circuit Current RL = 10Ω to V+ 16 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product VS = ±2.5V 2 MHz AV = 100, RF = 100kΩ RG=1kΩRL = 10kΩto VCM eN VP-P Peak-to-Peak Input Noise Voltage VS = ±2.5V 14 µVP-P f = 0.1Hz to 10Hz eN Input Noise Voltage Density VS = ±2.5V 55 nV/√(Hz) f = 1kHz VS = ±2.5V 29 nV/√(Hz) f = 10kHz iN Input Noise Current Density VS = ±2.5V 5 fA/√(Hz) f = 1kHz Cin Differential Input Capacitance VS = ±2.5V 1.0 pF f = 1MHz Common Mode Input Capacitance 1.3 pF TRANSIENT RESPONSE SR Slew Rate 20% to 80% VOUT VOUT = 0.5V to 4.5V 1 V/µs tr, tf, Small Signal Rise Time, tr 10% to 90% VS = ±2.5V 100 ns AV = +1, VOUT = 0.05VP-P Fall Time, tf 10% to 90% RF=0ΩRL = 10kΩCL=15pF 115 ns ts Settling Time to 0.1%, 4VP-P Step VS = ±2.5V 7.5 µs AV = +1, RF = 0ΩRL=10kΩ CL= 1.2pF NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN6728 Rev 8.00 Page 5 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. 50 10,000 40 V+ = ±2.5V 30 Hz) AV = 1  20 V/ n 1000 A) 10 E ( p G (S 0 TA A L IBI -10 E VO 100 -20 S OI -30 N T -40 SIMULATION PU -50-40 -20 0 20 40 60 80 100 120 140 IN 101 10 100 1k 10k 100k TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 3. INPUT NOISE VOLTAGE SPECTRAL DENSITY 120 20 120 20 100 0 100 0 OP GAIN (dB) 24680000 GAIN ----86420000 ASE (°) OP GAIN (dB) 24680000 GAIN ----86420000 ASE (°) OPEN-LO--42000 RV+L == ±100.09kV PHASE ---111420000PH OPEN-LO--42000 RV+L == ±120.05kV PHASE ---111420000PH CL = 10pF CL = 10pF -60 SIMULATION -160 -60 SIMULATION -160 -80 -180 -80 -180 0.1 1 10 100 1k 10k 100k 1M 10M 100M 0.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL=100kΩ FIGURE 5. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL=100kΩ CL = 10pF, VS=±0.9V CL = 10pF, VS = ±2.5V 80 80 PSRR- VS = ±2.5V 70 70 PSRR- VS = ±0.9V 60 60 CMRR (dB) 345000 PSRR (dB) 345000 PSRR+ PVSSR =R ±+0 . 9VVS = ±2.5V RL = INF 20 20 CL = 4pF 10 10 AV = +1 SIMULATION VCM = 100mVP-P 0 0 0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 6. CMRR vs FREQUENCY, VS = ±2.5 FIGURE 7. PSRR vs FREQUENCY, VS = ±0.9V, ±2.5V FN6728 Rev 8.00 Page 6 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 70 1 60 AV = 1000 Rg = 100, Rf = 100k 0 Rg = 1k, Rf = 100k B) -1 50 d B) 40 AV = 100 VC+L == ±42p.F5V GAIN ( --32 VOUT = 10mVP-P GAIN (d 2300 AV = 10 VROL U=T 1 =0 k50mVP-P ALIZED --54 VVOOUUT T= = 1 5000mmVVPP--PP 10 Rg = 10k, Rf = 100k ORM -6 VCSL == ±42p.F5V VVOOUUTT == 520000mmVVPP--PP 0 AV = R1 g = OPEN, Rf = 0 N --87 ARVL == +101k VOUT = 1VP-P -10 -9 10 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 9. FREQUENCY RESPONSE vs VOUT 1 14 0 12 VS = ±2.5V RL = 10k B) -1 B) 10 AV = +1 CL = 1004pF N (d -2 RL = 49.9k N (d 8 VOUT = 50mVP-P CL = 474pF ZED GAI --43 RRLL = = 4 1.909kk ZED GAI 46 CL = 224pF MALI --65 V+ = ±2.5V RL = 1k MALI 2 CL = 104pF NOR -7 ACVL == +4p1F RL = 499 NOR 0 CL = 26pF --98 VOUT = 50mVP-P RL = 100 --42 CL = 4pF 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 10. GAIN vs FREQUENCY vs RL FIGURE 11. GAIN vs FREQUENCY vs CL 1 140 0 120 B) -1 d ALIZED GAIN ( ----5432 VS = ±2.5V OSS-TALK (dB) 1680000 VRSL -=D R±2IV.5EVR = INF NORM --76 CRAVLL === +140p1kF VVSS == ±±11..7255VV CR 2400 RACVLL - ==R E+4p1CFEIVER = 10k -8 VOUT = 50mVP-P VS = ±0.9V VSOURCE = 1VP-P -9 0 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 13. CROSSTALK, VS= ±2.5V FN6728 Rev 8.00 Page 7 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 30 3 20 2 VS = ±2.5V V) V) m 10 L ( 1 ALL SIGNAL ( -100 RACVVVOSLL U====T +±11 =2051 .kp55F0VmVP-P ARGE SIGNA-10 RACVVLL S=== =+11 501±pk0F.9V SM L VOUT = RAIL -20 -2 -30 -3 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) TIME (µs) FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE, VS=±2.5V FIGURE 15. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS=±0.9V, ±2.5V 0.1 0.5 0.6 3.0 0 INPUT 0 0.5 OUTPUT AT VS = ±2.5V 2.5 INPUT (V) ---000...321 OUTPUT RACRAVLLfT = ===V 1 9S1I0N.5=0Fp9±k0F,. 9RVg = 1k ---110...505 OUTPUT (V) INPUT (V) 000...234 OUTPUT AT VS RACR= VLLf± =0=== .1 991I0N.V50F p9kF, Rg = 1k 112...050 OUTPUT (V) -0.4 OUTPUT AT VS = ±2.5V -2.0 0.1 0.5 -0.5 -2.5 0 0 INPUT -0.6 -3.0 -0.1 -0.5 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) TIME (µs) FIGURE 16. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, FIGURE 17. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS=±0.9V, ±2.5V VS=±0.9V, ±2.5V 100 VS = ±2.5V 90 RL = 10k 80 AV = 1 VOUT = 50mVP-P %) 70 RSHOOT ( 456000 OVERSHOOTO+V E R S H O O T- E V O 30 20 10 0 1 10 100 1000 10000 CAPACITANCE (pF) FIGURE 18. % OVERSHOOT vs LOAD CAPACITANCE, VS= ±2.5V FN6728 Rev 8.00 Page 8 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Applications Information Power Dissipation It is possible to exceed the +125°C maximum junction Functional Description temperatures under certain load, power supply conditions and The ISL28113, ISL28213 and ISL28413 are single, dual and ambient temperature conditions. It is therefore important to quad, CMOS rail-to-rail input, output (RRIO) micropower calculate the maximum junction temperature (TJMAX) for all operational amplifiers. They are designed to operate from single applications to determine if power supply voltages, load supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts conditions, or package type need to be modified to remain in the have an input common mode range that extends 100mV above safe operating area. These parameters are related using and below the power supply voltage rails. The output stage can Equation1: swing to within 15mV of the supply rails with a 10kΩload. T = T + xPD (EQ. 1) JMAX MAX JA MAXTOTAL Input ESD Diode Protection Where: All input terminals have internal ESD protection diodes to both • PDMAXTOTAL is the sum of the maximum power dissipation of positive and negative supply rails, limiting the input voltage to each amplifier in the package (PDMAX) within one diode beyond the supply rails (see “Pin Descriptions-Circuit 1” on page3). For applications where the • PDMAX for each amplifier can be calculated using Equation2: input voltage may exceed either power supply voltage by 0.5V or V OUTMAX PD = V I +V - V ---------------------------- more, an external series resistor must be used to ensure the input MAX S qMAX S OUTMAX R (EQ. 2) L currents never exceed 20mA (see Figure19). Where: RF • TMAX = Maximum ambient temperature V+ •JA = Thermal resistance of the package RIN- - • PDMAX = Maximum power dissipation of 1 amplifier VIN- • VS = Total supply voltage RIN+ + RL • IqMAX = Maximum quiescent supply current of 1 amplifier RG • VOUTMAX = Maximum output voltage swing of the application V- • RL = Load resistance ISL28113, ISL28213 and ISL28413 SPICE FIGURE 19. INPUT ESD DIODE CURRENT LIMITING Model Output Phase Reversal Figure21 shows the SPICE model schematic and Figure22 shows the net list for the SPICE model. The model is a simplified version Output phase reversal is a change of polarity in the amplifier of the actual device and simulates important AC and DC transfer function when the input voltage exceeds the supply parameters. AC parameters incorporated into the model are: 1/f voltage. The ISL28113, ISL28213 and ISL28413 are immune to and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC output phase reversal, even when the input voltage is 1V beyond parameters are IOS, total supply current and output voltage swing. the supplies. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page4. The AVOL is adjusted Unused Channels for 85dB with the dominate pole at 100Hz. The CMRR is set 72dB, If the application requires less than all amplifiers one channel, f=35kHz). The input stage models the actual device to present an the user must configure the unused channel(s) to prevent it from accurate AC representation. The model is configured for ambient oscillating. The unused channel(s) will oscillate if the input and temperature of +25°C. output pins are floating. This will result in higher than expected Figures23 through 32 show the characterization vs simulation supply currents and possible noise injection into the channel results for the Noise Voltage, Closed Loop Gain vs Frequency, being used. The proper way to prevent this oscillation is to short Large Signal 5V Step Response, CMRR and Open-loop Gain the output to the inverting input and ground the positive input (as Phase. shown in Figure20). - + FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS FN6728 Rev 8.00 Page 9 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macromodel hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. FN6728 Rev 8.00 Page 10 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 En Vin+ +- R21 +- VOLTAGE NOISE STAGE 800E3 28 V++ V9 29 DDN13 + V1 I2 G1A - + 1E-6V 5E-3 R10 En 0.00035V 2 - + RA1 1E9 - 1 5RE2121 +- +- VmV1icd 13.0R0104 1.0R0204 4 M16 9 R105 8 R16010 M17 14 1R090 DDDXX1 15 4 R23 CinDiff EOS R3 R4 6 11 12 D2 5 10 10 5E11 1.02pF In+ M14 5 M15 R7 R8 G2A RA2 1 1 1 Vc 7 13 - Vmid Vin- Cin1 Cin2 I1 IOS +1E-6V + 5E-3 25E-12 1.26pF 1.26pF V2 - V-- V-- VCM INPUT STAGE 1ST GAIN STAGE V++ G1 D3 G3 D5 318.329E3 G5 L1 V++ 17 DX 19 DX R13 4 + + R11 + + + 4.5474 5 - -0V.361V 1 - -0V.6504V 5.0CnF2 Vmid - 21 R11E56 16 Vc Vg Vg Vc R16 Vmid Vmid G2 R12 G4 0.604V C3 E4 G6 1E6 + 1 + 5.0nF 22 - V4 - V6 + + - L2 + 18 -0.61V + 20 - R14 - - + D4 D6 4.5474 318.329E3 V-- DX DX V-- VCM VCM 1ST GAIN STAGE (CONT) 2ND GAIN STAGE MID SUPPLY REF COMMON MODE GAIN STAGE V++ G7 V+ C4 D9 D10 G11 V+ + + 10pF DX DX - +- E2 - - R19 26 27 V7 + 50 R17 D7 DX Vg 90uIASY 5305.32 24 + -0.08V VOUT VOUT 23 V8 Vmid D8 DX 25 - +0.08V R20 V- R18 G12 50 5305.32 +- +- E3 +- C3 DDY11 +- +- DDY12 +- V- 10pF V-- G8 G9 G10 SUPPLY ISOLATION STAGE POLE STAGE OUTPUT STAGE FFIIGGUURREE 2211.. SSPPIICCEE SSCCHHEEMMAATTIICC FN6728 Rev 8.00 Page 11 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 * source ISL28113_SPICEmodel *2nd Gain Stage * Revision D, LaFontaine February 22, 2010 Improved noise G_G3 V++ VG 16 VMID 24.893e-3 performance G_G4 V-- VG 16 VMID 24.893e-3 * Model for Noise, supply currents, CMRR 72dB f=35kHz, AVOL V_V5 19 VG .604 85dB f=100Hz V_V6 VG 20 .604 * SR = 1.0V/us, GBWP 2MHz, 2nd pole 3MHz Output voltage clamp D_D5 19 V++ DX and short ckt I limit D_D6 V-- 20 DX *Copyright 2009 by Intersil Corporation R_R13 VG V++ 318.329e3 *Refer to data sheet “LICENSE STATEMENT” Use of R_R14 V-- VG 318.329e3 *this model indicates your acceptance with the C_C2 VG V++ 5E-09 *terms and provisions in the License Statement. C_C3 V-- VG 5E-09 * Connections: +input * * | -input *Mid supply Ref * | | +Vsupply E_E4 VMID V-- V++ V-- 0.5 * | | | -Vsupply E_E2 V++ 0 V+ 0 1 * | | | | output E_E3 V-- 0 V- 0 1 * | | | | | I_ISY V+ V- DC 90e-6 .subckt ISL28113subckt Vin+ Vin- V+ V- VOUT * * source ISL28113_DS rev1 *Common Mode Gain Stage with Zero * G_G5 V++ VC VCM VMID 0.25118 *Voltage Noise G_G6 V-- VC VCM VMID 0.25118 E_En VIN+ EN 28 0 1 E_EOS 1 EN VC VMID 1 D_D13 29 28 DN R_R15 VC 21 0.001 V_V9 29 0 0.45 R_R16 22 VC 0.001 R_R21 28 0 30 R_R22 EN VCM 5e11 * R_R23 VCM VIN- 5e11 *Input Stage L_L1 21 V++ 4.547418E-09 M_M14 3 1 5 5 NCHANNELMOSFET L_L2 22 V-- 4.547418E-09 M_M15 4 VIN- 6 6 NCHANNELMOSFET * M_M16 11 VIN- 9 9 PMOSISIL *Pole Stage M_M17 12 1 10 10 PMOSISIL G_G7 V++ 23 VG VMID 0.18849 I_I1 7 V-- DC 5e-3 G_G8 V-- 23 VG VMID 0.18849 I_I2 V++ 8 DC 5e-3 R_R17 23 V++ 5.30532 I_IOS VIN- 1 DC 25e-12 R_R18 V-- 23 5.30532 G_G1A V++ 14 4 3 1404 C_C4 23 V++ 1e-8 G_G2A V-- 14 11 12 1404 C_C5 V-- 23 1e-8 V_V1 V++ 2 1e-6 * V_V2 13 V-- 1e-6 *Output Stage with Correction Current Sources R_R1 3 2 1.0004 G_G9 26 V-- VOUT 23 0.02 R_R2 4 2 1.0004 G_G10 27 V-- 23 VOUT 0.02 R_R3 5 7 10 G_G11 VOUT V++ V++ 23 0.02 R_R4 7 6 10 G_G12 V-- VOUT 23 V-- 0.02 R_R5 9 8 10 V_V7 24 VOUT .08 R_R6 8 10 10 V_V8 VOUT 25 .08 R_R7 13 11 1 D_D7 23 24 DX R_R8 13 12 1 D_D8 25 23 DX R_RA1 14 V++ 1 D_D9 V++ 26 DX R_RA2 V-- 14 1 D_D10 V++ 27 DX C_CinDif VIN- EN 1.02E-12 D_D11 V-- 26 DY C_Cin1 V-- EN 1.26e-12 D_D12 V-- 27 DY C_Cin2 V-- VIN- 1.26e-12 R_R19 VOUT V++ 50 * R_R20 V-- VOUT 50 *1st Gain Stage .model pmosisil pmos (kp=16e-3 vto=-0.6) G_G1 V++ 16 15 VMID 334.753e-3 .model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6) G_G2 V-- 16 15 VMID 334.753e-3 .model DN D(KF=6.69e-9 AF=1) V_V3 17 16 .61 .MODEL DX D(IS=1E-12 Rs=0.1) V_V4 16 18 .61 .MODEL DY D(IS=1E-15 BV=50 Rs=1) D_D1 15 VMID DX .ends ISL28113subckt D_D2 VMID 15 DX D_D3 17 V++ DX D_D4 V-- 18 DX R_R9 15 14 100 R_R10 15 VMID 1e9 R_R11 16 V++ 1 R_R12 V-- 16 1 * FIGURE 22. SPICE NET LIST FN6728 Rev 8.00 Page 12 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Characterization vs Simulation Results 10,000 10,000 z) V+ = ±2.5V z) √H AV = 1 √H V/ V/ n n GE ( 1000 GE ( 1000 A A T T L L O O V V E E S S OI 100 OI 100 N N T T U U P P N N I I 10 10 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 23. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 24. SIMULATED INPUT NOISE VOLTAGE (A) AC sims.dat (active) 70 70 Rg = 100, Rf = 100k 60 AV = 1000 60 50 Rg = 1k, Rf = 100k B) 40 AV = 100 VC+L == ±42p.F5V B) 40 AIN (d 30 AV = 10 VROL U=T 1 =0 k50mVP-P AIN (d G 20 G 20 Rg = 10k, Rf = 100k 10 0 AV = 1 0 Rg = OPEN, Rf = 0 -10 -10 10 100 1k 10k 100k 1M 10M 100M 10 100 1.0k 10k 100k 1.0M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 25. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 26. SIMULATED CLOSED LOOP GAIN vs FREQUENCY (A) AC sims.dat (active) 3 3 VOUT 2 VS = ±2.5V 2 V) V) VS = ±2.5V L ( 1 L ( 1 NA VS = ±0.9V NA VIN G G SI 0 SI -0 GE RL = 10k GE LAR -1 ACVVOL U==T +1 =51 pRFAIL LAR -1 RCLL == 1105kpF -2 -2 AV = +10 VOUT = RAIL -3 -3 0 2 4 6 8 10 12 14 16 18 20 0 5 10 1 5 20 25 30 TIME (µs) TIME (µs) FIGURE 27. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE FIGURE 28. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs vs RL, VS=±0.9V, ±2.5V RL, VS = ±0.9V, ±2.5V FN6728 Rev 8.00 Page 13 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Characterization vs Simulation Results (Continued) (A) AC sims.dat (active) 120 20 200 100 0 E (°) B) 80 -20 AS 160 d GAIN H EN-LOOP GAIN (-246200000 V+ = ±2.5V PHASE -----864110002000PHASE (°) OOP GAIN (dB)/P 12800 OP-40 RL = 100k -140 N-L 40 CL = 10pF E -60 SIMULATION -160 OP 0 -80 -180 0.1 1 10 100 1k 10k 100k 1M 10M 100M 0.01 0.1 1.0 10 100 1 . 0 k 10k 100k 1.0M 10M100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 29. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs FIGURE 30. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs FREQUENCY FREQUENCY (A) AC sims.dat (active) 80 80 70 60 60 B) 50 B) d d R ( 40 R ( 40 R R M M C 30 C 20 20 10 SIMULATION 0 0 0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M 0.01 0.1 1.0 10 100 1 . 0 k 10k 100k 1.0M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 31. SIMULATED (DESIGN) CMRR FIGURE 32. SIMULATED(SPICE) CMRR FN6728 Rev 8.00 Page 14 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you have the latest Rev. DATE REVISION CHANGE 4/8/15 FN6728.8 Added a row to the eN parameter in the Electrical Specification table on page5 to show low noise. Corrected typo on Figures15, 16, 17 and 27 by updating the time units from “ms” to “µs”. Updated the About Intersil Verbiage. 10/25/12 FN6728.7 Ordering Information changes on page2: Removed “italics font” on “ISL28213FHZ-T7A” entry Changed on both the 28213FHZ entries, “Part Marking” from “BCP” to “BEKA” Added Note 3 Lead Finish Note for 8 Ld SOT-23 package Added Note 5 reference for all the SOT-23 and SC-70 entries (6 total), after the part marking, and added the note to Table. Added POD P8.064 on page23 4/16/12 FN6728.6 Mask changes have been made from RevA to RevB, datasheet updated to reflect new silicon. Page 4: Vos limits changed from ±5mV to ±4mV at room temp and ±6mV to ±5mV at +125°C. TcVos, Max spec removed, typical increased from 2 to 5. Page 7, Replaced Figure 8 with new graph. Page 7, Replaced Figure 11 with new graph. Page 8, Replaced Figure 18 with new graph. 5/18/11 FN6728.5 - On page2, Ordering Information table: ISL28113FHZ-T7 & -T7A PKG DWG # changed from MDP0038 (Obsoleted) to P5.064A. Removed ISL28213FHZ and added “Coming Soon” to parts ISL28213FHZ-T7A and ISL28413TSSOPEVAL1Z. - On page3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to IN- terminals. - On page4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V- - 0.5V to V+ + 0.5V". - On page4, updated CMRR and PSRR parameters in Electrical Specifications table with test condition specifiying -40°C to +125°C typical parameter. - On page5, updated Note 6 (“over-temp” note) referenced in MIN and MAX column headings of Electrical Specifications table from "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." to new standard "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." - On page9, under “Input ESD Diode Protection,” removed “They also contain back to-back diodes across the input terminals.” Changed “For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor...” to “For applications where the input differential voltage may exceed either power supply voltage by 0.5V or more, an external series resistor...”. Removed “Although the amplifier is fully protected, high input slew rates that exceed the amplifier slew rate (±1V/µs) may cause output distortion.” - On page9, Figure 19: updated circuit schematic by removing back-to-back input protection diodes. - On page18, replaced Package Outline Drawing MDP0038 (obsolete) with P5.064A. FN6728 Rev 8.00 Page 15 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Revision History (Continued) The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE 3/23/10 FN6728.4 Page 1, 2nd paragraph - Added “...SOT23-8 packages...” and changed “SO8” to “SOIC8”. Also global, changed S08 to SOIC8 Pg 2, Ordering Information table: Part # ISL28213FEZ changed to ISL28213FHZ and Part Marking changed to "TBD" -Added Related Literature on page 1, updated ordering information by adding Eval boards. -Added to ordering information part number ISL28213FHZ 8 Ld SOT-23 Package as coming soon. -Replaced Figure 24 Simulated Input Noise Voltage with following changes: Y-axis from “10 to 100” to “10,000 to 10” Removed (A) AC sims.dat (active) from top of graph Curve changed to improve noise performance Made changes to Spice Net List as follows: -Changed Revision from “C” to “D” and added improved noise performance to Revision line. -Changed in Voltage Noise “V_V9 29 0 .00035” to “V_V9 29 0 0.45” “R_R21 28 0 800E3 TC=0,0” to “R_R21 28 0 30” -Removed TC=0 in Input Stage from R_R1 through C_Cin2 -Removed TC=0 in 1st Gain Stage from R_R9 through R_R12 -Removed TC=0 in 2nd Gain Stage from R_R13 through C_C3 -Changed in Common Mode Gain Stage with Zero “G_G5 V++ VC VCM VMID 2.5118E-10” to “G_G5 V++ VC VCM VMID 0.25118” “G_G6 V-- VC VCM VMID 2.5118E-10” to “G_G6 V-- VC VCM VMID 0.25118” Removed TC=0 from R_R16 through R_R23 -Changed in Pole Stage “G_G7 V++ 23 VG VMID 188.49e-6” to ‘G_G7 V++ 23 VG VMID 0.18849” “G_G8 V-- 23 VG VMID 188.49e-6” to “G_G8 V-- 23 VG VMID 0.18849” Removed TC=0 from R_R17 through C_C5 Removed TC=0 in Output Stage with Correction Current Sources from R_R19 and R_R20 Made changes to Spice Schematic Figure 21 as follows: -Input Stage - Modified connection to the EOS (voltage control voltage source) -Added to Thermal Information 8 LD SOT-23 as TBD -Added to pin configuration for the ISL28213 8 Ld SOT-23 12/16/09 FN6728.3 Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page2. Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page4. 11/17/09 FN6728.2 Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information” on page2. 11/12/09 FN6728.1 Changed theta Ja to 250 from 300. Added license statement (page10) and reference in spice model (page12). 10/26/09 FN6728.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN6728 Rev 8.00 Page 16 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Small Outline Transistor Plastic Packages (SC70-5) P5.049 D e1 VIEW C 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES 5 4 A 0.031 0.043 0.80 1.10 - E CL A1 0.000 0.004 0.00 0.10 - 1 2 3 CL E1 A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 e b c 0.003 0.009 0.08 0.22 6 CL c1 0.003 0.009 0.08 0.20 6 0.20 (0.008) M C C D 0.073 0.085 1.85 2.15 3 CL E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 A A2 A1 SPELAATNINEG e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - -C- L 0.010 0.018 0.26 0.46 4 L1 0.017 Ref. 0.420 Ref. - 0.10 (0.004) C L2 0.006 BSC 0.15 BSC  0o 8o 0o 8o - b WITH N 5 5 5 PLATING b1 R 0.004 - 0.10 - c c1 R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X 1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R 6. These Dimensions apply to the flat section of the lead between GAUGE PLANE 0.08mm and 0.15mm from the lead tip. SEATING L 7. Controlling dimension: MILLIMETER. Converted inch dimen- PLANE C  sions are for reference only. L1 L2 4X 1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN FN6728 Rev 8.00 Page 17 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Package Outline Drawing P5.064A 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev 0, 2/10 1.90 0-3° D A 0.08-0.20 5 4 PIN 1 INDEX AREA 2.80 3 1.60 3 5 0.15 CD 2x 2 0.20 C (0.60) 2x 0.95 SEE DETAIL X B 0.40 ±0.05 3 END VIEW 0.20M C A-B D TOP VIEW 10° TYP (2 PLCS) 5 0.15 C A-B H 2.90 2x 1.45 MAX C 1.14 ±0.15 (0.25)GAUGE 0.10 C SEATING PLANE PLANE 0.45±0.1 4 SIDE VIEW 0.05-0.15 DETAIL "X" (0.60) (1.20) NOTES: 1. Dimensions are in millimeters. (2.40) Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. Dimension is exclusive of mold flash, protrusions or gate burrs. 4. Foot length is measured at reference to guage plane. 5. This dimension is measured at Datum “H”. 6. Package conforms to JEDEC MO-178AA. (0.95) (1.90) TYPICAL RECOMMENDED LAND PATTERN FN6728 Rev 8.00 Page 18 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 4.9±0.15 DETAIL "X" 3.0±0.1 1.10 Max PIN# 1 ID B 0.18 ± 0.05 SIDE VIEW 2 1 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 H GAUGE PLANE C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 3°±3° 0.08 CAB 0.10 ± 0.05 0.10C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not 0.65 included. 0.40 4. Plastic interlead protrusions of 0.25mm max per side are not included. 1.40 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP0043 MSOP 8L. FN6728 Rev 8.00 Page 19 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25MC AB SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C 0.175 ± 0.075 SEATING PLANE 0.10C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN6728 Rev 8.00 Page 20 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Small Outline Package Family (SO) A D h X 45° NN (N/2)+1 A PIN #1 I.D. MARK E E1 c SEE DETAIL “X” 1 (N/2) B L1 0.010M C A B e H C A2 GAUGE SEATING PLANE 0.010 PLANE A1 L 4° ±4° 0.004 C 0.010M C A B b DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO16 SO16 (0.300”) SO20 SO24 SO28 SYMBOL SO-8 SO-14 (0.150”) (SOL-16) (SOL-20) (SOL-24) (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 FN6728 Rev 8.00 Page 21 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Thin Shrink Small Outline Package Family (TSSOP) 0.25M C A B MDP0044 D A N (N/2)+1 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 0.20 C B A 1 (N/2) 2X b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 N/2 LEAD TIPS B c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 TOP VIEW D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 0.05 H e e 0.65 0.65 0.65 0.65 0.65 Basic C L 0.60 0.60 0.60 0.60 0.60 ±0.15 SEATING L1 1.00 1.00 1.00 1.00 1.00 Reference PLANE Rev. F 2/07 b 0.10M C A B 0.10 C NOTES: N LEADS SIDE VIEW 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per SEE DETAIL “X” side. 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A2 A GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X FN6728 Rev 8.00 Page 22 of 23 April 8, 2015

ISL28113, ISL28213, ISL28413 Small Outline Transistor Plastic Packages (SOT23-8) P8.064 0.20 (0.008) M C VIEW C 8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL e INCHES MILLIMETERS b SYMBOL MIN MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - 8 7 6 5 A1 0.000 0.0059 0.00 0.15 - CL E CL E1 A2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - 1 2 3 4 b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 e1 c1 0.003 0.008 0.08 0.20 6 D C D 0.111 0.118 2.80 3.00 3 CL E 0.103 0.118 2.60 3.00 - E1 0.060 0.067 1.50 1.70 3 A A2 A1 SPELAATNINEG e 0.0256 Ref 0.65 Ref - e1 0.0768 Ref 1.95 Ref - -C- L 0.014 0.022 0.35 0.55 4 L1 0.024 Ref. 0.60 Ref. 0.10 (0.004) C L2 0.010 Ref. 0.25 Ref. N 8 8 5 WITH b R 0.004 - 0.10 - PLATING b1 R1 0.004 0.010 0.10 0.25  0o 8o 0o 8o - c c1 Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178BA. 4X 1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R 6. These Dimensions apply to the flat section of the lead between GAUGE PLANE 0.08mm and 0.15mm from the lead tip. SEATING 7. Controlling dimension: MILLIMETER. Converted inch dimen- L PLANE sions are for reference only C  L1 L2 4X 1 VIEW C © Copyright Intersil Americas LLC 2009-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6728 Rev 8.00 Page 23 of 23 April 8, 2015