DATASHEET ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 FN8273 12-Bit, 250kSPS Low-Power ADCs with Single-Ended and Differential Inputs and Multiple Input Rev 1.00 Channels September 5, 2013 The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, Features ISL26325 and ISL26329 family of sampling SAR-type ADCs feature excellent linearity over supply and temperature • Pin-compatible family allows easy design upgrades variations, and offer versions with 1-, 2-, 4- and 8-channel • Excellent differential non-linearity (0.7LSB max) single-ended inputs, and 1-, 2- and 4-channel differential • Low THD: -86dB (typ) inputs. A proprietary input multiplexer and combination buffer amplifier reduces the input drive requirements, resulting in • Simple SPI-compatible serial digital interface lower cost and reduced board space. Specified measurement • Low 3mA operating current accuracy is maintained with input signals up to VDD. • Power-down current between conversions 8µA (typ) Members of the The ISL26320, ISL26321, ISL26322, • +5.25V to +2.7V supply ISL26323, ISL26324, ISL26325 and ISL26329 family of Low-Power ADCs offer pinout intercompatibility, differing only • Excellent ESD survivability: 5kV HBM, 350V MM, 2kV CDM in the analog inputs, to support quick replication of proven Applications layouts across multiple design platforms. • Industrial process control The serial digital interface is SPI compatible and is easily interfaced to popular FPGAs and microcontrollers. Power • Energy measurement consumption is limited to 15mW at a sampling rate of • Multichannel data acquisition systems 250kSPS, and an operating current of just 8µA typical between conversions, when configured for Auto Power-down • Pressure sensors mode. • Flow controllers The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 feature up to 5kV Human Body Model ESD survivability and are available in the popular SOIC and TSSOP packages. Performance is specified for operation over the full industrial temperature range (-40°C to +125°C). VDD VREF BUFFER CNV ANALOG INPUTS SCLK DIFFERENTIAL/ MUX ADC SPI SINGLE-ENDED SDO SDI OSC POR GND FIGURE 1. FUNCTIONAL BLOCK DIAGRAM FN8273 Rev 1.00 Page 1 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Application Block Diagram I2C Bus ANALOG SIGNAL INPUT MODULEs RTC RS-232 Pressure/Strain Gage Sensor MUX and ADC VREF Precision RS-485 RS-485 Master Amps M ADC μC μC DCP AmGpaliifn+ie Vrs AFciltteiv+resV UX RTC VREF Precision Precision Amps Amps POWER -V -V Voltage Temperature Sensor V Supervisor & LDO’s Sequencers VREF DCP System Power Core & Thermistor +V Switching I/O Power +V P Aremcpissio-Vn P Aremcpission AFciltteivres V Regulator SCwonitctrhoilnlegr LDO RSewgiutclahtionrgs -V Thermocouple +V Buffer, Filters, P Aremcpission Precisi+onVAFciltteivres CoAnMcttrouotalo tlroosrosps+V Span+ DVrivers M +V High Voltage Input Rail ~24V ISOB-Tlohcekrmal -V Amps-V PreAc-Vimsiposn PreAc-iVmsiposn UX DAC VREF -V Single Ended ANALOG SIGNAL OUTPUT MODULE Controller Flow Sensor Loop Supply Gain Active Differential Amp+lifViers Filte+rsV Isolator TPrarwness/ (cid:165)dsuucreer Iout 4-20mA Vin P Aremcpission P Armecpission Isolated Power Extractor -V -V Pin-Compatible Family RESOLUTION SPEED ANALOG INPUT MODEL (Bits) (kHz) INPUT CHANNELS ISL26310 12 125 Differential 1 ISL26311 12 125 Single-Ended 1 ISL26312 12 125 Differential 2 ISL26313 12 125 Single-Ended 2 ISL26314 12 125 Differential 4 ISL26315 12 125 Single-Ended 4 ISL26319 12 125 Single-Ended 8 ISL26320 12 250 Differential 1 ISL26321 12 250 Single-Ended 1 ISL26322 12 250 Differential 2 ISL26323 12 250 Single-Ended 2 ISL26324 12 250 Differential 4 ISL26325 12 250 Single-Ended 4 ISL26329 12 250 Single-Ended 8 FN8273 Rev 1.00 Page 2 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Ordering Information DESCRIPTION PART NUMBER PART RESOLUTION SPEED INPUT INPUT TEMP. RANGE PACKAGE PKG (Notes 1, 2, 3) MARKING (Bits) (kHz) (SE/DIFF) CHANNELS (°C) (Pb-Free) DWG # ISL26320FBZ 26320 FBZ 12 250 Diff 1 -40 to +125 8 Ld SOIC M8.15 ISL26321FBZ 26321 FBZ 12 250 SE 1 -40 to +125 8 Ld SOIC M8.15 ISL26322FVZ 26322 FVZ 12 250 Diff 2 -40 to +125 16 Ld TSSOP M16.173 ISL26323FBZ 26323 FBZ 12 250 SE 2 -40 to +125 8 Ld SOIC M8.15 ISL26324FVZ 26324 FVZ 12 250 Diff 4 -40 to +125 16 Ld TSSOP M16.173 ISL26325FVZ 26325 FVZ 12 250 SE 4 -40 to +125 16 Ld TSSOP M16.173 ISL26329FVZ 26329 FVZ 12 250 SE 8 -40 to +125 16 Ld TSSOP M16.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329. For more information on MSL please see techbrief TB363. FN8273 Rev 1.00 Page 3 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Pin Configurations ISL26320 ISL26321 (8 LD SOIC) (8 LD SOIC) TOP VIEW TOP VIEW VDD 1 8 CNV VDD 1 8 CNV GND 2 7 SCLK GND 2 7 SCLK AIN+ 3 6 SDO VREF 3 6 SDO AIN- 4 5 SDI AIN0 4 5 SDI ISL26323 (8 LD SOIC) TOP VIEW VDD 1 8 CNV GND 2 7 SCLK AIN0 3 6 SDO AIN1 4 5 SDI ISL26322 ISL26324 (16 LD TSSOP) (16 LD TSSOP) TOP VIEW TOP VIEW VDD 1 16 CNV VDD 1 16 CNV GND 2 15 SCLK GND 2 15 SCLK VREF 3 14 SDO VREF 3 14 SDO GND 4 13 SDI GND 4 13 SDI AIN0+ 5 12 NC AIN0+ 5 12 AIN3+ AIN0- 6 11 NC AIN0- 6 11 AIN3- AIN1+ 7 10 NC AIN1+ 7 10 AIN2+ AIN1- 8 9 NC AIN1- 8 9 AIN2- ISL26325 ISL26329 (16 LD TSSOP) (16 LD TSSOP) TOP VIEW TOP VIEW VDD 1 16 CNV VDD 1 16 CNV GND 2 15 SCLK GND 2 15 SCLK VREF 3 14 SDO VREF 3 14 SDO GND 4 13 SDI GND 4 13 SDI AIN0 5 12 AIN3 AIN0 5 12 AIN7 NC 6 11 NC AIN1 6 11 AIN6 AIN1 7 10 AIN2 AIN2 7 10 AIN5 NC 8 9 NC AIN3 8 9 AIN4 FN8273 Rev 1.00 Page 4 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Pin Descriptions PIN NUMBER PIN NAME ISL26320 ISL26321 ISL26322 ISL26323 ISL26324 ISL26325 ISL26329 DESCRIPTION VDD 1 1 1 1 1 1 1 Positive Supply Voltage GND 2 2 2, 4 2 2, 4 2, 4 2, 4 Ground VREF - 3 3 - 3 3 3 Reference Voltage Input AIN0+ - - 5 - 5 - - Differential Analog Input, Positive AIN0- - - 6 - 6 - - Differential Analog Input, Negative AIN1+ - - 7 - 7 - - Differential Analog Input, Positive AIN1- - - 8 - 8 - - Differential Analog Input, Negative AIN2+ - - - - 10 - - Differential Analog Input, Positive AIN2- - - - - 9 - - Differential Analog Input, Negative AIN3+ - - - - 12 - - Differential Analog Input, Positive AIN3- - - - - 11 - - Differential Analog Input, Negative AIN0 - 4 - 3 - 5 5 Single-Ended Analog Input AIN1 - - - 4 - 7 6 Single-Ended Analog Input AIN2 - - - - - 10 7 Single-Ended Analog Input AIN3 - - - - - 12 8 Single-Ended Analog Input AIN4 - - - - - - 9 Single-Ended Analog Input AIN5 - - - - - - 10 Single-Ended Analog Input AIN6 - - - - - - 11 Single-Ended Analog Input AIN7 - - - - - - 12 Single-Ended Analog Input SDI 5 5 13 5 13 13 13 Serial Interface Data Input SDO 6 6 14 6 14 14 14 Serial Interface Data Output SCLK 7 7 15 7 15 15 15 Serial Interface Clock Input CNV 8 8 16 8 16 16 16 Conversion Control Input NC - - 9, 10, 11, 12 - - 6, 8, 9, 11 - No Connect AIN+ 3 - - - - - - Differential Analog Input, Positive AIN- 4 - - - - - - Differential Analog Input, Negative FN8273 Rev 1.00 Page 5 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Absolute Maximum Ratings Thermal Information AIN+, AIN-, VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3 to VDD + 0.3V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Digital Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3 to VDD + 0.3V 8 Ld SOIC (Notes 4, 5) . . . . . . . . . . . . . . . . . 98 48 VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V 16 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 92 29 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3 to + 0.3V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW ESD Rating Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . .5000V Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . .350V Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . .2000V http://www.intersil.com/pbfree/Pb-FreeReflow.asp Latch-up (Tested per JESD-78B; Class 2, Level A). . . . . . . . . . . . . . . . . . . . . . . 100mA Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to +5.25V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN MAX SYMBOL PARAMETER TEST LEVEL OR NOTES (Note 6) TYP (Note 6) UNITS ANALOG INPUTS Number of Input Channels ISL26320, ISL26321 1 ISL26322 2 ISL26323 2 ISL26324, ISL26325 4 ISL26329 8 Input Voltage Range Differential Inputs (AINX+ - AINX-) is 0 VREF V -VREF (Min) and +VREF (Max) AINX, Single-Ended Inputs 0 VREF V Common Mode Input Voltage Range Differential Inputs VREF/2 – 0.2 VREF/2 VREF/2 + 0.2 V Average Input Current 2.5 µA CIN Input Capacitance 4 pF Channel-Channel Crosstalk fIN = 100kHz -86 dB VIN = FS, other channels=0V VOLTAGE REFERENCE VREFEX External Reference Input Voltage Range 2 2.5 VDD V IREFIN Average Input Current 200 220 µA CREFIN Effective Input Capacitance 10 pF DC ACCURACY Resolution (No Missing Codes) 12 Bits DNL Differential Nonlinearity Error -0.7 +0.7 LSB INL Integral Nonlinearity Error -0.7 +0.7 LSB Gain Error -6 6 LSB Gain Error Matching -2 2 LSB Offset Error -6 6 LSB FN8273 Rev 1.00 Page 6 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN MAX SYMBOL PARAMETER TEST LEVEL OR NOTES (Note 6) TYP (Note 6) UNITS Offset Error Matching -2 2 LSB PSRR Power Supply Rejection Ratio 70 dB DYNAMIC PERFORMANCE Signal-to-Noise Differential Inputs 73.4 dB SNR Notes: VIN = FS - 0.1dB, fIN = 10kHz Single-Ended Inputs 73.4 dB Signal-to-Noise + Distortion Differential Inputs 73.1 dB SINAD Notes: VIN = FS - 0.1dB, fIN = 10kHz Single-Ended Inputs 73.1 dB Total Harmonic Distortion Differential Inputs -86 dB THD Notes: VIN = FS - 0.1dB, fIN = 10kHz Single-Ended Inputs -86 dB SFDR Spurious-free Dynamic Range fIN = 20kHz 96 dB Notes: VIN = FS - 0.1dB BW -3dB Input Bandwidth 2.5 MHz tAD Sampling Aperture Delay 12 ns tjit Sampling Aperture Jitter 25 ps POWER SUPPLY REQUIREMENTS VDD Supply Voltage 2.7 5.25 V IDD Supply Current 3 3.5 mA PD Power Consumption Normal Operation 15 17.5 mW IPD Power-down Current Auto Power-Down Mode 8 50 µA Istby Standby Mode Current Auto Sleep Mode 0.4 mA DIGITAL INPUTS VIH 0.7 VDD V VIL 0.2 VDD V VOH IOH = -1mA VDD-0.4 V VOL IOL = 1mA 0.2 VDD V IIH, IIL Input Leakage Current -100 100 nA Serial Clock Frequency 20 MHz TIMING SPECIFICATIONS (Note 7) tSCLK SCLK Period (in RAC Mode) 50 ns tSCLK SCLK Period (in RSC, RDC Modes) 50 100 ns tDATA Safe Data Transfer Time After Conversion 1.6 µs State Begins tCSB_SCLK CSB Falling Low to SCLK Rising Edge 40 ns tSDI_SU SDI Setup Time with Respect to Positive 10 ns Edge of SCLK tSDI_H SDI Hold Time with Respect to Positive 10 ns Edge of SCLK tSDO_V SDOUT Valid Time with Respect to 25 ns Negative Edge of SCLK tSDOZ_D SDOUT to High Impedance State After CNV (Note 8) 85 ns Rising Edge (or last SCLK falling edge) tACQ Acquisition Time when Fully Powered Up 400 ns FN8273 Rev 1.00 Page 7 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Electrical Specifications VREF = VDD V, VDD = 2.7V to 5V, VCM = VDD/2, SCLK = 20MHz and TA = -40°C to +125°C (typical performance at +25°C), unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN MAX SYMBOL PARAMETER TEST LEVEL OR NOTES (Note 6) TYP (Note 6) UNITS tACQ Acquisition Time in Auto Sleep Mode 1.7 µs tACQ Acquisition time in Auto Power Down 150 µs Mode tSCLKH SCLK High Time 20 ns tSCLKL SCLK Low Time 20 ns tCNV CNV Pulse Width 100 ns NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. The device may become nonresponsive if the minimum acquisition times are not met in their respective modes, requiring a power cycle to restore normal operation. 8. Transition time to high impedance state is dominated by RC loading on the SDOUT pin. Specified value is measured using equivalent loading shown in Figure 2. VDD RL 2k OUTPUT PIN CL 10pF FIGURE 2. EQUIVALENT LOAD CIRCUIT FOR DIGITAL OUTPUT TESTING FN8273 Rev 1.00 Page 8 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, unless otherwise specified. 1.00 1.00 0.75 0.75 0.50 0.50 0.25 0.25 s) s) B B LS 0 LS 0 L ( L ( DN-0.25 IN-0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -1.00 -2000 -1000 0 1000 2000 -2000 -1000 0 1000 2000 CODE CODE FIGURE 3. DIFFERENTIAL NONLINEARITY (DNL) vs CODE FIGURE 4. INTEGRAL NONLINEARITY (INL) vs CODE 1.0 1.0 0.8 POSITIVE DNL 0.8 0.6 0.6 POSITIVE INL 0.4 0.4 0.2 0.2 NL 0.0 NL 0.0 D I -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 NEGATIVE INL -0.8 NEGATIVE DNL -0.8 -1.0 -1.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 5. DNL DISTRIBUTION vs TEMPERATURE FIGURE 6. INL DISTRIBUTION vs TEMPERATURE 2.0 0.0 2.7V -0.1 1.5 -0.2 B) 1.0 SB) -0.3 R (LS 0.5 OR (L -0.4 5.25V 5.0V 3.3V RO 0.0 3.3V 2.7V RR -0.5 R E N E -0.5 ET -0.6 GAI FFS -0.7 -1.0 O 5.0V -0.8 -1.5 5.25V -0.9 -2.0 -1.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. GAIN ERROR vs SUPPLY VOLTAGE AND TEMPERATURE FIGURE 8. OFFSET ERROR vs SUPPLY VOLTAGE AND TEMPERATURE FN8273 Rev 1.00 Page 9 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, unless otherwise specified. (Continued) 25 4.0 3.5 20 )sn( YAL 15 )Am( TN 23..50 5.0V 5.25V E E D R ER RU 2.0 U 10 C TR YL 1.5 E P PA PU 1.0 2.7V 3.3V 5 S 0.5 0 2.7 3.2 3.7 4.2 4.7 5.2 0.0-40 -20 0 20 40 60 80 100 120 SUPPLY VOLTAGE TEMPERATURE (°C) FIGURE 9. APERTURE DELAY vs SUPPLY VOLTAGE FIGURE 10. SUPPLY CURRENT vs VOLTAGE AND TEMPERATURE 2.5 50 45 2.0 A) 40 µ mA) NT ( 35 5.25V T ( 1.5 RE 30 N R RE AUTO POWER DOWN MODE NORMAL MODE CU 25 CUR 1.0 AUTO SLEEP MODE WN 20 5.0V PPLY UTDO 15 3.3V U 0.5 H 10 S S 5 2.7V 0.0 0 100 1k 10k 100k -40 -20 0 20 40 60 80 100 120 SAMPLE RATE (Sps) TEMPERATURE (°C) FIGURE 11. SUPPLY CURRENT vs SAMPLING RATE (VDD = 5V) FIGURE 12. SHUTDOWN CURRENTS vs VOLTAGE AND TEMPERATURE 75 -80 5.25V 5.0V 74 -82 B) NAD (d 73 D (dB) -84 5.25V 5.0V SI H R/ 72 T -86 N S 3.3V 2.7V 71 -88 2.7V 3.3V 70 -90 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 13. SNR AND SINAD vs SUPPLY VOLTAGE AND TEMPERATURE FIGURE 14. THD vs SUPPLY VOLTAGE AND TEMPERATURE FN8273 Rev 1.00 Page 10 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Typical Performance Characteristics TA = +25°C, VDD = 5V, VREF = 5V, fSAMPLE = 250kHz, fSCLK = 20MHz, unless otherwise specified. (Continued) 75 0 SNR -10 -20 70 -30 B) SINAD D (d B) -40 NA 65 D (d -50 SI H R/ T -60 N S -70 60 -80 -90 55 -100 100 1k 10k 100k 1M 100 1k 10k 100k 1M INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) FIGURE 15. SNR AND SINAD vs INPUT FREQUENCY FIGURE 16. THD vs INPUT FREQUENCY 0 70,000 SNR = 73.6dB THD = -87.6dB -20 60,000 SINAD = 73.4dB 65,536 SFDR = 89.1dB CODES B) -40 ENOB = 11.4 50,000 d E ( -60 40,000 LITUD -80 HITS30,000 P M-100 A 20,000 -120 10,000 -140 0 0 CODES CODES -160 0 0 25000 50000 75000 100000 125000 -3 -2 -1 0 1 2 3 FREQUENCY (Hz) CODE FIGURE 17. SINGLE-TONE FFT FIGURE 18. SHORTED INPUT HISTOGRAM FN8273 Rev 1.00 Page 11 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Circuit Description supports three different modes of reading the conversion data. These will be discussed later in this data sheet. The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 families of 12-bit ADCs are low-power Figures 19 and 20 illustrate simplified representations of the Successive Approximation-type (SAR) ADCs with 1-, 2-, 4-, or converter analog section for differential and single-ended 8-channels and a choice of single-ended or differential inputs. inputs, respectively. During the acquisition phase (CNV= 0) the The high-impedance buffered input simplifies interfacing to input signal is presented to the Cs samples capacitors. To sensors and external circuitry. properly sample the signal, the CNV signal must remain low for the specified time. When CNV is taken high (CNV = 1), the The entire ISL26320, ISL26321, ISL26322, ISL26323, switches that connect the sampling capacitors to the input are ISL26324, ISL26325, ISL26329 families follow the same base opened and the control logic begins the successive pinout and differs only in the analog input pins, allowing the user approximation sequence to convert the captured signal into a to replicate the basic board layout across multiple platforms with digital word. The conversion sequence timing is determined by a minimum redesign effort. the on-chip oscillator. The simple serial digital interface is compatible with popular ADC Transfer Function FPGAs and microcontrollers and allows direct conversion control by the CNV pin. The ISL26320, the ISL26322, and the ISL26324 feature differential inputs with output data coding in two's complement Functional Description format (see Table 1). The size of one LSB in these devices is (2*VREF)/4096. Figure 21 illustrates the ideal transfer function The ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, for these devices. ISL26325 and ISL26329 devices are SAR (Successive Approximation Register) analog-to-digital converters that use The ISL26321, ISL26323, ISL26325, and ISL26329 feature capacitor-based charge redistribution as their conversion single-ended inputs with output coding in binary format method. (seeTable2). The size of one LSB in these devices is VREF/4096. Figure 22 illustrates the ideal transfer function for these devices. These devices include an on-chip power-on reset (POR) circuit to initialize the internal digital logic when power is applied. An on-chip oscillator provides the master clock for the conversion logic. The CNV signal controls when the converter enters into its signal acquisition time (CNV = 0), and when it begins the conversion sequence after the signal has been captured (CNV=1). The converters include a configuration register that can be accessed via the serial port. The configuration register has various bits to indicate which channel (where applicable) is selected, to activate the auto-power-down feature where the ADC is shut down between conversions, or to output the configuration register contents along with the data conversion word whenever a conversion word is read from the serial port. The serial port VREF C VREF AC DA D CNV CS CNV CS ACQ AAIINN+– BUFFER AACCQQ VCAAMCCQQ CCNNVV COMPARATOR LSOAGRIC AIN BUFFER ACQ VCAMACCQQ CCNNVV COMPARATOR LSOAGRIC CNV CS CNV CS VREF DAC DAC FIGURE 19. ARCHITECTURAL BLOCK DIAGRAM, DIFFERENTIAL INPUT FIGURE 20. ARCHITECTURAL BLOCK DIAGRAM, SINGLE-ENDED FN8273 Rev 1.00 Page 12 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 011...111 1LSB = 2•VREF/4096 111...111 1LSB = VREF/4096 011...110 111...110 ADC CODE 100100100.........100100101 ADC CODE 011100100.........100100101 100...010 000...010 100...001 000...001 100...000 000...000 + –½VLRESFB 0V –1½+LVSREBF +–V1LRESFB 0 = + ½LSB FS = +VREF-1LSB ANALOG INPUT AIN+ – (AIN–) ANALOG INPUT FIGURE 21. IDEAL TRANSFER CHARACTERISTICS, DIFFERENTIAL INPUT FIGURE 22. IDEAL TRANSFER CHARACTERISTICS, SINGLE-ENDED INPUT Analog Inputs V Some members of the ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 family feature a 5.0 fully differential input with a nominal full-scale range equal to 4.0 twice the applied VREF voltage. Those devices with differential AIN– inputs have a nominal full scale range equal to twice the applied 3.0 AIN+ VREF voltage. Each input swings VREF volts (peak-to-peak), 180° 2.5Vp-p out of phase from one another for a total differential input of 2.0 2*VREF (refer to Figures 23 and 24). ALLOWABLE VCM RANGE 1.0 t VREF (P-P) AIN+ VREF = 2.5V ISL2631X/32X V AIN– VCM VREF (P-P) AIN- 5.0 5Vp-p AIN+ 4.0 FIGURE 23. DIFFERENTIAL INPUT SIGNALING VCM 3.0 Differential signaling offers several benefits over a single-ended ALLOWABLE VCM RANGE input, such as: 2.0 • Doubling of the full-scale input range (and therefore the 1.0 dynamic range) t • Improved even order harmonic distortion VREF = 5V • Better noise immunity due to common mode rejection FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE FOR DIFFERENTIAL INPUTS Figure 24 shows the relationship between the reference voltage and the full-scale differential input range for two different values of VREF. Note that the common-mode input voltage must be maintained within ±200mV of VREF/2 for differential inputs. Those devices with singled-ended inputs have a ground-referenced peak-to-peak input voltage span equal to the reference voltage. FN8273 Rev 1.00 Page 13 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Voltage Reference Input V An external reference voltage must be supplied to theVREF pin to set 5.0 the full-scale input range of the converter. The VREF input on these 4.0 devices can accept voltages ranging from 2V (nominal) to VDD, however, they are specified with VREF at a voltage of 5V with VDD at 3.0 AIN 5V. Note that exceeding VDD by more than 100mV can forward bias 2.5Vp-p the ESD protection diodes and degrade measurement accuracy due 2.0 to leakage current. A lower value voltage reference must be used if the device is operated with VDD at voltages lower than 5V. If the 1.0 VREF pin is tied to the VDD pin, the VREF pin should be decoupled with a local 1µF ceramic capacitor as described in a later paragraph. t VREF = 2.5V Figures 27 and 28 illustrate possible voltage reference options V for these ADCs. Figure 27 uses the precision ISL21090 voltage 5.0 5Vp-p AIN reference, which exhibits exceptionally low drift and low noise. The ISL21090 must be powered from a supply greater than 4.7V. 4.0 Figure 28 illustrates the ISL21010 voltage reference used with these ADCs. The ISL21010 series voltage references have higher 3.0 noise and drift than the ISL21090 devices, but operate at lower supply voltages. Therefore, these devices can readily be used 2.0 when these SAR ADCs operate with VDD at voltages less than 5V. 1.0 The outputs of ISL21090 or the ISL21010 devices should be decoupled with a 1µF ceramic capacitor. A 1µF, 6.3 V, X7R, 0603 t VREF = 5V (1608 metric) MLCC type capacitor is recommended for its high frequency performance. The trace length from the VREF pin to FIGURE 25. RELATIONSHIP BETWEEN VREF AND FULL-SCALE this capacitor and the voltage reference output should be as RANGE FOR SINGLE-ENDED INPUTS short as possible. Input Multiplexer The ISL26320 and ISL26323 devices (packaged in 8 pin SOIC The input of the multiplexer connects the selected analog input packages) derive their voltage reference from the VDD pin. To pins to the ADC input. A proprietary sampling circuit significantly achieve best performance, the VDD pin of these devices should reduces the input drive requirements, resulting in lower overall be bypassed with the 1µF ceramic capacitor mentioned above. cost and board space in addition to improved performance. Note Power-Down/Standby Modes that the input capacitance is only 2-3pF during the Sampling phase, changing to 40pF during the Settling phase, resulting in In order to reduce power consumption between conversions, a an average input current of 2.5µA and an effective input number of user-selectable modes can be utilized by setting the capacitance of only 4pF (see Figure 26). appropriate bits in the Configuration Register. TOTAL DC Auto Power-down (PD0 = 0) reduces power consumption by INPUT VOLTAGE AC ERROR ERROR shutting down all portions of the device except the oscillator and ERROR digital interface after completion of a conversion. There is a short recovery period after CNV is asserted Low (150µs with external reference). OFFSET ERROR SETTLING ERROR AND NOISE In Auto Sleep mode (PD1 = 1), the device will automatically enter the low-power Sleep mode at the end of the current conversion. Recovery from this mode involves only 2.1µs and may offer an alternative to Power-down mode in some applications. Output Data Format SAMPLING PHASE The converter output word is delivered in two’s complement format in differential input mode, and straight binary in ETTING PHASE single-ended input mode of operation respectively, all MSB-first. Input exceeding the specified full-scale voltage results in a clipped FIGURE 26. INPUT SAMPLING OPERATION output which will not return to in-range values until after the input signal has returned to the specified allowable voltage range. Data must be read prior to the completion of the current conversion to avoid conflict and loss of data, due to overwriting of the new conversion data into the output register. FN8273 Rev 1.00 Page 14 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 5V + BULK 0.1µF 1 DNC DNC 8 VDD ISL2631X 2 VIN DNC 7 ISL2632X VREF 2.5V 3 COMP VOUT 6 0.1µF 1µF (SEE VOLTAGE REFERENCE INPUT) 4 GND TRIM 5 ISL21090 FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY +2.7V TO +3.6V OR +5V + BULK 0.1µF VIN 1 0.1µF GND ISL2631X VDD 3 ISL2632X VREF VOUT 2 1.25, 2.048 OR 2.5V ISL21010 1µF (SEE VOLTAGE REFERENCE INPUT) FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY +2.7V TO +5V BULK 1µF (SEE VOLTAGE REFERENCE INPUT) ISL26320 VDD ISL26323 FIGURE 29. VOLTAGE REFERENCE FOR ISL26320/ISL26323 IS DERIVED FROM VDD TABLE 1. OUTPUT CODES - DIFFERENTIAL TABLE 2. OUTPUT CODES - SINGLE-ENDED Input Voltage Two’s Complement (12-bit) Input Voltage Binary (12 bit) >(VFS-1.5 LSB) 7FF >AIN-1.5 LSB FFF 7FF VFS-1.5 LSB ... 7FE FFF AIN-1.5 LSB … 000 FFE -0.5 LSB … FFF 001 0.5 LSB … 801 000 -VFS +0.5 LSB … 800 <0.5 LSB 000 NOTE: VFS in the table above equals the voltage between AIN+ and AIN-. Differential full scale is equal to 2* VREF. NOTE: Single-ended full scale is equal to VREF. FN8273 Rev 1.00 Page 15 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Serial Digital Interface Reading During Conversion Mode WithoutEOC The SL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325 and ISL26329 families utilizes an SPI-compatible From Idle, the user initiates the input signal Acquisition mode by interface to set the device configuration and read conversion taking CNV Low, and then initiates a conversion after tACQ by data. This flexible interface provides 3 modes of operation: pulsing CNV High. After the conversion starts, data is exchanged Reading After Conversion (RAC), Reading During Conversion on the serial interface while CNV is held Low (see Figure31). CNV (RDC), and Reading Spanning Conversions (RSC), with an must also be asserted High before tDATA to avoid enabling EOC. additional option providing an End of Conversion (EOC) indication This method is ideal for hosts with high SCLK communication on the SDO output in all 3 modes. The choice of operating mode rates to operate the device at the highest conversion rates. is determined by the timing of the signals on the serial interface. At the end of conversion the device enters the Idle state. After the The interface consists of the data clock (SCLK), serial digital host is certain that the conversion is completed (3.6µs after input (SDI), serial digital output (SDO), and the conversion control conversion is initiated at 250kSPS) a new acquisition can be input (CNV). From the Idle state (after completion of a prior initiated by pulling CNV Low which will initiate the Acquisition state. conversion), a High-to-Low transition on CNV indicates the Reading Spanning Conversion Mode beginning of input signal acquisition, with the Conversion then initiated by a subsequent Low-to-High transition. When CNV is WithoutEOC Low, input data presented to SDI is latched on the rising edge of In applications desiring slower interface data rates and while still SCLK. Output data will be present at SDO on the falling edge of maintaining maximum possible throughput, RSC mode can be SCLK. SDO is in the high-impedance state whenever CNV is High, used to transfer data during both the Acquisition and Conversion and activity on SCLK should be avoided during this time to avoid phases, as shown in Figure 32. corruption of the conversion process. SCLK should be Low when CNV is High. Data exchange begins during the Acquisition phase until CNV is asserted High to initiate a conversion and SDO returns to the During the Nth conversion, output data indicates the conversion high-impedance state, interrupting the exchange. After CNV is data and configuration settings for the N-1th conversion, while returned Low, SDO will return to the state prior to the CNV pulse the current configuration settings apply to the N+1th conversion. in order to avoid data loss. Once again data exchange occurs In order to minimize errors due to digital noise coupling, there when CNV is Low. CNV must be asserted High before tDATA in should be no activity on the serial interface after the specified order to avoid enabling EOC. tDATA period. Data should be read before the conversion is At the end of conversion the device enters the Idle state. After completed to avoid the newer results being overwritten resulting the host is certain that the conversion is completed (3.6µs after in a permanent loss of data. conversion is initiated at 250kSPS) a new acquisition can be Reading After Conversion Mode Without EOC initiated by pulling CNV Low, which will take the device back to Acquisition state from Idle state. In this mode, data transfer always occurs during the Acquisition phase, supporting the widest variety of interface data rates. Figure 30 depicts a timing waveform in this mode. From Idle, the device enters the Acquisition phase when CNV is taken Low. SDO emerges High from a high-impedance state, waiting for an SCLK to present the MSB of the current output data word. The configuration settings can be updated using SDI and at the same time previous conversion results can be read from SDO. After the communication is completed or the required acquisition time (tACQ) has elapsed – whichever is later – CNV transitions High indicating the start of conversion. CNV must be held High continuously for a minimum of 3.6µs (at 250kSPS) so that the conversion is completed without enabling EOC. Subsequently CNV may be asserted Low at any time so that the next Acquisition phase can begin. This method is suitable for hosts which operate with lower frequency SCLK. Note that when using slower SPI rates the data transfer time can exceed the minimum acquisition time, which will limit the conversion throughput to less than the maximum specified rate. For example, a 12-bit data transfer takes 12µs with a 1MHz SPI clock. This adds to the 3.6µs conversion time for an effective throughput of 64ksps. FN8273 Rev 1.00 Page 16 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle Acq. tACQ CNV tSCLK tSCLKH tSDOZ_D tCNV_SCLK SCLK tSCLKL tSDI_H SDI D15 D14 . . . D5 D4 D15 D14 . . . D5 D4 Configuration N+1 Configuration N+2 tSDI_SU Hi-Z State tSDO_V SDO MSB MSB-1 . . . D1 LSB MSB MSB-1 . . . LSB Conversion Result N-1 Conversion Result N FIGURE 30. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE, WITHOUT EOC ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle tACQ tDATA tCNV CNV tSCLK tSCLKH tCNV_CLK SCLK tSCLKL tSDI_H SDI D15 D14 . . . D5 D4 D14 . . . D5 D4 Configuration N+1 tSDI_SU Configuration N+2 Hi-Z State tSDO_V SDO MSB MSB-1 . . . D1 LSB MSB MSB-1 . . . D1 Conversion Result N-1 Conversion Result N FIGURE 31. TIMING DIAGRAM FOR READING DURING CONVERSION MODE, WITHOUT EOC ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle tCNV tDATA CNV tACQ tSCLKH tCNV_SCLK SCLK tSCLK tSCLKL tSDI_H SDI D15 D14 D13 D12 . . . D4 D15 D14 D13 D12 . . . D4 Configuration N+1 Configuration N+2 tSDI_SU Hi-Z State tSDO_V SDO MSB MSB-1 MSB-1 MSB-2 . . . D1 LSB MSB MSB-1 MSB-1 MSB-2 . . . D1 Conversion Result N-1 Conversion Result N Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied). FIGURE 32. TIMING DIAGRAM FOR READING SPANNING CONVERSION MODE, WITHOUT EOC FN8273 Rev 1.00 Page 17 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Reading After Conversion Mode, with EOC Reading Spanning Conversion Mode, with EOC In this mode (Figure 33), after CNV is asserted Low to start input After initiating an Acquisition by bringing CNV Low, the user acquisition, a data exchange is executed by SCLK during the begins exchanging data as previously mentioned, until CNV is Acquisition period. CNV is asserted High briefly to initiate a asserted High to initiate a conversion and SDO returns to a Conversion, forcing SDO to a high-impedance state. SDO returns high-impedance state, interrupting the exchange. And, after CNV HIGH when CNV is asserted Low during the entire conversion period. is returned Low, SDO will return to the state prior to the CNV pulse in order to avoid losing data interrupted by the conversion At the end of conversion, the device asserts SDO Low to indicate pulse (see Figure 35). The user should take care to observe the that the conversion is complete. This may be used as an interrupt tDATA period in order to minimize the effects of digital noise on to start the Acquisition phase. It should be noted (as indicated in sensitive portions of conversion. After completion of the data Figure 33) that an additional pulse on CNV is required at the end exchange, an additional pulse on SCLK forces SDO to a of conversion to take the part back to Acquisition from Idle state. high-impedance state. At the end of conversion, the device As discussed in section “Reading After Conversion Mode Without asserts SDO Low indicating the end of conversion. The device EOC”. The acquisition time (tACQ) may limit the conversion then returns to Idle, waiting for a pulse on CNV to initiate a new throughput at slower SPI clock rates. Acquisition cycle. Accessing the Configuration Register During Reading During Conversion Mode, with EOC Data Readback From Idle, a falling edge on CNV initiates the Acquisition mode, The Configuration Register contains the channel address of the and then a rising edge initiates a Conversion. After the current conversion data. The contents can be accessed during a conversion is initiated, CNV is asserted Low once again. Data normal data output sequence by continuing to clock data from exchange across SDI and SDO can proceed while CNV is Low, SDO if the register readback mode is enabled. Both 12-bit output again observing the requirements of the tDATA period in order to data words and the 16-bit configuration word are output in 28 minimize the effects of digital noise on sensitive portions of the SCLK periods, as shown in Figure 36, which demonstrates an conversion. In this mode, an additional pulse is required on SCLK example sequence. Note that SDO goes into the high-impedance after the completion of the data exchange, to transition SDO to state when CNV is High. The Configuration Register can be read the high-impedance state. Later, SDO is asserted low by the during any Read Sequence by generating the additional SCLKs, device indicating end of conversion. The device then returns to with the restriction that the sequence must be completed prior to Idle. The falling edge of SDO may be used as an interrupt to start the end of the current conversion. This will prevent loss of data the Acquisition phase (see Figure 34). due to overwriting of the new conversion data into the output and configuration registers. ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle Acq. tACQ tCNV CNV tSCLK tSCLKH tCNV_SCLK SCLK tSCLKL tSDI_H SDI D15 D14 . . . D5 D4 D15 D14 . . . D5 D4 Configuration N+1 Configuration N+2 tSDI_SU Hi-Z State tSDO_V SDO MSB MSB-1 . . . D1 LSB MSB MSB-1 . . . LSB Conversion Result N-1 Conversion Result N FIGURE 33. TIMING DIAGRAM FOR READING AFTER CONVERSION MODE WITH EOC ON SDO OUTPUT FN8273 Rev 1.00 Page 18 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle tACQ tDATA tCNV CNV tSCLK tSCLKH tCNV_CLK SCLK tSCLKL tSDI_H SDI D15 D14 . . . D5 D4 D14 . . . D5 D4 Configuration N+1 tSDI_SU Configuration N+2 Hi-Z State tSDO_V SDO MSB MSB-1 . . . D1 LSB MSB MSB-1 . . . D1 Conversion Result N-1 Conversion Result N FIGURE 34. TIMING DIAGRAM FOR READING DURING CONVERSION MODE WITH EOC ON SDO OUTPUT ADC STATE Conversion N Conversion N+1 Power-Up Idle Acquisition Conversion Idle Acquisition Conversion Idle tCNV tDATA CNV tACQ tSCLKH tCNV_SCLK SCLK tSCLK tSCLKL tSDI_H SDI D15 D14 D13 D12 . . . D4 D15 D14 D13 D12 . . . D4 Configuration N+1 Configuration N+2 tSDI_SU Hi-Z State tSDO_V SDO MSB MSB-1 MSB-1 MSB-2 . . . D1 LSB MSB MSB-1 MSB-1 MSB-2 . . . D1 Conversion Result N-1 Conversion Result N Note: Transition from Acquisition to Conversion mode may occur after any integer number of clock cycles (provided that the minimum tACQ is satisfied). FIGURE 35. TIMING DIAGRAM FOR READING SPANNING CONVERSIONS MODE WITH EOC ON SDO OUTPUT ADC STATE Conversion N Power-Up Idle Acquisition Conversion Idle CNV SCLK SDI D15 D14 . . . D5 D4 Configuration N+1 Hi-Z State SDO MSB MSB-1 . . . D1 LSB Cfg15 Cfg14 . . . Cfg1 Cfg0 Conversion Result N-1 Configuration settings of N-1 Result FIGURE 36. TIMING DIAGRAM FOR READING AFTER CONVERSION WITH REGISTER READBACK, WITHOUT EOC FN8273 Rev 1.00 Page 19 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Device Configuration Registers Power Management Modes The Input Multiplexer Channel Select and power management In all SPI interface modes (RAC, RDC, etc.) the device has three features are controlled by loading the appropriate bits into the states of operation: Acquisition, Conversion and Idle. Power 16-bit Configuration Register through the serial port, MSB-first, management modes decide the state of the ADC in Idle mode as shown below. The first two Load bits LD1-LD0 must be set to and are selected by the PM bits in the Configuration Register as “11” in order to perform a Register update: any other setting will shown in Table 3 and 4. leave the Register unchanged. Changes to the Configuration In the default mode (Continuous Operation) the ADC is fully Register will be implemented internally immediately following powered in the Idle state and can be taken back to the the completion of the current conversion, or require a dummy Acquisition state instantaneously. In this mode the ADC can be conversion in order to take effect. Also, in the case of all power operated with maximum throughput and hence is ideally suitable management features, a recovery time will be incurred when for applications where the ADC is operated continuously. returning to normal operation, as indicated. In Auto Sleep Mode the ISL263XX will be in a sleep state TABLE 3. CONFIGURATION REGISTER consuming less than 0.4mA. However, it should be noted that the BIT 15 requirements on tACQ are more stringent in Auto Sleep mode (MSB) 14 13 12 11 10 9 8 since the device must wake up and then perform the Acquisition. LD1 LD0 ADDR2 ADDR1 ADDR0 PM1 PM0 Unused In Auto Power Down Mode (as selected by PM bits) the ADC will be in power-down condition during the Idle period, consuming less than BIT 0 5µA of current. Wake-up time takes 150µs. The acquisition time BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (LSB) (tACQ) must be increased to account for this delay. RGRD Unused The power management modes provide a high degree of flexibility in trading average power consumption versus the TABLE 4. CONFIGURATION REGISTER 2 required throughput. Significant power savings can be achieved by operating in either Auto Sleep Mode or Auto Power-Down BIT(S) DESCRIPTION mode depending on the throughput requirements. 15:14 Register Load word, set to “11” to update registers, otherwise previous settings are retained. 13:11 Multiplexer Channel Select word ADDR2:0. 000H: Channel AIN0 (single-ended input devices) or AIN0+/AIN0- (differential input devices). 001H: Channel AIN1 or AIN1+/AIN1- 010H: Channel AIN2 or AIN2+/AIN2- 011H: Channel AIN3 or AIN3+/AIN3- 100H: Channel AIN4 101H: Channel AIN5 110H: Channel AIN6 111H: Channel AIN7 10:9 Power Management Configuration Control 00H: Auto Power-Down mode. Device will go into Power-down mode automatically at the end of the next conversion cycle. 01H: Continuous Operation mode (default). Device remains fully powered at all times. 1xH: Auto Sleep Mode. Device will enter reduced-power Sleep mode automatically at the end of the next conversion cycle. A "1" in PM1 overrides the setting in PM0. 8 Unused. 7 Register readback mode. "1" means register readback is enabled resulting in configuration settings to be output along with conversion results. "0" (default) mode of operation register settings are not output. 6:0 Unused. FN8273 Rev 1.00 Page 20 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE September 5, 2013 FN8273.1 Updated Figure 22 on page 13, IDEAL TRANSFER CHARACTERISTICS, SINGLE-ENDED INPUT. Block diagram on page2, corrected temperature sensor drawing and added an input to the Mux and ADC section. June 8, 2012 FN8273.0 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability © Copyright Intersil Americas LLC 2012-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8273 Rev 1.00 Page 21 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Package Outline Drawing M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 A 1 3 5.00 ±0.10 16 9 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 C B A 1 8 0.65 B 0.09-0.20 TOP VIEW END VIEW H - 0.05 1.00 REF C 1.20 MAX 0.90 +0.15/-0.10 SEATING PLANE GAUGE 0.25 +0.05/-0.06 5 PLANE 0.25 0.10MCBA 0.10C 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN8273 Rev 1.00 Page 22 of 23 September 5, 2013

ISL26320, ISL26321, ISL26322, ISL26323, ISL26324, ISL26325, ISL26329 Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN8273 Rev 1.00 Page 23 of 23 September 5, 2013