DATASHEET ISL26132, ISL26134 FN6954 Low-Noise 24-bit Delta Sigma ADC Rev 3.00 November 20, 2014 The ISL26132 and ISL26134 are complete analog front ends Features for high resolution measurement applications. These 24-bit Delta-Sigma Analog-to-Digital Converters include a very • Up to 21.6 Noise-free bits low-noise amplifier and are available as either two or four • Low noise amplifier with gains of 1x/2x/64x/128x differential multiplexer inputs. The devices offer the same • RMS noise: 10.6nV @ 10Sps (PGA = 128x) pinout as the ADS1232 and ADS1234 devices and are functionally compatible with these devices. The ISL26132 and • Linearity error: 0.0002% FS ISL26134 offer improved noise performance at 10Sps and • Simultaneous rejection of 50Hz and 60Hz (@ 10Sps) 80Sps conversion rates. • Two (ISL26132) or four (ISL26134) channel differential The on-chip low-noise programmable-gain amplifier provides input multiplexer gains of 1x/2x/64x/128x. The 128x gain setting provides an • On-chip temperature sensor (ISL26132) input range of ±9.766mVFS when using a 2.5V reference. The high input impedance allows direct connection of sensors, such • Automatic clock source detection as load cell bridges to ensure the specified measurement • Simple interface to read conversions accuracy without additional circuitry. The inputs accept signals • +5V Analog, +5 to +2.7V digital supplies 100mV outside the supply rails when the device is set for unity gain. • Pb-Free (RoHS compliant) The Delta-Sigma ADC features a third order modulator • TSSOP packages: ISL26132, 24 pin; ISL26134, 28 pin providing up to 21.6-bit noise-free performance. The device Applications can be operated from an external clock source, crystal (4.9152MHz typical), or the on-chip oscillator. • Weigh scales The two channel ISL26132 is available in a 24 Ld TSSOP • Temperature monitors and controls package and the four channel ISL26134 is available in a 28 Ld • Industrial process control TSSOP package. Both are specified for operation over the • Pressure sensors automotive temperature range (-40°C to +105°C). AVDD CAP DVDD XTALIN/CLOCK INTERNAL EXTERNAL CLOCK OSCILLATOR XTALOUT AIN1+ AIN1- SDO/RDY AIN2+ AIN2- INPUT PGA MULTIPLEXER 1x/2x/64x/ ADC AIN3+ 128x AIN3- SCLK ISL26134 Only AIN4+ AIN4- PWDN SPEED A0 A1/TEMP AGND GAIN0 GAIN1 CAP DGND VREF+ VREF- DGND DGND NOTE for A1/TEMP pin: Functions as A1 on ISL26134; Functions as TEMP on ISL26132 FIGURE 1. BLOCK DIAGRAM FN6954 Rev 3.00 Page 1 of 23 November 20, 2014

ISL26132, ISL26134 Ordering Information PART NUMBER TEMPERATURE RANGE PACKAGE PKG. (Notes 2, 3) PART MARKING (°C) (Pb-free) DWG. # ISL26132AVZ 26132 AVZ -40 to +105 24 Ld TSSOP M24.173 ISL26132AVZ-T (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173 ISL26132AVZ-T7A (Note 1) 26132 AVZ -40 to +105 24 Ld TSSOP (Tape & Reel) M24.173 ISL26134AVZ 26134 AVZ -40 to +105 28 Ld TSSOP M28.173 ISL26134AVZ-T (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173 ISL26134AVZ-T7A (Note 1) 26134 AVZ -40 to +105 28 Ld TSSOP (Tape & Reel) M28.173 ISL26134AV28EV1Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL26132, ISL26134. For more information on MSL please see techbrief TB363. TABLE 1. KEY DIFFERENCES OF PARTS PART NUMBER NUMBER OF CHANNELS ON-CHIP TEMPERATURE SENSOR NUMBER OF PINS ISL26132 2 YES 24 ISL26134 4 NO 28 Pin Configurations ISL26132 ISL26134 (24 LD TSSOP) (28 LD TSSOP) TOP VIEW TOP VIEW DVDD 1 24 SDO/RDY DVDD 1 28 SDO/RDY DGND 2 23 SCLK DGND 2 27 SCLK XTALIN/CLOCK 3 22 PDWN XTALIN/CLOCK 3 26 PDWN XTALOUT 4 21 SPEED XTALOUT 4 25 SPEED DGND 5 20 GAIN1 DGND 5 24 GAIN1 DGND 6 19 GAIN0 DGND 6 23 GAIN0 TEMP 7 18 AVDD A1 7 22 AVDD A0 8 17 AGND A0 8 21 AGND CAP 9 16 VREF+ CAP 9 20 VREF+ CAP 10 15 VREF- CAP 10 19 VREF- AIN1+ 11 14 AIN2+ AIN1+ 11 18 AIN2+ AIN1- 12 13 AIN2- AIN1- 12 17 AIN2- AIN3+ 13 16 AIN4+ AIN3- 14 15 AIN4- FN6954 Rev 3.00 Page 2 of 23 November 20, 2014

ISL26132, ISL26134 Pin Descriptions PIN NUMBER ANALOG/DIGITAL NAME ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION DVDD 1 1 Digital Digital Power Supply (2.7V to 5.25V) DGND 2, 5, 6 2, 5, 6 Digital Digital Ground XTALIN/CLOCK 3 3 Digital/Digital Input External Clock Input: typically 4.9152MHz. Tie low to activate internal oscillator. Can also use external crystal across XTALIN/CLOCK and XTALOUT pins. XTALOUT 4 4 Digital External Crystal connection TEMP 7 - Digital Input On-chip Temperature Diode Enable A1 - 7 Digital Input A0 8 8 TABLE 2. INPUT MULTIPLEXER SELECT ISL26134 ISL26132 A1 A0 CHANNEL 0 0 AIN1 0 1 AIN2 1 0 AIN3 1 1 AIN4 CAP 9, 10 9, 10 Analog PGA Filter Capacitor AIN1+ 11 11 Analog Input Positive Analog Input Channel 1 AIN1- 12 12 Analog Input Negative Analog Input Channel 1 AIN3+ - 13 Analog Input Positive Analog Input Channel 3 AIN3- - 14 Analog Input Negative Analog Input Channel 3 AIN4- - 15 Analog Input Negative Analog Input Channel 4 AIN4+ - 16 Analog Input Positive Analog Input Channel 4 AIN2- 13 17 Analog Input Negative Analog Input Channel 2 AIN2+ 14 18 Analog Input Positive Analog Input Channel 2 VREF- 15 19 Analog Input Negative Reference Input VREF+ 16 20 Analog Input Positive Reference Input AGND 17 21 Analog Analog Ground AVDD 18 22 Analog Analog Power Supply 4.75V to 5.25V GAIN0 19 23 Digital Input TABLE 3. GAIN SELECT GAIN1 20 24 GAIN1 GAIN0 GAIN 0 0 1 0 1 2 1 0 64 1 1 128 FN6954 Rev 3.00 Page 3 of 23 November 20, 2014

ISL26132, ISL26134 Pin Descriptions (Continued) PIN NUMBER ANALOG/DIGITAL NAME ISL26132 ISL26134 INPUT/OUTPUT DESCRIPTION SPEED 21 25 Digital Input TABLE 4. DATA RATE SELECT SPEED DATA RATE 0 10Sps 1 80Sps PDWN 22 26 Digital Input Power-Down: Holding this pin low powers down the entire converter and resets the ADC. SCLK 23 27 Digital Input Serial Clock: Clock out data on the rising edge. Also used to initiate Offset Calibration and Sleep modes. See “Serial Clock Input (SCLK)” on page14 for more details. SDO/RDY 24 28 Digital Output Dual-Purpose Output: Data Ready: Indicate valid data by going low. Data Output: Outputs data, MSB first, on the first rising edge of SCLK. Circuit Description The ISL26132 (2-channel) and ISL26134 (4-channel) devices are very low noise 24-bit delta-sigma ADCs that include a programmable gain amplifier and an input multiplexer. The ISL26132 offers an on-chip temperature measurement capability. The ISL26132, ISL26134 provide pin compatibility and output data compatibility with the ADS1232/ADS1234, and offer the same conversion rates of 10Sps and 80Sps. All the features of the ISL26132, ISL26134 are pin-controllable, while offset calibration, standby mode, and output conversion data are accessible through a simple 2-wire interface. The clock can be selected to come from an internal oscillator, an external clock signal, or crystal (4.9152MHz typical). FN6954 Rev 3.00 Page 4 of 23 November 20, 2014

ISL26132, ISL26134 Absolute Maximum Ratings Thermal Information AGND to DGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Analog In to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to AVDD+0.3V 24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 65 18 Digital In to DGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to DVDD+0.3V 28 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 63 18 Input Current Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW Momentary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C ESD Rating Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . . . . . . . . . .7.5kV http://www.intersil.com/pbfree/Pb-FreeReflow.asp Machine Model (Per JESD22-A115). . . . . . . . . . . . . . . . . . . . . . . . . .450V Charged Device Model (Per JESD22-C101) . . . . . . . . . . . . . . . . . . . . . . . . 2kV Operating Conditions Latch-up (Per JEDEC JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA @ Room and Hot (+105°C) Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DVDD to DGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.25V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and TA=-40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C MIN MAX SYMBOL PARAMETER TEST LEVEL or NOTES (Note 6) TYP (Note 6) UNITS ANALOG INPUTS Differential Input Voltage Range ±0.5VREF/ V Gain Common Mode Input Voltage Gain = 1, 2 AGND - 0.1 AVDD + 0.1 V Range Gain = 64, 128 AGND+1.5 AVDD - 1.5 V Gain = 1 ±20 nA Differential Input Current Gain = 2 ±40 nA Gain = 64, 128 ±1 nA SYSTEM PERFORMANCE Resolution No Missing Codes 24 Bits Internal Osc. SPEED = High 80 SPS Internal Osc. SPEED = Low 10 SPS Data Rate External Osc. SPEED = High fCLK/61440 SPS External Osc. SPEED = Low fCLK/491520 SPS Digital Filter Settling Time Full Setting 4 Conversions INL Integral Nonlinearity Differential Input Gain = 1, 2 ±0.0002 ±0.001 % of FSR (Note7) Differential Input Gain = 64, 128 ±0.0004 % of FSR (Note7) Input Offset Error Gain = 1 ±0.4 ppm of FS Gain = 128 ±1.5 ppm of FS Input Offset Drift Gain = 1 0.3 µV/°C Gain = 128 10 nV/°C Gain Error (Note 8) Gain = 1 ±0.007 ±0.02 % Gain = 128 ±0.02 % Gain Drift Gain = 1 0.5 ppm/°C Gain = 64 3.5 ppm/°C Gain = 128 3.5 ppm/°C FN6954 Rev 3.00 Page 5 of 23 November 20, 2014

ISL26132, ISL26134 Electrical Specifications VREF+ = 5V, VREF- = 0V, AVDD = 5V, DVDD = 5V, AGND = DGND = 0V, MCLK = 4.9152MHz, and TA=-40°C to +105°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +105°C (Continued) MIN MAX SYMBOL PARAMETER TEST LEVEL or NOTES (Note 6) TYP (Note 6) UNITS CMRR Common Mode Rejection AtDC, Gain = 1, V = 1V 85 100 dB At DC, Gain = 128, V = 0.1V 100 dB 50Hz/60Hz Rejection (Note 9) External 4.9152MHz Clock 130 dB PSRR Power Supply Rejection At DC, Gain = 1, V = 1V 82 100 dB At DC, Gain = 128, V = 0.1V 100 105 dB Input Referred Noise See “Typical Characteristics” beginning on page8 Noise Free Bits See “Typical Characteristics” beginning on page8 VOLTAGE REFERENCE INPUT VREF Voltage Reference Input VREF = VREF+ - VREF- 1.5 AVDD AVDD + 0.1 V VREF- Negative Reference Input AGND - 0.1 VREF+ - 1.5 V VREF+ Positive Reference Input VREF- + 1.5 AVDD + 0.1 V IREF Voltage Reference Input Current ±350 nA POWER SUPPLY REQUIREMENTS AVDD Analog Supply Voltage 4.75 5.0 5.25 V DVDD Digital Supply Voltage 2.7 3.3 5.25 V AIDD Analog Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 7 8.5 mA Normal Mode, AVDD = 5, Gain = 64, 128 9 12 mA Standby Mode 0.2 3 µA Power-Down 0.2 2.5 µA DIDD Digital Supply Current Normal Mode, AVDD = 5, Gain = 1, 2 750 950 µA Normal Mode, AVDD = 5, Gain = 64, 128 750 950 µA Standby Mode 1.5 26 µA Power-Down 1 26 µA PD Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 49.6 mW Normal Mode, AVDD = 5, Gain = 64, 128 68 mW Standby Mode 0.14 mW Power-Down 0.14 mW DIGITAL INPUTS VIH 0.7 DVDD V VIL 0.2 DVDD V VOH IOH = -1mA DVDD - 0.4 V VOL IOL = 1mA 0.2 DVDD V Input Leakage Current ±10 µA External Clock Input Frequency 0.3 4.9152 MHz Serial Clock Input Frequency 1 MHz NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. FSR = Full Scale Range = VREF/Gain 8. Gain accuracy is calibrated at the factory (AVDD = +5V). 9. Specified for word rate equal to 10Sps. FN6954 Rev 3.00 Page 6 of 23 November 20, 2014

ISL26132, ISL26134 Noise Performance The ISL26132 and ISL26134 provide excellent noise performance. The noise performance on each of the gain settings of the PGA at the selected word rates is shown in Tables5 and 6. Resolution in bits decreases by 1-bit if the ADC is operated as a single-ended input device. Noise measurements are input-referred, taken with bipolar inputs under the specified operating conditions, with fCLK= 4.9152MHz. TABLE 5. AVDD = 5V, VREF = 5V, DATA RATE = 10Sps RMS NOISE PEAK-TO-PEAK NOISE NOISE-FREE BITS GAIN (nV) (nV) (Note 10) (Note 11) 1 243 1604 21.6 2 148 977 21.3 64 11.3 75 20 128 10.6 70 19 TABLE 6. AVDD = 5V, VREF = 5V, DATA RATE = 80Sps RMS NOISE PEAK-TO-PEAK NOISE NOISE-FREE BITS GAIN (nV) (nV) (Note 10) (Note 11) 1 565 3730 20.4 2 285 1880 20.3 64 29.5 194.8 18.6 128 28.2 186.1 17.6 NOTES: 10. The peak-to-peak noise number is 6.6 times the rms value. This encompasses 99.99% of the noise excursions that may occur. This value best represents the worst case noise that could occur in the output conversion words from the converter. 11. Noise-Free Bits is defined as: Noise-Free Bits = ln(FSR/peak-to-peak noise)/ln(2) where FSR is the full scale range of the converter, VREF/Gain. FN6954 Rev 3.00 Page 7 of 23 November 20, 2014

ISL26132, ISL26134 Typical Characteristics 10 300 GAIN = 1 GAIN = 1, N = 1024 RATE = 10Sps RATE = 10Sps 250 STD DEV = 1.635 LSB 5 VREF = 2.5V SB) 200 L E ( S D T CO 0 UN 150 UT CO P UT 100 O -5 50 -10 0 0 200 400 600 800 1000 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 2. NOISE AT GAIN = 1, 10Sps FIGURE 3. NOISE HISTOGRAM AT GAIN = 1, 10Sps 10 250 GAIN = 2 GAIN = 2, N = 1024 RATE = 10Sps RATE = 10Sps STD DEV = 1.989 LSB 200 5 VREF = 2.5V B) S L E ( S 150 D T CO 0 UN UT CO 100 P T U O -5 50 -10 0 0 200 400 600 800 1000 -8 -6 -4 -2 0 2 4 6 8 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 4. NOISE AT GAIN = 2, 10Sps FIGURE 5. NOISE HISTOGRAM AT GAIN = 2, 10Sps 20 120 GAIN = 64 GAIN = 64, N = 1024 RATE = 10Sps RATE = 10Sps 15 100 STD DEV = 4.627 LSB VREF = 2.5V B) 10 S 80 L E ( 5 S D T O N 60 C U UT 0 CO P UT 40 O -5 20 -10 -15 0 0 200 400 600 800 1000 -20 -15 -10 -5 0 5 10 15 20 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 6. NOISE AT GAIN = 64, 10Sps FIGURE 7. NOISE HISTOGRAM AT GAIN = 64, 10Sps FN6954 Rev 3.00 Page 8 of 23 November 20, 2014

ISL26132, ISL26134 Typical Characteristics (Continued) 50 60 GAIN = 128 GAIN = 128, N = 1024 RATE = 10Sps RATE = 10Sps 30 50 STD DEV = 8.757 LSB VREF = 2.5V B) S 40 L E ( 10 S D T CO UN 30 UT -10 CO P UT 20 O -30 10 -50 0 0 200 400 600 800 1000 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 8. NOISE AT GAIN = 128, 10Sps FIGURE 9. NOISE HISTOGRAM AT GAIN = 128, 10Sps 25 120 GAIN = 1 GAIN = 1, N = 1024 20 RATE = 80Sps RATE = 80Sps 100 STD DEV = 3.791 LSB 15 VREF = 2.5V B) 10 S 80 L E ( 5 S D T CO 0 UN 60 UT -5 CO P UT 40 O -10 -15 20 -20 -25 0 0 200 400 600 800 1000 -15 -10 -5 0 5 10 15 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 10. NOISE AT GAIN = 1, 80Sps FIGURE 11. NOISE HISTOGRAM AT GAIN = 1, 80Sps 25 120 GAIN = 2 GAIN = 2, N = 1024 RATE = 80Sps RATE = 80Sps 100 STD DEV = 3.831 LSB 15 VREF = 2.5V SB) 80 L E ( 5 S D T CO UN 60 PUT -5 CO UT 40 O -15 20 -25 0 0 200 400 600 800 1000 -15 -10 -5 0 5 10 15 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 12. NOISE AT GAIN = 2, 80Sps FIGURE 13. NOISE HISTOGRAM AT GAIN = 2, 80Sps FN6954 Rev 3.00 Page 9 of 23 November 20, 2014

ISL26132, ISL26134 Typical Characteristics (Continued) 100 50 GAIN = 64 GAIN = 64, N = 1024 RATE = 80Sps RATE = 80Sps STD DEV = 12.15 LSB 40 50 VREF = 2.5V B) S L E ( S 30 D T O 0 N C U UT CO 20 P T U O -50 10 -100 0 0 200 400 600 800 1000 -40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 14. NOISE AT GAIN = 64, 80Sps FIGURE 15. NOISE HISTOGRAM AT GAIN = 64, 80Sps 160 30 GAIN = 128 GAIN = 128, N = 1024 120 RATE = 80Sps RATE = 80Sps 25 STD DEV = 23.215 LSB 80 VREF = 2.5V SB) 40 20 L DE ( 0 TS O N 15 C U UT -40 CO P UT -80 10 O -120 5 -160 -200 0 0 200 400 600 800 1000 -80 -60 -40 -20 0 20 40 60 80 TIME (SAMPLES) OUTPUT CODE (LSB) FIGURE 16. NOISE AT GAIN = 128, 80Sps FIGURE 17. NOISE HISTOGRAM AT GAIN = 128, 80Sps 10 10000 8 NORMAL MODE, PGA = 64.128 1000 A) A) NORMAL MODE, ALL PGA GAINS m 6 µ T ( T ( N NORMAL MODE, PGA = 1, 2 N 100 E E R R UR 4 UR C C 10 POWERDOWN MODE 2 0 1 -40 -10 20 50 80 110 -40 -10 20 50 80 110 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 18. ANALOG CURRENT vs TEMPERATURE FIGURE 19. DIGITAL CURRENT vs TEMPERATURE FN6954 Rev 3.00 Page 10 of 23 November 20, 2014

ISL26132, ISL26134 Typical Characteristics (Continued) 11.0 10000 WORD RATE = 10Sps GAIN = 1, 80Sps 64k FFT 10.8 25 AVERAGES 10.6 ps) z) 1000 S H E ( 10.4 V/√ RAT E (n A 10.2 S T OI DA N 100 10.0 9.8 9.6 10 -40 -10 20 50 80 110 0.01 0.1 1 10 TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 20. TYPICAL WORD RATE vs TEMPERATURE USING FIGURE 21. NOISE DENSITY vs FREQUENCY AT GAIN = 1, 80Sps INTERNAL OSCILLATOR 100 GAIN = 128, 80Sps 64k FFT 25 AVERAGES z) H √ V/ n 10 E ( S OI N 1 0.01 0.1 1 10 FREQUENCY (Hz) FIGURE 22. NOISE DENSITY vs FREQUENCY AT GAIN = 128, 80Sps FN6954 Rev 3.00 Page 11 of 23 November 20, 2014

ISL26132, ISL26134 Functional Description The input span of the ADC is ±0.5 VREF/GAIN. For a 5V VREF and a gain of 1x, the input span will be 5VP-P fully differential as Analog Inputs shown in Figure 23. Note that input voltages that exceed the supply rails by more than 100mV will turn on the ESD protection The analog signal inputs to the ISL26132 connect to a 2-Channel diodes and degrade measurement accuracy. differential multiplexer and the ISL26134 connect to a 4-Channel differential multiplexer (Mux). The multiplexer connects a pair of If the differential input exceeds well above the +VE or the -VE FS inputs to the positive and negative inputs (AINx+, AINx-), selected (by ~1.5x times) the output code will clip to the corresponding FS by the Channel Select Pins A0 and A1 (ISL26134 only). Input value. Under such conditions, the output data rate will become channel selection is shown in Table 7. On the ISL26132, the 1/4th of the original value as the Digital State Machine will TEMP pin is used to select the Temperature Sensor function. RESET the Delta-Sigma Modulator and the Decimation Filter. TABLE 7. INPUT CHANNEL SELECTION Temperature Sensor (ISL26132 only) CHANNEL SELECT PINS ANALOG INPUT PINS SELECTED When the TEMP pin of the ISL26132 is set High, the input multiplexer is connected to a pair of diodes, which are scaled in A1 A0 AIN+ AIN- both size and current. The voltage difference measured between 0 0 AIN1+ AIN1- them corresponds to the temperature of the die according to 0 1 AIN2+ AIN2- Equation 1: (EQ. 1) 1 0 AIN3+ AIN3- V= 102.2mV+(379VTC)Gain 1 1 AIN4+ AIN4- Note: Valid only for GAIN = 1x or 2x Whenever the MUX channel is changed (i.e. if any one of the Where T is the temperature of the die, and Gain = the PGA Gain following inputs - A0/A1, Gain1/0, SPEED is changed), the Setting. digital logic will automatically restart the digital filter and will At a temperature of +25°C, the measured voltage will be cause SDO/RDY to go low only when the output is fully settled. approximately 111.7mV. Note that this measurement indicates But if the input itself is suddenly changed, then the user needs to only the temperature of the die itself. Applying the result to ignore the first four RDY pulses (going low) to get an accurate correct for the temperature drift of a device external to the measurement of the input signal. package requires that thermal coupling between the sensor and 1.25V the die be taken into account. Low-Noise Programmable Gain Amplifier 3.75 (PGA) The chopper-stabilized programmable gain amplifier features a 2.50 AIN+ variety of gain settings to achieve maximum dynamic range and measurement accuracy from popular sensor types with excellent low noise performance, input offset error, and low drift, and with minimal external parts count. The GAIN0 and GAIN1 pins allow the 1.25 user to select gain settings of 1x, 2x, 64x, or 128x. A block diagram INPUT VOLTAGE RANGE = ±0.5VREF/GAIN is shown in Figure 24. The differential input stage provides a gain of 64, which is bypassed when the lower gain settings are selected. VREF = 5V, GAIN = 1X The lower gain settings (1and2) will accept inputs with common 3.75 mode voltages up to 100mV outside the rails, allowing the device to accept ground-referred signals. At gain settings of 64 or 128 the common mode voltage at the inputs is limited to 1.5V inside the 2.50 AIN- supply rails while maintaining specified measurement accuracy. 1.25 2.50V FIGURE 23. DIFFERENTIAL INPUT FOR VREF = 5V, GAIN = 1X FN6954 Rev 3.00 Page 12 of 23 November 20, 2014

ISL26132, ISL26134 CAP AINx+ + RINT A1 - RF1 R1 ADC RF2 - RINT A2 AINx- + CAP FIGURE 24. SIMPLIFIED PROGRAMMABLE GAIN AMPLIFIER BLOCK DIAGRAM Filtering PGA Output Noise If the ADC is to be operated from a crystal, it should be located close to the package pins of the ADC. Note that external loading The programmable gain amplifier, as shown in Figure 24, capacitors for the crystal are not required as there are loading includes a passive RC filter on its output. The resistors are capacitors built into the silicon, although the capacitor values are located inside the chip on the outputs of the differential amplifier optimized for operation with a 4.9152MHz crystal. stages. The capacitor (nominally a 100nF C0G ceramic or a PPS film (Polyphenylene sulfide)) for the filter is connected to the two The XTALOUT pin is not intended to drive external circuits. CAP pins of the chip. The outputs of the differential amplifier stages of the PGA are filtered before their signals are presented CRYSTAL to the delta-sigma modulator. This filter reduces the amount of XTALIN/ OSCILLATOR noise by limiting the signal bandwidth and filters the chopping CLOCK CLOCK DETECT artifacts of the chopped PGA stage. Voltage Reference Inputs (VREF+, VREF-) INTERNAL EN The voltage reference for the ADC is derived from the difference OSCILLATOR in the voltages presented to the VREF+ and VREF- pins; XTALOUT VREF=(VREF+ - VREF-). The ADCs are specified with a voltage MUX reference value of 5V, but a voltage reference as low as 1.5V can be used. For proper operation, the voltage on the VREF+ pin TO ADC should not be greater than AVDD + 0.1V and the voltage on the FIGURE 25. CLOCK BLOCK DIAGRAM VREF- pin should not be more negative than AGND - 0.1V. Clock Sources Digital Filter Characteristics The ISL26132, ISL26134 can operate from an internal oscillator, The digital filter inside the ADC is a fourth-order Sinc filter. an external clock source, or from a crystal connected between Figures 26 and 27 on page14 on illustrate the filter response for the XTALIN/CLOCK and XTALOUT pins. See the block diagram of the ADC when it is operated from a 4.9152MHz crystal. The the clock system in Figure25. When the ADC is powered up, the internal oscillator is factory trimmed so the frequency response CLOCK DETECT block determines if an external clock source is for the filter will be much the same when using the internal present. If a clock greater than 300kHz is present on the oscillator. The figures illustrate that when the converter is XTALIN/CLOCK pin, the circuitry will disable the internal oscillator operated at 10Sps the digital filter provides excellent rejection of on the chip and use the external clock as the clock to drive the 50Hz and 60Hz line interference. chip circuitry. If the ADC is to be operated from the internal oscillator, the XTALIN/CLOCK pin should be grounded. FN6954 Rev 3.00 Page 13 of 23 November 20, 2014

ISL26132, ISL26134 Serial Clock Input (SCLK) 0 DDAATTAA RRAATTEE == 1100 SSpPsS The serial clock input is provided with hysteresis to minimize false triggering. Nevertheless, care should be taken to ensure reliable clocking. -50 B) Filter Settling Time and ADC Latency d AIN ( Whenever the analog signal into the ISL26132, ISL26134 G converters is changed, the effects of the digital filter must be -100 taken into account. The filter takes four data ready periods for the output code to fully reflect a new value at the analog input. If the multiplexer control input is changed, the modulator and the digital filter are reset, and the device uses four data ready -150 0 10 20 30 40 50 60 70 80 90 100 periods to fully settle to yield a digital code that accurately FREQUENCY (Hz) represents the analog input. Therefore, from the time the control FIGURE 26. 10Sps: FREQUENCY RESPONSE OUT TO 100Hz inputs for the multiplexer are changed until the SDO/RDY goes low, four data ready periods will elapse. The settling time delay -50 after a multiplexer channel change is listed in Table 8 for the converter operating in continuous conversion mode. This is also -60 DATA RATE = 10Sps shown pictorially in Figure 28 for a change in the MUX setting -70 and Figure 29 for an abrupt change in the analog input VIN. -80 B) -90 d N ( -100 GAI -110 -120 -130 -140 -150 45 50 55 60 65 FREQUENCY (Hz) FIGURE 27. 10Sps: 50/60Hz NOISE REJECTION, 45Hz TO 65Hz TABLE 8. SETTLING TIME DESCRIPTION PARAMETER (fCLK = 4.9152MHz) MIN MAX UNITS tS A0, A1, SPEED, Gain1, Gain0 change 40 50 µs set-up time t1 Settling time SPEED = 1 54 55 ms SPEED = 0 404 405 ms A0, A1, SPEED, Gain1, Gain0 t1 SDO/RDY tS FIGURE 28. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE FN6954 Rev 3.00 Page 14 of 23 November 20, 2014

ISL26132, ISL26134 Abrupt Change in External VIN VIN 1st conversion; 2ndconversion; 3rdconversion; 4thconversion; 5thconversion; Start of includes VIN settled, VIN settled, VIN settled, VIN and Digital, conversion unsettled VIN Digital filter Digital filter Digital filter filter settled unsettled unsettled unsettled SDO/RDY Conversion time FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE Conversion Data Rate Reading Conversion Data from the Serial Data Output/Ready SDO/RDY Pin The SPEED pin is used to select between the 10Sps and 80Sps conversion rates. The 10Sps rate (SPEED = Low) is preferred in When the ADC is powered, it will automatically begin doing applications requiring 50/60Hz noise rejection. Note that the conversions. The SDO/RDY signal will go low to indicate the sample rate is directly related to the oscillator frequency, as completion of a conversion. After the SDO/RDY signal goes low, 491,520 clocks are required to perform a conversion at the the MSB data bit of the conversion word will be output from the 10Sps rate, and 61,440 clocks at the 80Sps rate. SDO/RDY pin after SCLK is transitioned from a low to a high. Each subsequent new data bit is also output on the rising edge of Output Data Format SCLK (see Figure 30). The receiving device should use the falling The 24-bit converter output word is delivered in two’s edge of SCLK to latch the data bits. After the 24th SCLK, the complement format. Input exceeding full scale results in a SDO/RDY output will remain in the state of the LSB data bit until clipped output which will not return to in-range values until after a new conversion is completed. At this time, the SDO/RDY will go the input signal has returned to the specified allowable voltage high if low and then go low to indicate that a new conversion range and the digital filter has settled as discussed previously. word is available. If not all data bits are read from the SDO/RDY pin prior to the completion of a new conversion, they will be TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT overwritten. SCLK should be low during time t6, as shown in INPUT SIGNAL OUTPUT CODE (HEX) Figure 30, when SDO/RDY is high. +0.5VREF/GAIN 7FFFFF If the user wants the SDO/RDY signal to go high after reading the (+0.5VREF/GAIN)/(223 - 1) 000001 24 bits of the conversion data word, a 25th SCLK can be issued. The 25th SCLK will force the SDO/RDY signal to go high and 0 000000 remain high until it falls to signal that a new conversion word is (-0.5VREF/GAIN)/(223 - 1) FFFFFF available. Figure31 illustrates the behavior of the SDO/RDY signal when a 25th SCLK is used. -0.5VREF/GAIN 800000 DATA DDAATTAA RREEAADDYY NEW DATA READY MSB LSB SDO/RDY 23 22 21 0 t4 t5 t3 t6 t2 SCLK 1 24 t3 t7 FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA FN6954 Rev 3.00 Page 15 of 23 November 20, 2014

ISL26132, ISL26134 TABLE 10. INTERFACE TIMING CHARACTERISTICS PARAMETER DESCRIPTION MIN TYP MAX UNITS t2 SDO/RDY Low to first SLK 0 ns t3 SCLK pulsewidth, Low or High 100 ns t4 SCLK High to Data Valid 50 ns t5 Data Hold after SCLK High 0 ns t6 Register Update Time 39 µs t7 Conversion Period SPEED = 1 12.5 ms SPEED = 0 100 ms DATA DATA READY NEW DATA READY SDO/RDY 23 22 21 0 25TH SCLK FORCES SDO/RDY HIGH SCLK 1 24 25 FIGURE 31. OUTPUT DATA WAVEFORMS FOR SDO/RDY POLLING DATA READY AFTER CALIBRATION SDO/RDY 23 22 21 0 23 CALIBRATION BEGINS SCLK 1 24 25 26 t8 FIGURE 32. OFFSET CALIBRATION WAVEFORMS crystal oscillator amplifier. To enter the standby mode, take the Offset Calibration Control SCLK signal high and hold it high after SDO/RDY falls. The The offset internal to the ADC can be removed by performing an converter will remain in standby mode as long as SCLK is held offset calibration operation. Offset calibration can be initiated high. To return to normal operation, take SCLK back low and wait immediately after reading a conversion word with 24 SCLKs by for the SDO/RDY to fall to indicate that a new conversion has issuing two additional SCLKs. The offset calibration operation will completed. Figure 33 and Table 12 illustrate the details of begin immediately after the 26th SCLK occurs. Figure 32 standby mode. illustrates the timing details for the offset calibration operation. Supply currents are equal in Standby and Power-down modes unless a Crystal is used. If the Crystal is used, the Crystal During offset calibration, the analog inputs are shorted internally amplifier is turned ON, even in the standby mode. and a regular conversion is performed. This conversion generates a conversion word that represents the offset error. This value is Performing Offset Calibration After Standby stored and used to digitally remove the offset error from future Mode conversion words. The SDO/RDY output will fall to indicate the completion of the offset calibration operation. To perform an offset calibration automatically upon returning from standby, deliver two or more additional SCLKs following a TABLE 11. SDO/RDY DELAY AFTER CALIBRATION data read cycle, and then set and hold SCLK high. The device will PARAMETER MIN MAX UNITS remain in Standby as long as SCLK remains high. A calibration t8 SPEED = 1 108 109 ms cycle will begin once SCLK is brought low again to resume normal operation. Additional time will be required to perform the SPEED = 0 808 809 ms calibration after returning from Standby. Figure 34 and Table 13 Standby Mode Operation illustrate the details of performing offset calibration after standby mode. The ADC can be put into standby mode to save power. Standby mode reduces the power to all circuits in the device except the FN6954 Rev 3.00 Page 16 of 23 November 20, 2014

ISL26132, ISL26134 STANDBY MODE DATA READY SDO/RDY 23 22 21 0 23 START CONVERSION SCLK 1 24 t9 t10 t11 FIGURE 33. STANDBY MODE WAVEFORMS TABLE 12. STANDBY MODE TIMING PARAMETER DESCRIPTION MIN MAX UNITS t9 SCLK High after SPEED = 1 0 12.44 ms SDO/RDY Low SPEED = 0 0 99.94 ms t10 Standby Mode Delay SPEED = 1 12.5 ms SPEED = 0 100 ms t11 SDO/RDY falling edge SPEED = 1 50 60 ms after SCLK Low SPEED = 0 400 410 ms TABLE 13. OFFSET CALIBRATION TIMING AFTER STANDY PARAMETER DESCRIPTION MIN MAX UNITS t12 SDO/RDY Low after SPEED = 1 108 113 ms SCLK Low SPEED = 0 808 813 ms STANDBY MODE DATA READY AFTER CALIBRATION SDO/RDY 23 22 2211 0 23 BEGIN CALIBRATION SCLK 1 24 25 t10 t12 FIGURE 34. OFFSET CALIBRATION WAVEFORMS AFTER STANDBY FN6954 Rev 3.00 Page 17 of 23 November 20, 2014

ISL26132, ISL26134 Operation of PDWN AVDD PDWN must transition from low to high after both power supplies DVDD have settled to specified levels in order to initiate a correct power-up reset (Figure 35). This can be implemented by an external controller or a simple RC delay circuit, as shown in PDWN Figure 36. 10µs In order to reduce power consumption, the user can assert the Power-down mode by bringing PDWN Low as shown in Figure 37. FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES All circuitry is shut down in this mode, including the Crystal Oscillator. After PDWN is brought High to resume operation, the DVDD reset delay varies depending on the clock source used. While an external clock source will resume operation immediately, a circuit utilizing a crystal will incur about a 20ms delay due to the inherent start-up time of this type of oscillator. 1k CONNECT TO PDWN PIN 2.2nF FIGURE 36. PDWNDELAY CIRCUIT START DATA POWER-DOWN CLK CONVERSION READY SOURCE MODE WAKEUP PDWN tt1144 SDO/RDY t13 t11 SCLK FIGURE 37. POWER-DOWN MODE WAVEFORMS TABLE 14. POWER-DOWN RECOVERY TIMING PARAMETER DESCRIPTION TYP UNITS t13 Clock Recovery after PDWN Internal Oscillator 7.95 µs High External Clock Source 0.16 µs 4.9152MHz Crystal 5.6 ms Oscillator t14 PDWN Pulse Duration 26 µs (min) FN6954 Rev 3.00 Page 18 of 23 November 20, 2014

ISL26132, ISL26134 Application Information Application Examples Power-up Sequence – Initialization and WEIGH SCALE SYSTEM Configuration Figure 38 illustrates the ISL26132 connected to a load cell. The A/D converter is configured for a gain of 128x and a sample rate The sequence to properly power-up and initialize the device are of 10Sps. If a load cell with 2mV/V sensitivity is used, the full as follows. For details on individual functions, refer to their scale output from the load cell will be 10mV. On a gain of 128x descriptions. and sample rate of 10Sps, the converter noise is 67nVP-P. The 1. AVDD, DVDD ramp to specified levels converter will achieve 10mV/67nVP-P = 149,250 noise free 2. Apply External Clock counts across its 10mV input signal. This equates to 14,925 counts per millivolt of input signal. If five output words are 3. Pull PDWN High to initiate Reset averaged together this can be improved by √5 to yield √5*14925 4. Device begins conversion counts=33,370 counts per millivolt of input signal with an 5. SDO/RDY goes low at end of first conversion effective update rate of 2 readings per second. OPTIONAL ACTIONS • Perform Offset Calibration • Place device in Standby • Return device from Standby • Read on-chip Temperature (applicable to ISL26132 only) 5V 3V 0.1µF 18 1 AVDD DVDD VDD 20 GAIN1 16 VREF+ 19 GAIN0 9 GAIN = 128 CAP 24 0.1µF SDO/RDY - + 10 CAP SCLK 23 CONMTIRCORLOLER 22 ISL26132 PDWN 4 11 XTALOUT AIN+1 12 AIN-1 14 XTALIN/CLOCK 3 AIN+2 21 13 SPEED AIN-2 8 A0 15 VREF- TEMP 7 AGND DGND GND 17 2, 5, 6 FIGURE 38. WEIGH SCALE APPLICATION FN6954 Rev 3.00 Page 19 of 23 November 20, 2014

ISL26132, ISL26134 +5V +3V 0.1µF 0.1µF 18 1 AVDD DVDD 5M IS4L.029160V09 16 VREF+ GAIN1 20 10nF GAIN0 19 24 SDO/RDY 23 MICRO SCLK CONTROLLER 22 10k PDWN 11 AIN+1 4 XTALOUT TYPE K 10k 12 AIN-1 1µF 14 XTALIN/CLOCK 3 4.9152 AIN+2 21 MHz 13 SPEED AIN-2 8 5M A0 15 7 VREF- TEMP AGND DGND 17 2, 5, 6 FIGURE 39. THERMOCOUPLE MEASUREMENT APPLICATION THERMOCOUPLE MEASUREMENT PCB Board Layout and System Figure 39 illustrates the ISL26132 in a thermocouple Configuration application. The 4.096V reference combined with the PGA gain set to 128x sets the input span of the converter to ±16mV. This The ISL26132, ISL26134 ADC is a very low noise converter. To supports the K type thermocouple measurement for achieve the full performance available from the device will require attention to the printed circuit layout of the circuit board. temperatures from -270°C at -6.485mV to +380°C at about Care should be taken to have a full ground plane without 16mV. impairments (traces running through it) directly under the chip If a higher temperature is preferred, the PGA can be set to 64x to on the back side of the circuit board. The analog input signals provide a converter span of ±32mV. This will allow the converter should be laid down adjacent (AIN+ and AIN- for each channel) to to support temperature measurement with the K type achieve good differential signal practice and routed away from thermocouple up to about +765°C. any traces carrying active digital signals. The connections from the CAP pins to the off-chip filter capacitor should be short, and Figure 39 shows that the thermocouple is referenced to a voltage without any digital signals nearby. The crystal, if used, should be dictated by the resistor divider from the +5V supply to ground. connected with relatively short leads. No active digital signals These set the common mode voltage at about 2.5V. The 5M should be routed near or under the crystal case or near the resistors provide a means for detection of an open thermocouple. traces, which connect it to the ADC. The AGND and DGND pins of If the thermocouple fails to open or is not connected, the bias the ADC should be connected to a common solid ground plane. through the 5M resistors will cause the input to the PGA to go to All digital signals to the chip should be powered from the same full scale. supply, as that used for DVDD (do not allow digital signals to be active high unless the DVDD supply to the chip is alive). Route all active digital signals in a way to keep distance from any analog pin on the device (AIN, VREF, CAP, AVDD). Power on the AVDD supply should be active before the VREF voltage is present. PCB layout patterns for the chips (ISL26132 and ISL26134) are found on the respective package outline drawings on pages 22 and 23. FN6954 Rev 3.00 Page 20 of 23 November 20, 2014

ISL26132, ISL26134 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE November 20, 2014 FN6954.3 Datasheet updated with minor text and graphic changes. November 12, 2012 FN6954.2 Changed in Abs Max Rating on page5 Latchup JESD from 78B to 78C Electrical Spec Table Gain Drift on page5 changed the following: Added Gain = 64 and Typical value of 3.5 Changed Gain = 128 Typical value from 7 to 3.5 Table 5 on page7 changed the following: Gain 64 RMS changed from 10.8 to 11.3 Peak to Peak from 71 to 75 NFB from 20.1 to 20 Gain 128 RMS changed from 10.2 to 10.6 Peak to Peak from 67 to 70 NFB from 19.1 to 19 Table 6 on page7 changed the following: Gain 64 RMS changed from 28.3 to 29.5 Peak to Peak from 187 to 194.8 NFB from 18.7 to 18.6 Gain 128 RMS changed from 27 to 28.2 Peak to Peak from 178 to 186.1 NFB from 17.7 to 17.6 September 08, 2011 FN6954.1 Power Supply Requirements on page6 - AIDD - Analog Supply Current - Normal Mode, AVDD = 5, Gain=1,2 changed TYP and MAX from “6, 7.3” to “7, 8.5” Power Dissipation, Total Normal Mode, AVDD = 5, Gain = 1, 2 changed from “43.3” to “49.6” mW (Max) August 22, 2011 FN6954.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2011-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6954 Rev 3.00 Page 21 of 23 November 20, 2014

ISL26132, ISL26134 Package Outline Drawing M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 24 13 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 C B A 1 12 +0.05 0.65 B 0.15 -0.06 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90+0.15 -0.10 1.20 MAX GAUGE SEATING PLANE PLANE 0.25 0.25+0.05 5 -0.06 0°-8° 0.10C 0.10MCBA 0.05 MIN 0.15 MAX 0.60± 0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN6954 Rev 3.00 Page 22 of 23 November 20, 2014

ISL26132, ISL26134 Package Outline Drawing M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 9.70± 0.10 SEE DETAIL "X" 28 15 6.40 PIN #1 4.40 ± 0.10 I.D. MARK 2 3 0.20 C B A 1 14 +0.05 0.15 0.65 B -0.06 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90+0.15 -0.10 1.20 MAX GAUGE PLANE 0.25 SEATING PLANE +0.05 0.25-0.06 5 0.05 MIN 0°-8° 0.10C 0.10MCBA 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) is 0.07mm. 6. Dimension in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153. FN6954 Rev 3.00 Page 23 of 23 November 20, 2014