DATASHEET ISL23425 FN7873 Dual, 256-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) Rev 1.00 September 11, 2015 The ISL23425 is a volatile, low voltage, low noise, low power, Features 256-tap, dual digitally controlled potentiometer (DCP) with an SPI Bus™ interface. It integrates two DCP cores, wiper switches • Two potentiometers per package and control logic on a monolithic CMOS integrated circuit. • 256 resistor taps Each digitally controlled potentiometer is implemented with a • 10k 50kor 100k total resistance combination of resistor elements and CMOS switches. The • SPI serial interface position of the wipers are controlled by the user through the - No additional level translator for low bus supply SPI bus interface. Each potentiometer has an associated volatile Wiper Register (WRi, i = 0, 1) that can be directly written - Daisy Chaining of multiple DCPs to and read by the user. The contents of the WRi controls the • Maximum supply current without serial bus activity position of the wiper. When powered on, the wiper of each DCP (standby) will always commence at mid-scale (128 tap position). - 4µA @ VCC and VLOGIC = 5V The low voltage, low power consumption, and small package - 1.7µA @ VCC and VLOGIC = 1.7V of the ISL23425 make it an ideal choice for use in battery • Shutdown Mode operated equipment. In addition, the ISL23425 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the - Forces the DCP into an end-to-end open circuit and RWi is VCC value. This allows for low logic levels to be connected connected to RLi internally directly to the ISL23425 without passing through a voltage - Reduces power consumption by disconnecting the DCP level shifter. resistor from the circuit The DCP can be used as a three-terminal potentiometer or as a • Power supply two-terminal variable resistor in a wide variety of applications - VCC = 1.7V to 5.5V analog power supply including control, parameter adjustments, and signal processing. - VLOGIC = 1.2V to 5.5V SPI bus/logic power supply Applications • Wiper resistance: 70 typical @ VCC = 3.3V • Power supply margining • Power-on preset to mid-scale (128 tap position) • Trimming sensor circuits • Extended industrial temperature range: -40°C to +125°C • Gain adjustment in battery powered instruments • 14 Ld TSSOP or 16 Ld µTQFN packages • RF power amplifier bias compensation • Pb-free (RoHS compliant) 10000 VREF 8000 Ω) E ( 6000 RH1 C AN - VREF_M T ESIS 4000 1 ODCFP RW1 + R ISL23325 ISL28114 2000 RL1 0 0 64 128 192 256 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. VREF ADJUSTMENT POSITION, 10kΩ DCP FN7873 Rev 1.00 Page 1 of 20 September 11, 2015

ISL23425 Block Diagram VLOGIC VCC RH0 RH1 SCK POWER UP SDI INTERFACE, SPI CONTROL SDO INTERFACE AND WR0 WR1 CS STATUS VOLATILE VOLATILE LOGIC REGISTER REGISTER AND AND WIPER WIPER CONTROL CONTROL CIRCUITRY CIRCUITRY GND RW0 RL0 RW1 RL1 Pin Configurations Pin Descriptions ISL23425 TSSOP µTQFN SYMBOL DESCRIPTION (14 LD TSSOP) 1, 7 5, 6, 15 GND Ground pin TOP VIEW 2 16 VLOGIC SPI bus/logic supply Range 1.2V to 5.5V GND 1 14 VCC 3 1 SDO Logic Pin - Serial bus data output VLOGIC 2 13 RL0 (configurable) SDO 3 12 RW0 4 2 SCK Logic Pin - Serial bus clock input SCK 4 11 RH0 5 3 SDI Logic Pin - Serial bus data input SDI 5 10 RH1 6 4 CS Logic Pin - Active low chip select CS 6 9 RW1 8 8 RL1 DCP1 “low” terminal GND 7 8 RL1 9 9 RW1 DCP1 wiper terminal 10 10 RH1 DCP1 “high” terminal ISL23425 11 11 RH0 DCP0 “high” terminal (16 LD µTQFN) TOP VIEW 12 12 RW0 DCP0 wiper terminal C LOGI ND CC L0 13 13 RL0 DCP0 “low” terminal V G V R 14 14 VCC Analog power supply. 6 5 4 3 Range 1.7V to 5.5V 1 1 1 1 SDO 1 12 RW0 7 NC Not Connected SCK 2 11 RH0 SDI 3 10 RH1 CS 4 9 RW1 5 6 7 8 D D C 1 N N N L G G R FN7873 Rev 1.00 Page 2 of 20 September 11, 2015

ISL23425 Ordering Information RESISTANCE PART NUMBER PART OPTION TEMP RANGE PACKAGE PKG. (Note 5) MARKING (kΩ) (°C) (Pb-free) DWG. # ISL23425TFVZ (Notes 1, 3) 23425 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23425UFVZ (Notes 1, 3) (No longer 23425 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 available, recommended replacement: ISL23425TFRUZ-TK) 23425WFVZ (Notes 1, 3) 23425 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23425TFRUZ-T7A (Notes 2, 4) GBJ 100 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A ISL23425TFRUZ-TK (Notes 2, 4) GBJ 100 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A ISL23425UFRUZ-T7A (Notes 2, 4) (No GBH 50 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A longer available, recommended replacement: ISL23425TFRUZ-TK) ISL23425UFRUZ-TK (Notes 2, 4) (No longer GBH 50 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A available, recommended replacement: ISL23425TFRUZ-TK) ISL23425WFRUZ-T7A (Notes 2, 4) GBG 10 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A ISL23425WFRUZ-TK (Notes 2, 4) GBG 10 -40 to +125 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23425. For more information on MSL please see techbrief TB363. FN7873 Rev 1.00 Page 3 of 20 September 11, 2015

ISL23425 Absolute Maximum Ratings Thermal Information Supply Voltage Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 14 Ld TSSOP Package (Notes 6, 7) . . . . . . 112 40 VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 16 Ld µTQFN Package (Notes 6, 7) . . . . . . 110 64 Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Voltage on Any Digital Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Wiper current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .4.5kV CDM Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . . . . . . . . 1kV Recommended Operating Conditions Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7V to 5.5V VLOGIC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA 7. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS RTOTAL RH to RL Resistance W option 10 kΩ U option 50 kΩ T option 100 kΩ RH to RL Resistance Tolerance -20 ±2 +20 % End-to-End Temperature Coefficient W option 125 ppm/°C U option 65 ppm/°C T option 45 ppm/°C VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0 VCC V RW Wiper Resistance RH - floating, VRL = 0V, force IW current to 70 200 Ω the wiper, IW = (VCC - VRL)/RTOTAL, VCC=2.7V to 5.5V VCC = 1.7V 580 Ω CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page8 32/32/32 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB PSRR Power Supply Reject Ratio Wiper output change if VCC change -75 dB ±10%; wiper at middle point VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity, Guaranteed W option -1.0 ±0.5 +1.0 LSB (Note 13) Monotonic (Note 9) U, T option -0.5 ±0.15 +0.5 LSB (Note 9) FN7873 Rev 1.00 Page 4 of 20 September 11, 2015

ISL23425 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS DNL Differential Non-linearity, Guaranteed W option -1 ±0.4 +1 LSB (Note 12) Monotonic (Note 9) U, T option -0.4 ±0.1 +0.4 LSB (Note 9) FSerror Full-scale Error W option -5 -2 0 LSB (Note 11) (Note 9) U, T option -2 -0.5 0 LSB (Note 9) ZSerror Zero-scale Error W option 0 2 5 LSB (Note 10) (Note 9) U, T option 0 0.4 2 LSB (Note 9) Vmatch DCP to DCP Matching DCPs at same tap position, same voltage -2 ±0.5 2 LSB (Note 22) at all RH terminals, and same voltage at (Note 9) all RL terminals TCV Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C (Note 14) U option, Wiper Register set to 80 hex 4 ppm/°C T option, Wiper Register set to 80 hex 2.3 ppm/°C tLS_Settling Large Signal Wiper Settling Time From code 0 to FF hex, measured from 0 300 ns to 1 LSB settling of the wiper fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-Linearity, Guaranteed W option; VCC = 2.7V to 5.5V -2.0 ±1 +2.0 MI (Note 18) Monotonic (Note 15) W option; VCC = 1.7V 10.5 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -1.0 ±0.3 +1.0 MI (Note 15) U, T option; VCC = 1.7V 2.1 MI (Note 15) RDNL Differential Non-Linearity, Guaranteed W option; VCC = 2.7V to 5.5V -1 ±0.4 +1 MI (Note 17) Monotonic (Note 15) W option; VCC = 1.7V ±0.6 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 15) U, T option; VCC = 1.7V ±0.35 MI (Note 15) Roffset Offset, wiper at 0 position W option; VCC = 2.7V to 5.5V 0 3 5.5 MI (Note 16) (Note 15) W option; VCC = 1.7V 6.3 MI (Note 15) U, T option; VCC = 2.7V to 5.5V 0 0.5 2 MI (Note 15) U, T option; VCC = 1.7V 1.1 MI (Note 15) Rmatch DCP to DCP Matching Any two DCPs at the same tap position -2 ±0.5 2 LSB (Note 23) with the same terminal voltages (Note 9) FN7873 Rev 1.00 Page 5 of 20 September 11, 2015

ISL23425 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS TCR Resistance temperature coefficient W option; Wiper register set between 32 170 ppm/°C (Note 19) hex and FF hex U option; Wiper register set between 80 ppm/°C 32hex and FF hex T option; Wiper register set between 50 ppm/°C 32hex and FF hex Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V, 1.5 mA fSCK = 5MHz (for SPI active read and write) VLOGIC = 1.2V, VCC = 1.7V, 30 µA fSCK = 1MHz (for SPI active read and write) ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 100 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V, 2 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.5 µA SPI interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, 2 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1.2 µA SPI interface in standby ILOGIC VLOGIC Shutdown Current VLOGIC = VCC = 5.5V, 2 µA SHDN SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.5 µA SPI interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, 2 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1.2 µA SPI interface in standby ILkgDig Leakage Current, at Pins CS, SDO, SDI, SCK Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA tDCP Wiper Response Time CS rising edge to the new position of the 0.4 µs wiper (changes from 10% to 90% FS) 1.5 µs W, U, T options specified top to bottom 3.5 µs tShdnRec DCP Recall Time from Shutdown Mode CS rising edge to wiper recalled position 1.5 µs and RH connection VCC, VLOGIC VCC ,VLOGIC Ramp Rate (Note 21) Ramp monotonic at any level 0.01 50 V/ms Ramp Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note 8) (Note 20) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC+ 0.3 V Hysteresis SDI and SCK Input Buffer VLOGIC > 2V 0.05 x VLOGIC V Hysteresis VLOGIC < 2V 0.1 x VLOGIC V FN7873 Rev 1.00 Page 6 of 20 September 11, 2015

ISL23425 Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note 8) (Note 20) UNITS VOL SDO Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V Rpu SDO Pull-Up Resistor Off-Chip Maximum is determined by 1.5 kΩ tRO and tFO with maximum bus load Cb = 30pF, fSCK=5MHz Cpin SCK, SDO, SDI, CS Pin Capacitance 10 pF fSCK SCK Frequency VLOGIC = 1.7V to 5.5V 5 MHz VLOGIC = 1.2V to 1.6V 1 MHz tCYC SPI Clock Cycle Time VLOGIC ≥ 1.7V 200 ns tWH SPI Clock High Time VLOGIC ≥ 1.7V 100 ns tWL SPI Clock Low Time VLOGIC ≥ 1.7V 100 ns tLEAD Lead Time VLOGIC ≥ 1.7V 250 ns tLAG Lag Time VLOGIC ≥ 1.7V 250 ns tSU SDI, SCK and CS Input Setup Time VLOGIC ≥ 1.7V 50 ns tH SDI, SCK and CS Input Hold Time VLOGIC ≥ 1.7V 50 ns tRI SDI, SCK and CS Input Rise Time VLOGIC ≥ 1.7V 10 ns tFI SDI, SCK and CS Input Fall Time VLOGIC ≥ 1.7V 10 20 ns tDIS SDO Output Disable Time VLOGIC ≥ 1.7V 0 100 ns tSO SDO Output Setup Time VLOGIC ≥ 1.7V 50 ns tV SDO Output Valid Time VLOGIC ≥ 1.7V 150 ns tHO SDO Output Hold Time VLOGIC ≥ 1.7V 0 ns tRO SDO Output Rise Time Rpu = 1.5k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 1.5k, Cbus = 30pF 60 ns tCS CS Deselect Time 2 µs NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255 14. TC = M------a---x------V------R-----W-------i------–----M-----i--n------V-------R----W--------i---------1----0----6------- for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage V VRWi+25°C +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255. 6 19. MaxRi–MinRi 10 for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the TC = ---------------------------------------------------------------------------- R Ri+25°C +165°C minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC first followed by the VCC. 22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 255, x = 0 to 1 and y = 0 to 1. 23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 255 , x = 0 to 1 and y = 0 to 1. FN7873 Rev 1.00 Page 7 of 20 September 11, 2015

ISL23425 DCP Macro Model RTOTAL RH RL CL CH CW 32pF 32pF 32pF RW Timing Diagrams Input Timing tCS CS tLEAD tCYC tLAG SCK ... tSU tH tWL tWH tFI tRI MSB ... LSB SDI SDO Output Timing CS SCK ... tSO tHO tDIS SDO MSB ... LSB tV SDI ADDR XDCP™ Timing (for All Load Instructions) CS tDCP SCK ... SDI MSB ... LSB VW SDO *When CS is HIGH SDO at Z or Hi-Z state FN7873 Rev 1.00 Page 8 of 20 September 11, 2015

ISL23425 Typical Performance Curves 0.4 0.08 0.2 0.04 )B )B S S L( NL 0 L( LN 0.00 D D -0.2 -0.04 -0.4 -0.08 0 64 128 192 256 0 64 128 192 256 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C 0.80 0.16 0.40 0.08 )BSL( LNI 0.00 B)SL( NLI 0.00 -0.40 -0.08 -0.80 -0.16 0 64 128 192 256 0 64 128 192 256 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.40 0.10 0.20 0.05 )IM( LNDR 0.00 )IM( LNRD 0.00 -0.20 -0.05 -0.40 -0.10 0 64 128 192 256 0 64 128 192 256 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7873 Rev 1.00 Page 9 of 20 September 11, 2015

ISL23425 Typical Performance Curves (Continued) 0.80 0.14 0.40 0.07 )IM )IM ( L 0.00 ( L 0.00 N N IR IR -0.40 -0.07 -0.80 -0.14 0 64 128 192 256 0 64 128 192 256 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 120 +25°C +125°C +25°C +125°C 100 80 ) ) ( E ( E 80 C C N 60 N A A T T S S 60 IS IS ER 40 ER -40°C RE -40°C RE 40 P P IW IW 20 20 0 0 0 64 128 192 256 0 64 128 192 256 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 400 80 300 60 )C°/mp 200 )C°/m p p 40 ( vC p( v T C T 100 20 0 15 63 111 159 207 255 0 15 63 111 159 207 255 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V FN7873 Rev 1.00 Page 10 of 20 September 11, 2015

ISL23425 Typical Performance Curves (Continued) 800 250 200 600 )C )C 150 °/m °/m p 400 p p p r( C (r C 100 T T 200 50 0 0 15 63 111 159 207 255 15 63 111 159 207 255 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 15. 10kΩ TCr vs TAP POSITION FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V 50 150 40 120 )C°/m 30 )C°/m 90 p p p( vC 20 pr( C 60 T T 10 30 0 0 15 63 111 159 207 255 15 63 111 159 207 255 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V SCK CLOCK WIPER CS RISING RW PIN CH1: 1V/DIV, 1µs/DIV CH1: 20mV/DIV, 2µs/DIV CH2: 10mV/DIV, 1µs/DIV CH2: 2V/DIV, 2µs/DIV   FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH FN7873 Rev 1.00 Page 11 of 20 September 11, 2015

ISL23425 Typical Performance Curves (Continued) 1V/DIV 0.5V/DIV 0.2µs/DIV 20µs/DIV VCC CS RISING WIPER WIPER   FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: RH TERMINAL 1.8 CH2: RW TERMINAL 1.6 )A µ 1.4 ( C I TC 1.2 N E 1.0 RR VCC = 5.5V, VLOGIC = 5.5V U 0.8 C Y B 0.6 D N AT 0.4 VCC = 1.7V, VLOGIC = 1.2V S 0.2 0 0.5V/DIV, 0.2µs/DIV -40 -15 10 35 60 85 110 -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Potentiometers Pins Power Pins RHI AND RLI VCC The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the Power terminal for the potentiometer section analog power ISL23425 are equivalent to the fixed terminals of a mechanical source. Can be any value needed to support voltage range of DCP potentiometer. RHi and RLi are referenced to the relative position pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. of the wiper and not the voltage potential on the terminals. With Bus Interface Pins WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. SERIAL CLOCK (SCK) RWI This input is the serial clock of the SPI serial interface. RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the SERIAL DATA INPUT (SDI) movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. The SDI is a serial data input pin for SPI interface. It receives operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. FN7873 Rev 1.00 Page 12 of 20 September 11, 2015

ISL23425 SERIAL DATA OUTPUT (SDO) the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi The SDO is a serial data output pin. During a read cycle, the data decreases monotonically. bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the following rising edge of SCK. While the ISL23425 is being powered up, both WRi are reset to 80h (128 decimal), which positions RWi at the center between The output type is configured through ACR[1] bit for Push-Pull or RLi and RHi. Open Drain operation. Default setting for this pin is Push-Pull. An external pull-up resistor is required for Open Drain output The WRi can be read or written to directly using the SPI serial operation. When CS is HIGH, the SDO pin is in tri-state (Z) or interface as described in the following sections. high-tri-state (Hi-Z) depends on the selected configuration. Memory Description CHIP SELECT (CS) The ISL23425 contains three volatile 8-bit registers: Wiper Register CS LOW enables the ISL23425, placing it in the active power WR0, Wiper Register WR1, and Access Control Register (ACR). mode. A HIGH to LOW transition on CS is required prior to the Memory map of ISL23425 is shown in Table 1. The Wiper Register start of any operation after power-up. When CS is HIGH, the WR0 at address 0, contains current wiper position of DCP0; The ISL23425 is deselected and the SDO pin is at high impedance, Wiper Register WR1 at address 1 contains current wiper position of and the device will be in the standby state. DCP1. The Access Control Register (ACR) at address 10h contains information and control bits described in Table 2. V LOGIC Digital power source for the logic control section. It supplies an TABLE 1. MEMORY MAP internal level translator for 1.2V to 5.5V serial bus operation. Use ADDRESS VOLATILE DEFAULT SETTING the same supply as the I2C logic source. (hex) REGISTER NAME (hex) Principles of Operation 10 ACR 40 1 WR1 80 The ISL23425 is an integrated circuit incorporating two DCPs with its associated registers and an SPI serial interface providing 0 WR0 80 direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected TABLE 2. ACCESS CONTROL REGISTER (ACR) in series. At either end of the array and between each resistor is BIT # 7 6 5 4 3 2 1 0 an electronic switch that transfers the potential at that point to the wiper. NAME/ 0 SHDN 0 0 0 0 SDO 0 VALUE The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap The SDO bit (ACR[1]) configures type of SDO output pin. The positions. default value of SDO bit is 0 for Push-Pull output. The SDO pin can be configured as Open Drain output for some applications. In Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC this case, an external pull-up resistor is required, reference the level at any conditions during power-up and normal operation. “Serial Interface Specification” on page6. The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the SPI logic source Shutdown Function which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is The SHDN bit (ACR[6]) disables or enables shutdown mode for all extremely important in systems where the master supply has DCP channels simultaneously. When this bit is 0, i.e., each DCP is lower levels than DCP analog supply. forced to end-to-end open circuit and each RW shorted to RL through a 2kΩ serial resistor as shown in Figure 25. Default value DCP Description of the SHDN bit is 1. Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are RH equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal RW within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WR of a DCP contains all zeroes 2kΩ (WRi[7:0]=00h), its wiper terminal (RWi) is closest to its “Low” terminal (RLi). When the WRi register of a DCP contains all ones RL (WRi[7:0]= FFh), its wiper terminal (RWi) is closest to its “High” terminal (RHi). As the value of the WRi increases from all zeroes FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At FN7873 Rev 1.00 Page 13 of 20 September 11, 2015

ISL23425 When the device enters shutdown, all current DCP WR settings are SPI Serial Interface maintained. When the device exits shutdown, the wipers will The ISL23425 supports an SPI serial protocol, mode 0. The return to the previous WR settings after a short settling time device is accessed via the SDI input and SDO output with data (seeFigure26). clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL23425. The SCK and CS lines are controlled by the host or master. The ISL23425 operates only as a slave device. V) (W All communication over the SPI interface is conducted by VR POWER-UP MID SCALE = 80H sending the MSB of each byte of data first. E, G A USER PROGRAMMED AFTER SHDN Protocol Conventions T L O V The SPI protocol contains Instruction Byte followed by one or more R SHDN ACTIVATED SHDN RELEASED Data Bytes. A valid Instruction Byte contains instruction as the three E WIPER RESTORE TO P WI THE ORIGINAL POSITION MSBs, with the following five register address bits (see Table3). SHDN MODE The next byte sent to the ISL23425 is the Data Byte. 0 TIME (s) TABLE 3. INSTRUCTION BYTE FORMAT FIGURE 26. SHUTDOWN MODE WIPER RESPONSE BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 Table 4 contains a valid instruction set for ISL23425. If the [R4:R0] bits are zero or one, then the read or write is to the WRi register. If the [R4:R0] are 10000, then the operation is to theACR. TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRTE 1 0 0 R4 R3 R2 R1 R0 WRi or ACR READ 1 1 0 R4 R3 R2 R1 R0 WRi or ACR WRTE Where X means “do not care”. FN7873 Rev 1.00 Page 14 of 20 September 11, 2015

ISL23425 CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 27. TWO BYTE WRITE SEQUENCE CS 1 8 16 24 32 SCK RD ADDR NOP SDI RD ADDR READ DATA SDO FIGURE 28. FOUR BYTE READ SEQUENCE Write Operation Read Operation A write operation to the ISL23425 is a two or more bytes A Read operation to the ISL23425 is a four byte operation. It operation. It requires first, the CS transition from HIGH-to-LOW. requires first, the CS transition from HIGH-to-LOW. Then the host Then the host sends a valid Instruction Byte, followed by one or sends a valid Instruction Byte, followed by a “dummy” Data Byte, more Data Bytes to the SDI pin. The host terminates the write NOP Instruction Byte and another “dummy” Data Byte to SDI pin. operation by pulling the CS pin from LOW-to-HIGH. Instruction is The SPI host receives the Instruction Byte (instruction code + executed on the rising edge of CS (see Figure 27). register address) and requested Data Byte from SDO pin on the rising edge of SCK during third and fourth bytes, respectively. The host terminates the read by pulling the CS pin from LOW-to-HIGH (see Figure 28). FN7873 Rev 1.00 Page 15 of 20 September 11, 2015

ISL23425 Applications Information The first part starts by HIGH-to-LOW transition on CS line, followed by N two bytes read instruction on SDI line with reversed Communicating with ISL23425 chain access sequence: the instruction byte + dummy data byte for the last DCP in chain is going first, followed by LOW-to-HIGH Communication with ISL23425 proceeds using SPI interface transition on CS line. The read instructions are executed during through the ACR (address 10000b), WR0 (addresses 00000b) the second part of read sequence. It also starts by HIGH-to-LOW and WR1 (addresses 00001b) registers. transition on CS line, followed by N number of two bytes NOP The wiper of the potentiometer is controlled by the WRi register. instructions on SDI line and LOW-to-HIGH transition of CS. The Writes and reads can be made directly to these registers to data is read on every even byte during the second part of the control and monitor the wiper position. read sequence while every odd byte contains code 111b followed by address from which the data is being read. Daisy Chain Configuration Wiper Transition When an application needs more than one ISL23425, it can communicate with all of them without additional CS lines by When stepping up through each tap in voltage divider mode, daisy chaining the DCPs as shown in Figure 29. In Daisy Chain some tap transition points can result in noticeable voltage configuration, the SDO pin of the previous chip is connected to transients, or overshoot/undershoot, resulting from the sudden the SDI pin of the following chip, and each CS and SCK pins are transition from a very low impedance “make” to a much higher connected to the corresponding microcontroller pins in parallel, impedance “break” within a short period of time (<1µs). There like regular SPI interface implementation. The Daisy Chain are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., configuration can also be used for simultaneous setting of EFh to FFh, which have higher transient glitch. Note that all multiple DCPs. Note, the number of daisy chained DCPs is switching transients will settle well within the settling time as limited only by the driving capabilities of the SCK and CS pins of stated in the datasheet. A small capacitor can be added the microcontroller; for larger number of SPI devices buffering of externally to reduce the amplitude of these voltage transients, SCK and CS lines is required. but that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a Daisy Chain Write Operation good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. The write operation starts by HIGH-to-LOW transition on CS line, followed by N number of two bytes write instructions on SDI line V Requirements LOGIC with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown in Figure30, It is recommended to keep VLOGIC powered all the time during where N is a number of DCPs in chain. The serial data is going normal operation. In a case where turning VLOGIC OFF is through DCPs from DCP0 to DCP(N-1) as follow: DCP0 --> DCP1--> necessary, it is recommended to ground the VLOGIC pin of the DCP2 --> ... --> DCP(N-1). The write instruction is executed on the ISL23425. Grounding the VLOGIC pin or both VLOGIC and VCC does rising edge of CS for all N DCPs simultaneously. not affect other devices on the same bus. It is good practice to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to Daisy Chain Read Operation the VLOGIC pin. The read operation consists of two parts: first, send the read V Requirements and Placement CC instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP instructions (N two It is recommended to put a 1µF capacitor in parallel with 0.1µF bytes operation) as shown in Figures 31 and 32. decoupling capacitor close to the VCC pin. N DCP IN A CHAIN CS SCK MOSI DCP0 DCP1 DCP2 DCP(N-1) MISO CS CS CS CS SCK SCK SCK SCK µC SDI SDO SDI SDO SDI SDO SDI SDO FIGURE 29. DAISY CHAIN CONFIGURATION FN7873 Rev 1.00 Page 16 of 20 September 11, 2015

ISL23425 CS SCK 16 CLKLS 16 CLKS 16 CLKS SDI WR D C P2 WR D C P1 WR D C P0 SDO 0 WR D C P2 WR D C P1 SDO 1 WR D C P2 SDO 2 FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 31. TWO BYTE READ INSTRUCTION CS SCK 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS SDI RD DCP2 RD DCP1 RD DCP0 NOP NOP NOP SDO DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP FN7873 Rev 1.00 Page 17 of 20 September 11, 2015

ISL23425 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE September 11, 2015 FN7873.1 - Updated ordering Information Table on page3. - Added About Intersil Verbiage. - Updated POD L16.2.6X1.8A to latest revision changes are as follow: Changed in Note 5 0.30 to 0.25 June 20, 2011 FN7873.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2011-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7873 Rev 1.00 Page 18 of 20 September 11, 2015

ISL23425 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 14 8 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 CBA 1 7 0.65 B 0.09-0.20 TOP VIEW END VIEW 1.00 REF H 0.05 C 0.90 +0.15/-0.10 1.20 MAX SEATING GAUGE PLANE PLANE 0.25 0.25 +0.05/-0.06 5 0.10C 0.10 CBA 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN FN7873 Rev 1.00 Page 19 of 20 September 11, 2015

ISL23425 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) L16.2.6x1.8A D A B 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA N E SYMBOL MIN NOMINAL MAX NOTES 2X 0.10 C A 0.45 0.50 0.55 - 1 2 A1 - - 0.05 - 2X 0.10 C A3 0.127 REF - TOP VIEW b 0.15 0.20 0.25 5 D 2.55 2.60 2.65 - 0.10 C C E 1.75 1.80 1.85 - A 0.05C e 0.40 BSC - SEATING PLANE A1 K 0.15 - - - SIDE VIEW L 0.35 0.40 0.45 - L1 0.45 0.50 0.55 - N 16 2 e PIN #1 ID Nd 4 3 K 1 2 Ne 4 3 L1 NX L  0 - 12 4 NX b 5 Rev. 6 1/14 (DATUM B) 16X NOTES: (DATUM A) 0.10 M CAB 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 0.05 M C 2. N is the number of terminals. BOTTOM VIEW 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured CL between 0.15mm and 0.25mm from the terminal tip. (A1) 6. The configuration of the pin #1 identifier is optional, but must be NX (b) L located within the zone indicated. The pin #1 identifier may be 5 either a mold or mark feature. e 7. Maximum package warpage is 0.05mm. SECTION "C-C" 8. Maximum allowable burrs is 0.076mm in all directions. C C TERMINAL TIP 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.20 0.50 0.40 10 LAND PATTERN FN7873 Rev 1.00 Page 20 of 20 September 11, 2015