DATASHEET ISL23418 FN7901 Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) Rev 1.00 September 24, 2015 The ISL23418 is a volatile, low voltage, low noise, low power, Features SPI™ bus, 128 taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches, and control • 128 Resistor Taps logic on a monolithic CMOS integrated circuit. • SPI Serial Interface - No Additional Level Translator for Low Bus Supply The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The - Daisy Chaining of Multiple DCP position of the wiper is controlled by the user through the SPI • Wiper Resistance: 70 Typical @ VCC = 3.3V bus interface. The potentiometer has an associated volatile Wiper Register (WR) that can be directly written to and read by • Shutdown Mode: Forces DCP into End-to-end Open Circuit; the user. The contents of the WR controls the position of the RW Shorted to RL Internally wiper. When powered on, the ISL23418 wiper always • Power-on Preset to Mid-scale (64-tap Position) commences at mid-scale (64-tap position). • Shutdown and Standby Current <2.8µA Max The low voltage, low power consumption, and small package • Power Supply size of the ISL23418 make it an ideal choice for use in battery operated equipment. The ISL23418 has a VLOGIC pin allowing - VCC = 1.7V to 5.5V Analog Power Supply down to 1.2V bus operation, independent from the VCC value. - VLOGIC = 1.2V to 5.5V SPI Bus/Logic Power Supply This allows for low logic levels to be connected directly to the • DCP Terminal Voltage from 0V to VCC ISL23418 without passing through a voltage level shifter. • 10k 50kor 100k Total Resistance The DCP can be used as a three-terminal potentiometer or as a • Extended Industrial Temperature Range: -40°C to +125°C two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal • 10 Ld MSOP or 10 Ld µTQFN Packages processing. • Pb-free (RoHS compliant) Related Literature Applications • See ISL23415, “Single, Low Voltage Digitally Controlled • Power Supply Margining Potentiometer (XDCP™)” • RF Power Amplifier Bias Compensation • LCD Bias Compensation • Gain Adjustment in Battery Powered Instruments • Portable Medical Equipment Calibration 10000 VREF 8000 Ω) E ( 6000 C RH1 N STA - VREF_M SI 4000 RW1 RE ISL23418 + 2000 ISL28114 RL1 0 0 25 50 75 100 125 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. VREF ADJUSTMENT POSITION, 10k FN7901 Rev 1.00 Page 1 of 20 September 24, 2015

ISL23418 Block Diagram VLOGIC VCC SCK RH POWER-UP SDI INTERFACE, SDO I/O BLOCK SLHEIFVTEELR COANNTDROL VOLWARTILE CS STATUS REGISTER LOGIC AND WIPER CONTROL CIRCUITRY RL RW GND Pin Configurations Pin Description ISL23418 (10 LD MSOP) MSOP µTQFN SYMBOL DESCRIPTION TOP VIEW VLOGIC 1 O 10 GND 1 10 VLOGIC S5P.5IV bus/logic supply; range 1.2V to SCK 2 9 VCC 2 1 SCK Logic pin: serial bus clock input SDO 3 8 RH 3 2 SDO Logic pin: serial bus data output SDI 4 7 RW (configurable) CS 5 6 RL 4 3 SDI Logic pin: serial bus data input 5 4 CS Logic pin: active low Chip Select ISL23418 (10 LD µTQFN) 6 5 RL DCP “low” terminal TOP VIEW 7 6 RW DCP wiper terminal C GI 8 7 RH DCP “high” terminal O L V 9 8 VCC Analog power supply; range 1.7V to O 10 5.5V SCK 1 9 GND 10 9 GND Ground pin SDO 2 8 VCC SDI 3 7 RH CS 4 6 RW 5 L R FN7901 Rev 1.00 Page 2 of 20 September 24, 2015

ISL23418 Ordering Information RESISTANCE PART NUMBER PART OPTION TEMP. RANGE PACKAGE PKG. (Note 5) MARKING (kΩ) (°C) (RoHS Compliant DWG. # ISL23418TFUZ (Notes 1, 3) 3418T 100 -40 to +125 10 Ld MSOP M10.118 ISL23418UFUZ (Notes 1, 3) 3418U 50 -40 to +125 10 Ld MSOP M10.118 ISL23418WFUZ (Notes 1, 3) 3418W 10 -40 to +125 10 Ld MSOP M10.118 ISL23418TFRUZ-T7A (Notes 2, 4) HL 100 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL23418TFRUZ-TK (Notes 2, 4) HL 100 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL23418UFRUZ-T7A (Notes 2, 4) HK 50 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available, recommended replacement: ISL23418TFRUZ-T7A) ISL23418UFRUZ-TK (Notes 2, 4) HK 50 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available, recommended replacement: ISL23418TFRUZ-TK) ISL23418WFRUZ-T7A (Notes 2, 4) HJ 10 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available, recommended replacement: ISL23418TFRUZ-T7A) ISL23418WFRUZ-TK (Notes 2, 4) HJ 10 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available, recommended replacement: ISL23418TFRUZ-TK) NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23418. For more information on MSL please see Tech Brief TB363. FN7901 Rev 1.00 Page 3 of 20 September 24, 2015

ISL23418 Absolute Maximum Ratings Thermal Information Supply Voltage Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 10 Ld MSOP Package (Notes 6, 7). . . . . . . 170 70 VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 10 Ld µTQFN Package (Notes 6, 7) . . . . . . 145 90 Voltage on any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Voltage on any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Wiper Current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV CDM Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . . . . . . . . 1kV Recommended Operating Conditions Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . .200V Latch Up Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7V to 5.5V VLOGIC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. For JC, the “case temp” location is taken at the package top center. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°Cto+125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS RTOTAL RH to RL Resistance W option 10 kΩ U option 50 kΩ T option 100 kΩ RH to RL Resistance Tolerance -20 ±2 +20 % End-to-End Temperature Coefficient W option 175 ppm/°C U option 85 ppm/°C T option 70 ppm/°C VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0 VCC V RW Wiper Resistance RH - floating, VRL = 0V, force IW current 70 200 Ω to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V 580 Ω CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page8. 32/32/32 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Feed Thru Digital Feedthrough from Bus to Wiper Wiper at middle point -65 dB PSRR Power Supply Reject Ratio Wiper output change if VCC change -75 dB ±10%; wiper at middle point VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity, Guaranteed W, U, T option -0.5 ±0.15 +0.5 LSB (Note 13) Monotonic (Note 9) FN7901 Rev 1.00 Page 4 of 20 September 24, 2015

ISL23418 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°Cto+125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS DNL Differential Non-linearity, Guaranteed W, U, T option -0.5 ±0.15 +0.5 LSB (Note 12) Monotonic (Note 9) FSerror Full-scale Error W option -2.5 -1.5 0 LSB (Note 11) (Note 9) U, T option -1.0 -0.7 0 LSB (Note 9) ZSerror Zero-scale Error W option 0 -1.5 2.5 LSB (Note 10) (Note 9) U, T option 0 -0.7 1.0 LSB (Note 9) TCV Ratiometric Temperature Coefficient W option, Wiper Register set to 40 hex 8 ppm/°C (Note 14) U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C tLS_Settling Large Signal Wiper Settling Time From code 0 to 7F hex 300 ns fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -1.0 ±0.5 +1.0 MI (Note 18) Monotonic (Note 15) W option; VCC = 1.7V ±3.0 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 15) U, T option; VCC = 1.7V ±1.0 MI (Note 15) RDNL Differential Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 17) Monotonic (Note 15) W option; VCC = 1.7V ±0.4 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 15) U, T option; VCC = 1.7V ±0.4 MI (Note 15) Roffset Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 0 1.8 3.0 MI (Note 16) (Note 15) W option; VCC = 1.7V 3.0 MI (Note 15) U, T option; VCC = 2.7V to 5.5V 0 0.3 1 MI (Note 15) U, T option; VCC = 1.7V 0.5 MI (Note 15) FN7901 Rev 1.00 Page 5 of 20 September 24, 2015

ISL23418 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°Cto+125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS TCR Resistance Temperature Coefficient W option; Wiper register set between 220 ppm/°C (Note 19) 32 hex and 7F hex U option; Wiper register set between 100 ppm/°C 32 hex and 7F hex T option; Wiper register set between 75 ppm/°C 32 hex and 7F hex Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°Cto+125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V, 1.5 mA fSCK = 5MHz (for SPI active read and write) VLOGIC = 1.2V, VCC = 1.7V, 30 µA fSCK = 1MHz (for SPI active read and write) ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 100 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V, 1.3 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.4 µA SPI interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, 1.5 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1 µA SPI interface in standby ILOGIC SHDN VLOGIC Shutdown Current VLOGIC = VCC = 5.5V, 1.3 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.4 µA SPI interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, 1.5 µA SPI interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1 µA SPI interface in standby ILkgDig Leakage Current, at Pins CS, SDO, SDI, Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA SCK tDCP Wiper Response Time W option; CS rising edge to wiper new position, 0.4 µs from 10% to 90% of final value. U option; CS rising edge to wiper new position, 1.5 µs from 10% to 90% of final value. T option; CS rising edge to wiper new position, 3.5 µs from 10% to 90% of final value. tShdnRec DCP Recall Time from Shutdown Mode CS rising edge to wiper recalled position and 1.5 µs RH connection VCC, VLOGIC VCC, VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms Ramp FN7901 Rev 1.00 Page 6 of 20 September 24, 2015

ISL23418 Serial Interface Specification For SCK, SDI, SDO, CS, unless otherwise noted. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note 8) (Note 20) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC+ 0.3 V Hysteresis SDI and SCK Input Buffer Hysteresis VLOGIC > 2V 0.05 x VLOGIC V VLOGIC < 2V 0.1 x VLOGIC VOL SDO Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V Rpu SDO Pull-up Resistor Off-chip Maximum is determined by tRO and tFO with 1.5 k maximum bus load Cb = 30pF, fSCK=5MHz Cpin SCK, SDO, SDI, CS Pin Capacitance 10 pF fSCK SCK Frequency VLOGIC = 1.7V to 5.5V 5 MHz VLOGIC = 1.2V to 1.6V 1 MHz tCYC SPI Clock Cycle Time VLOGIC ≥ 1.7V 200 ns tWH SPI Clock High Time VLOGIC ≥ 1.7V 100 ns tWL SPI Clock Low Time VLOGIC ≥ 1.7V 100 ns tLEAD Lead Time VLOGIC ≥ 1.7V 250 ns tLAG Lag Time VLOGIC ≥ 1.7V 250 ns tSU SDI, SCK and CS Input Setup Time VLOGIC ≥ 1.7V 50 ns tH SDI, SCK and CS Input Hold Time VLOGIC ≥ 1.7V 50 ns tRI SDI, SCK and CS Input Rise Time VLOGIC ≥ 1.7V 10 ns tFI SDI, SCK and CS Input Fall Time VLOGIC ≥ 1.7V 10 20 ns tDIS SDO Output Disable Time VLOGIC ≥ 1.7V 0 100 ns tSO SDO Output Setup Time VLOGIC ≥ 1.7V 50 ns tV SDO Output Valid Time VLOGIC ≥ 1.7V 150 ns tHO SDO Output Hold Time VLOGIC ≥ 1.7V 0 ns tRO SDO Output Rise Time Rpu = 1.5k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 1.5k, Cbus = 30pF 60 ns tCS CS Deselect Time 2 µs NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex, respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)127 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 14. MaxVRWi–MinVRWi 106 for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage TC = ------------------------------------------------------------------------------------------------------ V VRWi+25°C +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 15. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex, respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 127. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127. 6 19. MaxRi–MinRi 10 for i = 16 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the TC = ----------------------------------------------------------------------------- R Ri+25°C +165°C minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN7901 Rev 1.00 Page 7 of 20 September 24, 2015

ISL23418 DCP Macro Model RTOTAL RH RL CL CH CW 32pF 32pF 32pF RW Timing Diagrams Input Timing tCS CS tLEAD tCYC tLAG SCK ... tSU tH tWL tWH tFI tRI SDI MSB ... LSB SDO Output Timing CS SCK ... tSO tHO tDIS SDO MSB ... LSB tV SDI ADDR XDCP™ Timing (for All Load Instructions) CS tDCP SCK ... SDI MSB ... LSB VW SDO *When CS is HIGH SDO at Z or Hi-Z state FN7901 Rev 1.00 Page 8 of 20 September 24, 2015

ISL23418 Typical Performance Curves 0.4 0.30 0.2 0.15 )B )B S S L( LN 0 L( LN 0 D D -0.2 -0.15 -0.4 -0.30 0 25 50 75 100 125 0 25 50 75 100 125 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V 0.4 0.30 0.2 0.15 )B )B S S L 0 L 0 ( L ( L N N I I -0.2 -0.15 -0.4 -0.30 0 25 50 75 100 125 0 25 50 75 100 125 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V 0.4 0.30 0.2 0.15 )IM )IM ( L 0 (L 0 N N D D R R -0.2 -0.15 -0.4 -0.30 0 25 50 75 100 125 0 25 50 75 100 125 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V FN7901 Rev 1.00 Page 9 of 20 September 24, 2015

ISL23418 Typical Performance Curves (Continued) 0.6 0.30 0.4 0.15 0.2 )IM )IM (L 0 ( L 0 N N IR IR -0.2 -0.15 -0.4 -0.6 -0.30 0 25 50 75 100 125 0 25 50 75 100 125 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V 70 60 +125°C +125°C 60 50 +25°C ) ) ( E 50 +25°C ( E 40 C C N N A 40 A T T S S 30 IS IS E 30 E R R RE RE 20 -40°C P 20 P IW IW -40°C 10 10 0 0 0 25 50 75 100 125 0 25 50 75 100 125 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V 300 70 250 60 50 200 )C )C °/m °/m 40 p 150 p p p ( v ( v 30 C C T 100 T 20 50 10 0 0 7.5 32.5 57.5 82.5 107.5 7.5 32.5 57.5 82.5 107.5 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION FN7901 Rev 1.00 Page 10 of 20 September 24, 2015

ISL23418 Typical Performance Curves (Continued) 600 200 500 150 400 )C )C °/m °/m p 300 p 100 p p (r C ( Cr T 200 T 50 100 0 0 7.5 32.5 57.5 82.5 107.5 7.5 32.5 57.5 82.5 107.5 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION 35 120 30 90 25 )C°/m 20 )C°/m pp(v C 15 pp( Cr 60 T T 10 30 5 0 0 7.5 32.5 57.5 82.5 107.5 7.5 32.5 57.5 82.5 107.5 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION FIGURE 18. 100k TCr vs TAP POSITION SCK CLOCK RW PIN CH1: 1V/DIV, 1µs/DIV 20mV/DIV CH2: 10mV/DIV, 1µs/DIV 5µs/DIV FIGURE 19. WIPER DIGITAL FEEDTHROUGH FIGURE 20. WIPER TRANSITION GLITCH FN7901 Rev 1.00 Page 11 of 20 September 24, 2015

ISL23418 Typical Performance Curves (Continued) 1V/DIV 1V/DIV 1µs/DIV 0.1s/DIV VRW CS RISING EDGE FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: 0.5V/DIV, 0.2µs/DIV RH PIN 1.2 CH2: 0.2V/DIV, 0.2µs/DIV RW PIN )A 1.0 µ ( C C I T 0.8 VCC = 5.5V, VLOGIC = 5.5V N E R R 0.6 U C Y BD 0.4 N AT VCC = 1.7V, VLOGIC = 1.2V S 0.2 RTOTAL = 10k 0 -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP -40 -15 10 35 60 85 110 TEMPERATURE (°C) FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE FN7901 Rev 1.00 Page 12 of 20 September 24, 2015

ISL23418 Functional Pin Descriptions Voltage at any DCP pins, RH, RL, or RW should not exceed VCC level at any conditions during power-up and normal operation. Potentiometers Pins The VLOGIC pin must be connected to the SPI bus supply, which allows reliable communication with a wide range of RH AND RL microcontrollers, independently of the VCC level. This is extremely important in systems in which the digital supply has The high (RH) and low (RL) terminals of the ISL23418 are lower levels than the analog supply. equivalent to the fixed terminals of a mechanical potentiometer. The RH and RL are referenced to the relative position of the wiper DCP Description and not to the voltage potential on the terminals. With the WR Each DCP is implemented with a combination of resistor register set to 127 decimal, the wiper is closest to RH, and with elements and CMOS switches. The physical ends of DCP are the WR register set to 0, the wiper is closest to RL. equivalent to the fixed terminals of a mechanical potentiometer RW (RH and RL pins). The RW pin of the DCP is connected to RW is the wiper terminal, and it is equivalent to the moveable intermediate nodes and is equivalent to the wiper terminal of a terminal of a mechanical potentiometer. The position of the mechanical potentiometer. The position of the wiper terminal wiper within the array is determined by the WR register. within the DCP is controlled by the 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0] =00h), Bus Interface Pins its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[7:0] = 7Fh), its SERIAL CLOCK (SCK) wiper terminal (RW) is closest to its “High” terminal (RH). As the The SCK input is the serial clock of the SPI serial interface. value of WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position SERIAL DATA INPUT (SDI) closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while SDI is a serial data input pin for the SPI interface. SDI receives the resistance between RH and RW decreases monotonically. operation code, wiper address and data from the SPI remote host device. The data bits are shifted in at the rising edge of the While the ISL23418 is being powered up, the WR is reset to 40h serial clock, SCK, while CS input is low. (64 decimal), which locates RW to the mid value between RL and RH. SERIAL DATA OUTPUT (SDO) WR can be read or written to directly using the SPI serial SDO is a serial data output pin. During a read cycle, the data bits interface as described in the following sections. are shifted out on the falling edge of the serial clock SCK and are available to the master on the following rising edge of SCK. Memory Description The output type is configured through ACR[1] bit for Push-Pull or The ISL23418 contains two volatile 8-bit registers: the Wiper Open Drain operation. Default setting for this pin is Push-Pull. An Register (WR) and the Access Control Register (ACR). A memory external pull-up resistor is required for Open Drain output map of ISL23418 is shown in Table 1. WR, at address 0, contains operation. When CS is HIGH, the SDO pin is in tri-state (Z) or the current wiper position of the DCP. ACR, at address 10h, high-tri-state (Hi-Z), depending on the selected configuration. contains information and control bits as described in Table 2. CHIP SELECT (CS) TABLE 1. MEMORY MAP CS LOW enables the ISL23418, placing it in the active power ADDRESS DEFAULT SETTING mode. A HIGH to LOW transition on CS is required prior to the (hex) VOLATILE (hex) start of any operation after power-up. When CS is HIGH, the 10 ACR 40 ISL23418 is deselected, the SDO pin is at high impedance, and the device is in standby state. 0 WR 80 VLOGIC TABLE 2. ACCESS CONTROL REGISTER (ACR) VLOGIC is an input pin that supplies an internal level translator BIT # 7 6 5 4 3 2 1 0 for serial bus operation from 1.2V to 5.5V. NAME 0 SHDN 0 0 0 0 SDO 0 Principles of Operation Shutdown Function The ISL23418 is an integrated circuit incorporating one DCP with The SHDN bit (ACR[6]) disables or enables shutdown mode for all its associated registers and an SPI serial interface providing DCP channels simultaneously. When this bit is 0, DCP is forced to direct communication between a host and the potentiometer. end-to-end open circuit, and RW is connected to RL through a The resistor array is composed of individual resistors connected 2kΩ serial resistor, as shown in Figure 25. Default value of the in series. At either end of the array and between each resistor is SHDN bit is 1. an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. FN7901 Rev 1.00 Page 13 of 20 September 24, 2015

ISL23418 SPI Serial Interface RH The ISL23418 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output, with data clocked in on the rising edge of SCK and clocked out on the falling edge of SCK. CS must be LOW during communication with RW the ISL23418. The SCK and CS lines are controlled by the host or master. The ISL23418 operates only as a slave device. All 2kΩ communication over the SPI interface is conducted by sending the MSB of each byte of data first. RL Protocol Conventions FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE The SPI protocol contains an Instruction Byte followed by one or In shutdown mode, the RW terminal is shorted to the RL terminal more Data Bytes. A valid Instruction Byte contains instruction as with around 2kΩ resistance, as shown in Figure 25. When the device the three MSBs, with the following five register address bits enters shutdown, all current DCP WR settings are maintained. When (Table3). The next byte sent to the ISL23418 is the Data Byte. the device exits shutdown, the wipers return to the previous WR settings after a short settling time (Figure26). TABLE 3. INSTRUCTION BYTE FORMAT BIT # 7 6 5 4 3 2 1 0 I2 I1 I0 R4 R3 R2 R1 R0 V) (W Table 4 contains a valid instruction set for ISL23418. If the R POWER-UP MID SCALE = 40H [R4:R0] bits are zero, then the read or write is to the WR register. If V E, the [R4:R0] bits are 10000, then the operation is to the ACR. G A USER PROGRAMMED AFTER SHDN LT Write Operation O V R SHDN ACTIVATED SHDN RELEASED A write operation to the ISL23418 is a two or more bytes E WIPER RESTORE TO P operation. It first requires CS to transition from HIGH to LOW. WI ORIGINAL POSITION Then the host sends a valid Instruction Byte to the SDI pin, SHDN MODE followed by one or more Data Bytes. The host terminates the 0 TIME (s) write operation by pulling the CS pin from LOW to HIGH. The instruction is executed on the rising edge of CS (Figure 27). FIGURE 26. SHUTDOWN MODE WIPER RESPONSE Read Operation In shutdown mode, if there is a glitch in the power supply that A read operation to the ISL23418 is a four-byte operation. First, causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the the CS transitions from HIGH to LOW. Then the host sends a valid wipers are RESET to their mid position. This is done to avoid an Instruction Byte to the SDI pin, followed by a “dummy” Data Byte, undefined state at the wiper outputs. an NOP Instruction Byte, and another “dummy” Data Byte. The SPI host receives the Instruction Byte (instruction code + register address) and the requested Data Byte from the SDO pin on the rising edge of SCK during the third and fourth bytes, respectively. The host terminates the read by pulling the CS pin from LOW to HIGH (Figure 28). TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRTE 1 0 0 R4 R3 R2 R1 R0 WR or ACR READ 1 1 0 R4 R3 R2 R1 R0 WR or ACR WRTE where “X” means “do not care.” FN7901 Rev 1.00 Page 14 of 20 September 24, 2015

ISL23418 CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 27. TWO-BYTE WRITE SEQUENCE CS 1 8 16 24 32 SCK RD ADDR NOP SDI RD ADDR READ DATA SDO FIGURE 28. FOUR-BYTE READ SEQUENCE FN7901 Rev 1.00 Page 15 of 20 September 24, 2015

ISL23418 Applications Information First there is a HIGH-to-LOW transition on the CS line, followed by N two-byte read instructions on the SDI line, with reversed chain Communicating with ISL23418 access sequence. The instruction byte + dummy data byte for the last DCP in the chain goes first, followed by a LOW-to-HIGH Communication with ISL23418 is accomplished by using the SPI transition on the CS line. The read instructions are executed interface through the ACR (address 10000b) and WR (address during the second part of the read sequence. It also starts by a 00000b) registers. HIGH-to-LOW transition on the CS line, followed by N number of two-byte NOP instructions on the SDI line and a LOW-to-HIGH The wiper of the potentiometer is controlled by the WR register. transition of CS. The data is read on every even byte during the Writes and reads can be made directly to these registers to second part of the read sequence, while every odd byte contains control and monitor the wiper position. code 111b followed by the address from which the data is being Daisy Chain Configuration read. When an application needs more than one ISL23418, it can Wiper Transition communicate with all of them without additional CS lines by daisy chaining the DCPs, as shown in Figure 29. In daisy chain When stepping up through each tap in voltage divider mode, configuration, the SDO pin of the previous chip is connected to some tap transition points can exhibit noticeable voltage the SDI pin of the following chip, and each CS and SCK pin is transients or overshoot/undershoot, which results from the connected to the corresponding microcontroller pin in parallel, sudden transition from a very low impedance “make” to a much like regular SPI interface implementation. The daisy chain higher impedance “break” within a short period of time (<1µs). configuration can also be used for simultaneous setting of Several code transitions, such as 0Fh to 10h, 1Fh to 20h,..., and multiple DCPs. Note that the number of daisy chained DCPs is EFh to 7Fh, have higher transient glitch. Note that all switching limited only by the driving capabilities of the SCK and CS pins of transients settle well within the settling time as stated in the the microcontroller. For a larger number of SPI devices, buffering datasheet. A small capacitor can be added externally to reduce of the SCK and CS lines is required. the amplitude of these voltage transients, but this also reduces the useful bandwidth of the circuit, which may not be a good Daisy Chain Write Operation solution for some applications. Using fast amplifiers in a signal chain for fast recovery may be a good idea in these cases. The write operation starts with a HIGH to LOW transition on the CS line, followed by N number of two-byte write instructions on V Requirements LOGIC the SDI line, with reversed chain access sequence. The instruction byte + data byte for the last DCP in the chain go first, Keeping VLOGIC powered all the time during normal operation is as shown in Figure30, where N is the number of DCPs in the recommended. In cases in which turning VLOGIC OFF is chain. Serial data is going through the DCPs from DCP0 to necessary, grounding the VLOGIC pin is recommended. Grounding DCP(N-1) as follows: DCP0 --> DCP1--> DCP2 --> ... --> DCP(N-1). the VLOGIC pin or both VLOGIC and VCC does not affect other The write instruction is executed on the rising edge of CS for all N devices on the same bus. It is good practice to put a 1µF capacitor DCPs simultaneously. in parallel with a 0.1µF decoupling capacitor close to the VLOGIC pin. Daisy Chain Read Operation VCC Requirements and Placement The read operation consists of two parts. First, the read Putting a 1µF capacitor in parallel with a 0.1µF decoupling capacitor instructions (N two-byte operations) are sent with a valid address. close to the VCC pin is recommended. Second, the requested data is read while sending NOP instructions (N two-byte operations), as shown in Figures 31 and 32. N DCP IN A CHAIN CS SCK MOSI DCP0 DCP1 DCP2 DCP(N-1) MISO CS CS CS CS SCK SCK SCK SCK µC SDI SDO SDI SDO SDI SDO SDI SDO FIGURE 29. DAISY CHAIN CONFIGURATION FN7901 Rev 1.00 Page 16 of 20 September 24, 2015

ISL23418 CS SCK 16 CLKLS 16 CLKS 16 CLKS SDI WR D C P2 WR D C P1 WR D C P0 SDO 0 WR D C P2 WR D C P1 SDO 1 WR D C P2 SDO 2 FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 31. TWO-BYTE READ INSTRUCTION CS SCK 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS SDI RD DCP2 RD DCP1 RD DCP0 NOP NOP NOP SDO DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP FN7901 Rev 1.00 Page 17 of 20 September 24, 2015

ISL23418 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE September 24, 2015 FN7901.1 Updated the Ordering Information table on page3. Replaced Products section with About Intersil section. Updated Package Outline Drawing M10.118 to the latest revision. Changes are as follows: -Updated to new POD template. Added land pattern August 3, 2011 FN7901.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2011-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7901 Rev 1.00 Page 18 of 20 September 24, 2015

ISL23418 Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN7901 Rev 1.00 Page 19 of 20 September 24, 2015

ISL23418 Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 8. PIN 1 INDEX AREA 2.10 A PIN #1 ID B 0.05 MIN. 1 8. 1 4 0.10 MIN. 4X 0.20 MIN. 0 6 1. 10 5 0.80 10X 0.40 0.10 2X 9 6 6X 0.50 10 X 0.20 4 TOP VIEW 0.10M C AB BOTTOM VIEW M C SEE DETAIL "X" (0.05 MIN) (10 X 0.20) 1 PACKAGE MAX. 0.55 OUTLINE 0.10 C (10X 0.60) C (0.10 MIN.) SEATING PLANE 0.08 C (2.00) SIDE VIEW (0.80) (1.30) 0 . 125 REF C (6X 0.50 ) (2.50) 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Maximum package warpage is 0.05mm. 6. Maximum allowable burrs is 0.076mm in all directions. 7. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. 8. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7901 Rev 1.00 Page 20 of 20 September 24, 2015