DATASHEET ISL23328 FN7902 Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™) Rev 1.00 September 29, 2015 The ISL23328 is a volatile, low voltage, low noise, low power, Features 128-Tap, dual digitally controlled potentiometer (DCP) with an I2C Bus™ interface. It integrates two DCP cores, wiper switches • Two potentiometers per package and control logic on a monolithic CMOS integrated circuit. • 128 resistor taps Each digitally controlled potentiometer is implemented with a • 10kΩ, 50kΩ or 100kΩ total resistance combination of resistor elements and CMOS switches. The • I2C serial interface position of the wipers are controlled by the user through the I2C - No additional level translator for low bus supply bus interface. Each potentiometer has an associated volatile - Three address pins allow up to eight devices per bus Wiper Register (WRi, i = 0, 1) that can be directly written to and read by the user. The contents of the WRi controls the position • Power supply of the wiper. When powered on, the wiper of each DCP will - VCC = 1.7V to 5.5V analog power supply always commence at mid-scale (64 tap position). - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply The low voltage, low power consumption, and small package • Maximum supply current without serial bus activity of the ISL23328 make it an ideal choice for use in battery (standby) operated equipment. In addition, the ISL23328 has a VLOGIC pin allowing down to 1.2V bus operation, independent from the - 3µA @ VCC and VLOGIC = 5V VCC value. This allows for low logic levels to be connected - 1.7µA @ VCC and VLOGIC = 1.7V directly to the ISL23328 without passing through a voltage • Shutdown Mode level shifter. - Forces the DCP into an end-to-end open circuit and RWi is The DCP can be used as a three-terminal potentiometer or as a connected to RLi internally two-terminal variable resistor in a wide variety of applications - Reduces power consumption by disconnecting the DCP including control, parameter adjustments, and signal resistor from the circuit processing. • Wiper resistance: 70Ω typical @ VCC = 3.3V Applications • Power-on preset to mid-scale (64 tap position) • Power supply margining • Extended industrial temperature range: -40°C to +125°C • Trimming sensor circuits • 14 Ld TSSOP or 16 Ld UTQFN packages • Gain adjustment in battery powered instruments • Pb-free (RoHS Compliant) • RF power amplifier bias compensation 10000 VREF 8000 Ω) E ( 6000 RH1 C N TA - VREF_M SIS 4000 1 DCP RW1 E OF + R ISL23328 2000 ISL28114 RL1 0 0 32 64 96 128 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. VREF ADJUSTMENT POSITION, 10kΩ DCP FN7902 Rev 1.00 Page 1 of 20 September 29, 2015

ISL23328 Block Diagram VLOGIC VCC RH0 RH1 SCL POWER UP SDA INTERFACE, I/O LEVEL CONTROL A0 BLOCK SHIFTER AND WR0 WR1 A1 STATUS VOLATILE VOLATILE LOGIC REGISTER REGISTER A2 AND AND WIPER WIPER CONTROL CONTROL CIRCUITRY CIRCUITRY GND RW0 RL0 RW1 RL1 Pin Configurations Pin Descriptions ISL23328 (14 LD TSSOP) TSSOP UTQFN SYMBOL DESCRIPTION TOP VIEW 1 6, 15 GND Ground pin GND 1 14 VCC 2 16 VLOGIC I2C bus/logic supply. Range 1.2V to 5.5V VLOGIC 2 13 RL0 3 1 SDA Logic Pin - Serial bus data SDA 3 12 RW0 input/open drain output SCL 4 11 RH0 4 2 SCL Logic Pin - Serial bus clock input A0 5 10 RH1 5 3 A0 Logic Pin - Hardwire slave address A1 6 9 RW1 pin for I2C serial bus. Range: VLOGIC or GND A2 7 8 RL1 6 4 A1 Logic Pin - Hardwire slave address pin for I2C serial bus. ISL23328 Range: VLOGIC or GND (16 LD UTQFN) 7 5 A2 Logic Pin - Hardwire slave address TOP VIEW pin for I2C serial bus. LOGIC ND CC L0 8 8 RL1 DRaCnPg1e “: lVoLwO”G tIeCr mori nGaNlD V G V R 6 5 4 3 9 9 RW1 DCP1 wiper terminal 1 1 1 1 SDA 1 12 RW0 10 10 RH1 DCP1 “high” terminal SCL 2 11 RH0 11 11 RH0 DCP0 “high” terminal A0 3 10 RH1 12 12 RW0 DCP0 wiper terminal A1 4 9 RW1 13 13 RL0 DCP0 “low” terminal 5 6 7 8 2 D C 1 14 14 VCC Analog power supply. A GN N RL Range 1.7V to 5.5V 7 NC Not Connected FN7902 Rev 1.00 Page 2 of 20 September 29, 2015

ISL23328 Ordering Information PART NUMBER RESISTANCE OPTION TEMP RANGE PACKAGE PKG. (Note 4) PART MARKING (kΩ) (°C) (Pb-free) DWG. # ISL23328TFVZ (Note 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFVZ-T7A (Notes 1, 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFVZ-TK (Notes 1, 2) 23328 TFVZ 100 -40 to +125 14 Ld TSSOP M14.173 ISL23328UFVZ (Note 2) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 (No longer available,recommended replacement: ISL23328TFRUZ-TK) ISL23328UFVZ-T7A (Notes 1, 2) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 (No longer available,recommended replacement: ISL23328TFRUZ-TK) ISL23328UFVZ-TK (Notes 1, 2) 23328 UFVZ 50 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ (Note 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ-T7A (Notes 1, 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328WFVZ-TK (Notes 1, 2) 23328 WFVZ 10 -40 to +125 14 Ld TSSOP M14.173 ISL23328TFRUZ-T7A (Notes 1, 3) GBM 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328TFRUZ-TK (Notes 1, 3) GBM 100 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328UFRUZ-T7A (Notes 1, 3) GBL 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A (No longer available,recommended replacement: ISL23328TFRUZ-TK) ISL23328UFRUZ-TK (Notes 1, 3) GBL 50 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A (No longer available,recommended replacement: ISL23328TFRUZ-TK) ISL23328WFRUZ-T7A (Notes 1, 3) GBK 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A ISL23328WFRUZ-TK (Notes 1, 3) GBK 10 -40 to +125 16 Ld 2.6x1.8 UTQFN L16.2.6x1.8A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL23328. For more information on MSL please see techbrief TB363. FN7902 Rev 1.00 Page 3 of 20 September 29, 2015

ISL23328 Absolute Maximum Ratings Thermal Information Supply Voltage Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 14 Ld TSSOP Package (Notes 5, 6) . . . . . . 112 40 VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 16 Ld UTQFN Package (Notes 5, 6) . . . . . . 110 64 Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Voltage on Any Digital Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Wiper Current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .4.5kV Charged Device Model (Tested per JESD22-A114E) . . . . . . . . . . . . . 1kV Recommended Operating Conditions Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 300V Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . 100mA @ +125°C Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7V to 5.5V VLOGIC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA 6. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note7) (Note 19) UNITS RTOTAL RH to RL Resistance W option 10 kΩ U option 50 kΩ T option 100 kΩ RH to RL Resistance Tolerance -20 ±2 +20 % End-to-End Temperature Coefficient W option 125 ppm/°C U option 65 ppm/°C T option 45 ppm/°C VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0 VCC V RW Wiper Resistance RH - floating, VRL = 0V, force IW current 70 200 Ω to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V 580 Ω CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page9 32/32/32 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz Wiper at middle point, U option 49 nV/√Hz Wiper at middle point, T option 61 nV/√Hz Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB PSRR Power Supply Reject Ratio Wiper output change if VCC change -75 dB ±10%; wiper at middle point FN7902 Rev 1.00 Page 4 of 20 September 29, 2015

ISL23328 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note7) (Note 19) UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity, Guaranteed W option -0.5 ±0.15 +0.5 LSB (Note 12) Monotonic (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) DNL Differential Non-linearity, Guaranteed W option -0.5 ±0.15 +0.5 LSB (Note 11) Monotonic (Note 8) U, T option -0.5 ±0.15 +0.5 LSB (Note 8) FSerror Full-scale Error W option -3 -1.5 0 LSB (Note 8) U, T option -1.5 -0.9 0 LSB (Note 8) ZSerror Zero-scale Error W option 0 1.5 3 LSB (Note 9) (Note 8) U, T option 0 0.9 1.5 LSB (Note 8) Vmatch DCP to DCP Matching DCPs at same tap position, same -2 ±0.5 2 LSB (Note 21) voltage at all RH terminals, and same (Note 8) voltage at all RL terminals TCV Ratiometric Temperature Coefficient W option, Wiper Register set to 40 hex 8 ppm/°C (Notes 13) U option, Wiper Register set to 40 hex 4 ppm/°C T option, Wiper Register set to 40 hex 2.3 ppm/°C tLS_Settling Large Signal Wiper Settling Time From code 0 to 7F hex, measured from 300 ns 0 to 1 LSB settling of the wiper fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -1.0 ±0.5 +1.0 MI (Note 17) Monotonic (Note 14) W option; VCC = 1.7V 4 MI (Note 14) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 14) U, T option; VCC = 1.7V 1 MI (Note 14) RDNL Differential Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 16) Monotonic (Note 14) W option; VCC = 1.7V ±0.4 MI (Note 14) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 14) U, T option; VCC = 1.7V ±0.4 MI (Note 14) FN7902 Rev 1.00 Page 5 of 20 September 29, 2015

ISL23328 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note7) (Note 19) UNITS Roffset Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 0 1.8 3 MI (Note 15) (Note 14) W option; VCC = 1.7V 3 MI (Note 14) U, T option; VCC = 2.7V to 5.5V 0 0.3 1 MI (Note 14) U, T option; VCC = 1.7V 0.5 MI (Note 14) Rmatch DCP to DCP Matching Any two DCPs at the same tap position -2 2 LSB (Note 22) with the same terminal voltages (Note 8) TCR Resistance Temperature Coefficient W option; Wiper register set between 170 ppm/°C (Note 18) 19 hex and 7F hex U option; Wiper register set between 80 ppm/°C 19hex and 7F hex T option; Wiper register set between 50 ppm/°C 19hex and 7F hex Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note7) (Note 19) UNITS ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V, 200 µA fSCL = 400kHz (for I2C active read and write) VLOGIC = 1.2V, VCC = 1.7V, 5 µA fSCL = 400kHz (for I2C active read and write) ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 18 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V, 1 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.5 µA I2C interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, 2 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1.2 µA I2C interface in standby ILOGIC VLOGIC Shutdown Current VLOGIC = VCC = 5.5V, 1 µA SHDN I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.5 µA I2C interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, 2 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1.2 µA I2C interface in standby ILkgDig Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA SDA, SCL FN7902 Rev 1.00 Page 6 of 20 September 29, 2015

ISL23328 Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note7) (Note 19) UNITS tDCP Wiper Response Time W option; SCL rising edge of the 0.4 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. U option; SCL rising edge of the 1.5 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. T option; SCL rising edge of the 3.5 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit 1.5 µs after ACR data byte to wiper recalled position and RH connection VCC, VLOGIC VCC ,VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms Ramp (Note 20) Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note 7) (Note 19) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V Hysteresis SDA and SCL Input Buffer VLOGIC > 2V 0.05 x VLOGIC V Hysteresis VLOGIC < 2V 0.1 x VLOGIC V VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V Cpin SDA, SCL Pin Capacitance 10 pF fSCL SCL Frequency 400 kHz tsp Pulse Width Suppression Time at Any pulse narrower than the 50 ns SDA and SCL Inputs max spec is suppressed tAA SCL Falling Edge to SDA Output SCL falling edge crossing 30% 900 ns Data Valid of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window tBUF Time the Bus Must be Free Before SDA crossing 70% of VLOGIC 1300 ns the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition tLOW Clock LOW Time Measured at the 30% of 1300 ns VLOGIC crossing tHIGH Clock HIGH Time Measured at the 70% of 600 ns VLOGIC crossing tSU:STA START Condition Set-up Time SCL rising edge to SDA falling 600 ns edge; both crossing 70% of VLOGIC FN7902 Rev 1.00 Page 7 of 20 September 29, 2015

ISL23328 Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note 7) (Note 19) UNITS tHD:STA START Condition Hold Time From SDA falling edge 600 ns crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 100 ns 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC tHD:DAT Input Data Hold Time From SCL falling edge crossing 0 ns 70% of VLOGIC to SDA entering the 30% to 70% of VLOGIC window tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 600 ns 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC tHD:STO STOP Condition Hold Time for Read From SDA rising edge to SCL 1300 ns or Write falling edge; both crossing 70% of VLOGIC tDH Output Data Hold Time From SCL falling edge crossing 0 ns 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL=3mA,VLOGIC > 2V. IOL=0.5mA, VLOGIC < 2V tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF tSU:A A2, A1, A0 Setup Time Before START condition 600 ns tHD:A A2, A1, A0 Hold Time After STOP condition 600 ns NOTES: 7. Typical values are for TA = +25°C and 3.3V supply voltages. 8. LSB = [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZS error = V(RW)0/LSB. 10. FS error = [V(RW)127 – VCC]/LSB. 11. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 12. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127 13. TC = -M-----a----x-----V------R-----W-------i------–----M-----i--n-------V------R----W--------i---------1----0----6------- For i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage V VRWi+25°C +165°C and Min( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 16. RDNL = (RWi – RWi-1)/MI -1, for i = 8 to 127. 17. RINL = [RWi – (MI • i) – RW0]/MI, for i = 8 to 127. 18. MaxRi–MinRi 106 for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min() is the TC = ---------------------------------------------------------------------------- R Ri+25°C +165°C minimum value of the resistance over the temperature range. 19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 20. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible, it is recommended to ramp-up the VLOGIC first followed by the VCC. 21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. 22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1. FN7902 Rev 1.00 Page 8 of 20 September 29, 2015

ISL23328 DCP Macro Model RTOTAL RH RL CL CH CW 32pF 32pF 32pF RW Timing Diagrams SDA vs SCL Timing tF tHIGH tLOW tR tsp SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) A0, A1, and A2 Pin Timing START STOP SCL CLK 1 SDA tSU:A tHD:A A0, A1, A2 FN7902 Rev 1.00 Page 9 of 20 September 29, 2015

ISL23328 Typical Performance Curves 0.20 0.04 0.10 0.02 B) B) S S L (L 0.00 L (L 0.00 N N D D -0.10 -0.02 -0.20 -0.04 0 32 64 96 128 0 32 64 96 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. 10kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 4. 50kΩ DNL vs TAP POSITION, VCC = 3.3V, +25°C 0.30 0.12 0.15 0.09 B) B) S S L 0.00 L 0.06 L ( L ( N N I I -0.15 0.03 -0.30 0.00 0 32 64 96 128 0 32 64 96 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 6. 50kΩ INL vs TAP POSITION, VCC = 3.3V, +25°C 0.20 0.04 0.10 0.02 MI) MI) L ( 0.00 L ( 0.00 N N D D R R -0.10 -0.02 -0.20 -0.04 0 32 64 96 128 0 32 64 96 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. 10kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 8. 50kΩ RDNL vs TAP POSITION, VCC = 3.3V, +25°C FN7902 Rev 1.00 Page 10 of 20 September 29, 2015

ISL23328 Typical Performance Curves (Continued) 0.30 0.08 0.15 0.04 MI) MI) L ( 0.00 L ( 0.00 N N RI RI -0.15 -0.04 -0.30 -0.08 0 32 64 96 128 0 32 64 96 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C FIGURE 10. 50kΩ RINL vs TAP POSITION, VCC = 3.3V, +25°C 100 120 +125°C +25°C 100 +25°C +125°C 80 ) ) E ( E ( 80 C C N 60 N A A T T S S 60 SI SI E E R 40 R ER -40°C ER 40 -40°C P P WI WI 20 20 0 0 0 32 64 96 128 0 32 64 96 128 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V FIGURE 12. 50kΩ WIPER RESISTANCE vs TAP POSITION, VCC = 3.3V 200 40 150 30 C) C) m/° m/° p 100 p 20 p p v ( v ( C C T T 50 10 0 0 15 43 71 99 127 15 43 71 99 127 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 13. 10kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 14. 50kΩ TCv vs TAP POSITION, VCC = 3.3V FN7902 Rev 1.00 Page 11 of 20 September 29, 2015

ISL23328 Typical Performance Curves (Continued) 500 120 400 90 )C 300 )C °/m °/m p p 60 p p ( rC 200 r( C T T 30 100 0 0 15 43 71 99 127 15 43 71 99 127 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 15. 10kΩ TCr vs TAP POSITION FIGURE 16. 50kΩ TCr vs TAP POSITION, VCC = 3.3V 20 120 15 90 )C )C °/m °/m p 10 p 60 p p (v C ( rC T T 5 30 0 0 15 43 71 99 127 15 43 71 99 127 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, VCC = 3.3V FIGURE 18. 100kΩ TCr vs TAP POSITION, VCC = 3.3V SCL CLOCK WIPER SCL 9TH CLK OF THE DATA BYTE (ACK) RW PIN CH1: 1V/DIV, 1µs/DIV CH1: 20mV/DIV, 2µs/DIV CH2: 10mV/DIV, 1µs/DIV CH2: 2V/DIV, 2µs/DIV   FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH FN7902 Rev 1.00 Page 12 of 20 September 29, 2015

ISL23328 Typical Performance Curves (Continued) 1V/DIV 0.5V/DIV 0.2µs/DIV 20µs/DIV SCL VCC 9TH CLOCK OF THE DATA BYTE (ACK) WIPER WIPER     FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE CH1: RH TERMINAL CH2: RW TERMINAL   1.8 1.6 )A µ 1.4 ( C I TC 1.2 N E 1.0 RR VCC = 5.5V, VLOGIC = 5.5V U 0.8 C Y B 0.6 D N AT 0.4 VCC = 1.7V, VLOGIC = 1.2V S 0.2 0 0.5V/DIV, 0.2µs/DIV -40 -15 10 35 60 85 110 -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP TEMPERATURE (°C) FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions V CC Power terminal for the potentiometer section analog power Potentiometers Pins source. Can be any value needed to support voltage range of DCP pins, from 1.7V to 5.5V, independent of the VLOGIC voltage. RHI AND RLI Bus Interface Pins The high (RHi, i = 0, 1) and low (RLi, i = 0, 1) terminals of the ISL23328 are equivalent to the fixed terminals of a mechanical SERIAL DATA INPUT/OUTPUT (SDA) potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With The SDA is a bi-directional serial data input/output pin for I2C WRi set to 127 decimal, the wiper will be closest to RHi, and with interface. It receives device address, wiper address and data the WR set to 0, the wiper is closest to RLi. from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the RWI serial clock. RWi (i = 0, 1) is the wiper terminal, and it is equivalent to the SDA requires an external pull-up resistor, since it is an open drain movable terminal of a mechanical potentiometer. The position of input/output. the wiper within the array is determined by the WRi register. FN7902 Rev 1.00 Page 13 of 20 September 29, 2015

ISL23328 SERIAL CLOCK (SCL) The WRi can be read or written to directly using the I2C serial This input is the serial clock of the I2C serial interface. SCL interface as described in the following sections. requires an external pull-up resistor, since a master is an open Memory Description drain output. The ISL23328 contains three volatile 8-bit registers: Wiper DEVICE ADDRESS (A2, A1, A0) Register WR0, Wiper Register WR1, and Access Control Register The address inputs are used to set the least significant 3 bits of (ACR). Memory map of the ISL23328 is shown in Table 1. The the 7-bit I2C interface slave address. A match in the slave Wiper Register WR0 at address 0, contains current wiper position address serial data stream must match with the Address input of DCP0; The Wiper Register WR1 at address 1 contains current pins in order to initiate communication with the ISL23328. A wiper position of DCP1. The Access Control Register (ACR) at maximum of eight ISL23328 devices may occupy the I2C serial address 10h contains information and control bits described in bus (see Table 3). Table 2. V TABLE 1. MEMORY MAP LOGIC Digital power source for the logic control section. It supplies an ADDRESS VOLATILE DEFAULT SETTING internal level translator for 1.2V to 5.5V serial bus operation. Use (hex) REGISTER NAME (hex) the same supply as the I2C logic source. 10 ACR 40 Principles of Operation 1 WR1 40 0 WR0 40 The ISL23328 is an integrated circuit incorporating two DCPs with its associated registers and an I2C serial interface providing direct TABLE 2. ACCESS CONTROL REGISTER (ACR) communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected in series. At BIT # 7 6 5 4 3 2 1 0 either end of the array and between each resistor is an electronic NAME/ 0 SHDN 0 0 0 0 0 0 switch that transfers the potential at that point to the wiper. VALUE The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. Shutdown Function Voltage at any DCP pins, RHi, RLi or RWi, should not exceed VCC The SHDN bit (ACR[6]) disables or enables shutdown mode for all level at any conditions during power-up and normal operation. DCP channels simultaneously. When this bit is 0, i.e., DCP is forced to end-to-end open circuit and RW is connected to RL through a The VLOGIC pin is the terminal for the logic control digital power source. It should use the same supply as the I2C logic source 2kΩ serial resistor as shown in Figure 25. Default value of the SHDN bit is 1. which allows reliable communication with a wide range of microcontrollers and is independent from the VCC level. This is extremely important in systems where the master supply has RH lower levels than DCP analog supply. DCP Description Each DCP is implemented with a combination of resistor elements RW and CMOS switches. The physical ends of each DCP are equivalent 2kΩ to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical RL potentiometer. The position of the wiper terminal within the DCP is FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal When the device enters shutdown, all current DCP WR settings are (RWi) is closest to its “Low” terminal (RLi). When the WRi register maintained. When the device exits shutdown, the wipers will return of a DCP contains all ones (WRi[7:0] = 7Fh), its wiper terminal to the previous WR settings after a short settling time (see (RWi) is closest to its “High” terminal (RHi). As the value of the WRi Figure26). increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RLi to the In shutdown mode, if there is a glitch on the power supply which position closest to RHi. At the same time, the resistance between causes it to drop below 1.3V for more than 0.2 to 0.4µs, the RWi and RLi increases monotonically, while the resistance wipers will be RESET to their mid position. This is done to avoid between RHi and RWi decreases monotonically. an undefined state at the wiper outputs. While the ISL23328 is being powered up, both WR0 and WR1 are reset to 40h (64 decimal), which positions RWi at the center between RLi and RHi. FN7902 Rev 1.00 Page 14 of 20 September 29, 2015

ISL23328 ISL23328 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 27). A START condition is ignored V) during the power-up of the device. (W VR POWER-UP MID SCALE = 40H All I2C interface operations must be terminated by a STOP E, condition, which is a LOW to HIGH transition of SDA while SCL is G TA USER PROGRAMMED AFTER SHDN HIGH (see Figure 27). A STOP condition at the end of a read L O operation or at the end of a write operation places the device in V R SHDN ACTIVATED SHDN RELEASED its standby mode. E WIPER RESTORE TO P WI THE ORIGINAL POSITION An ACK (Acknowledge) is a software convention used to indicate SHDN MODE a successful data transfer. The transmitting device, either master 0 TIME (s) or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW FIGURE 26. SHUTDOWN MODE WIPER RESPONSE to acknowledge the reception of the eight bits of data (seeFigure28). 2 I C Serial Interface The ISL23328 responds with an ACK after recognition of a START The ISL23328 supports an I2C bidirectional bus oriented condition followed by a valid Identification Byte, and once again protocol. The protocol defines any device that sends data onto after successful receipt of an Address Byte. The ISL23328 also the bus as a transmitter and the receiving device as the receiver. responds with an ACK after receiving a Data Byte of a write The device controlling the transfer is a master and the device operation. The master must respond with an ACK after receiving being controlled is the slave. The master always initiates data a Data Byte of a read operation. transfers and provides the clock for both transmit and receive A valid Identification Byte contains 1010 as the four MSBs, and operations. Therefore, the ISL23328 operates as a slave device the following three bits are matching the logic values present at in all applications. pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1” All communication over the I2C interface is conducted by sending for a Read operation and “0” for a Write operation (see Table 3). the MSB of each byte of data first. TABLE 3. IDENTIFICATION BYTE FORMAT Protocol Conventions LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for 1 0 1 0 A2 A1 A0 R/W indicating START and STOP conditions (see Figure 27). On (MSB) (LSB) power-up of the ISL23328, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The SCL SDA START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS FN7902 Rev 1.00 Page 15 of 20 September 29, 2015

ISL23328 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S SIGNALS FROM T S THE MASTER A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 1 0 1 0A2A1A00 0 0 0 SIGNALS FROM A A A THE SLAVE C C C K K K FIGURE 29. BYTE WRITE SEQUENCE S S READ FRSMOIGAMNS ATTEHLRSE ARTT IDEBNYRTT/IWEF I WC=A I0TTHION ADBDYRTEESS ARTT IDEBNYRTT/IWEF I WC=A I1TTHION ACK ACK ACK OSPT SIGNAL AT SDA 1 0 1 0A2A1A00 0 0 0 1 0 1 0A2A1A01 A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 30. READ SEQUENCE Write Operation Read Operation A Write operation requires a START condition, followed by a valid A Read operation consists of a three byte instruction followed by Identification Byte, a valid Address Byte, a Data Byte, and a STOP one or more Data Bytes (see Figure 30). The master initiates the condition. After each of the three bytes, the ISL23328 responds operation issuing the following sequence: a START, the with an ACK. The data is transferred from I2C block to the Identification byte with the R/W bit set to “0”, an Address Byte, a corresponding register at the 9th clock of the data byte and the second START, and a second Identification byte with the R/W bit device enters its standby state (see Figures 28 and 29). set to “1”. After each of the three bytes, the ISL23328 responds with an ACK; then the ISL23328 transmits Data Byte. The master It is possible to perform a sequential Write to all DCP channels terminates the read operation issuing a NACK (ACK) and a STOP via a single Write operation. The command is initiated by sending condition following the last bit of the last Data Byte (see an additional Data Byte after the first Data byte instead of Figure30). sending a STOP condition. FN7902 Rev 1.00 Page 16 of 20 September 29, 2015

ISL23328 Applications Information V Requirements LOGIC VLOGIC should be powered continuously during normal operation. In a case where turning VLOGIC OFF is necessary, it is recommended to ground the VLOGIC pin of the ISL23328. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as possible. V Requirements and Placement CC It is recommended to put a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to the VCC pin. Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., 6Fh to 7Fh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN7902 Rev 1.00 Page 17 of 20 September 29, 2015

ISL23328 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE September 29, 2015 FN7902.1 Updated Ordering Information Table on page 3. Updated “Product“ section to “About Intersil”. Updated POD L16.2.6x1.8A from rev 5 go rev 6. Change since rev 5: Changed in Note 5 0.30 to 0.25 August 19, 2011 FN7902.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2011-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7902 Rev 1.00 Page 18 of 20 September 29, 2015

ISL23328 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 14 8 SEE DETAIL "X" 6.40 PIN #1 4.40 ±0.10 I.D. MARK 2 3 0.20 CBA 1 7 0.65 B 0.09-0.20 TOP VIEW END VIEW 1.00 REF H 0.05 C 0.90 +0.15/-0.10 1.20 MAX SEATING GAUGE PLANE PLANE 0.25 0.25 +0.05/-0.06 5 0.10C 0.10 CBA 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. TYPICAL RECOMMENDED LAND PATTERN FN7902 Rev 1.00 Page 19 of 20 September 29, 2015

ISL23328 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) L16.2.6x1.8A D A B 16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 6 INDEX AREA N E SYMBOL MIN NOMINAL MAX NOTES 2X 0.10 C A 0.45 0.50 0.55 - 1 2 A1 - - 0.05 - 2X 0.10 C A3 0.127 REF - TOP VIEW b 0.15 0.20 0.25 5 D 2.55 2.60 2.65 - 0.10 C C E 1.75 1.80 1.85 - A 0.05C e 0.40 BSC - SEATING PLANE A1 K 0.15 - - - SIDE VIEW L 0.35 0.40 0.45 - L1 0.45 0.50 0.55 - N 16 2 e PIN #1 ID Nd 4 3 K 1 2 Ne 4 3 L1 NX L  0 - 12 4 NX b 5 Rev. 6 1/14 (DATUM B) 16X NOTES: (DATUM A) 0.10 M CAB 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 0.05 M C 2. N is the number of terminals. BOTTOM VIEW 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured CL between 0.15mm and 0.25mm from the terminal tip. (A1) 6. The configuration of the pin #1 identifier is optional, but must be NX (b) L located within the zone indicated. The pin #1 identifier may be 5 either a mold or mark feature. e 7. Maximum package warpage is 0.05mm. SECTION "C-C" 8. Maximum allowable burrs is 0.076mm in all directions. C C TERMINAL TIP 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 3.00 1.80 1.40 1.40 2.20 0.90 0.40 0.20 0.20 0.50 0.40 10 LAND PATTERN FN7902 Rev 1.00 Page 20 of 20 September 29, 2015