DATASHEET ISL23315 FN7778 Single, Low Voltage Digitally Controlled Potentiometer (XDCP™) Rev 2.00 August 12, 2015 The ISL23315 is a volatile, low voltage, low noise, low power, I2C Features Bus™, 256Taps, single digitally controlled potentiometer (DCP), which integrates DCP core, wiper switches and control logic on • 256 resistor taps a monolithic CMOS integrated circuit. • I2C serial interface The digitally controlled potentiometer is implemented with a - No additional level translator for low bus supply combination of resistor elements and CMOS switches. The - Two address pins allow up to four devices per bus position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated • Power supply volatile Wiper Register (WR) that can be directly written to and - VCC = 1.7V to 5.5V analog power supply read by the user. The contents of the WR controls the position - VLOGIC = 1.2V to 5.5V I2C bus/logic power supply of the wiper. When powered on, the ISL23315’s wiper will always commence at mid-scale (128 tap position). • Wiper resistance: 70 typical @ VCC = 3.3V • Shutdown Mode - forces the DCP into an end-to-end open The low voltage, low power consumption, and small package circuit and RW is shorted to RL internally of the ISL23315 make it an ideal choice for use in battery operated equipment. In addition, the ISL23315 has a VLOGIC • Power-on preset to mid-scale (128 tap position) pin allowing down to 1.2V bus operation, independent from the • Shutdown and standby current <2.8µA max VCC value. This allows for low logic levels to be connected directly to the ISL23315 without passing through a voltage • DCP terminal voltage from 0V to VCC level shifter. • 10k 50kor 100k total resistance The DCP can be used as a three-terminal potentiometer or as a • Extended industrial temperature range: -40°C to +125°C two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • 10 Ld MSOP or 10 Ld µTQFN packages • Pb-free (RoHS compliant) Applications • Power supply margining • RF power amplifier bias compensation • LCD bias compensation • Laser diode bias compensation 10000 8000 Ω) E ( 6000 C N A T S SI 4000 E R 2000 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP FIGURE 2. VREF ADJUSTMENT POSITION, 10k DCP FN7778 Rev 2.00 Page 1 of 20 August 12, 2015

ISL23315 Block Diagram VLOGIC VCC SCL RH POWER-UP SDA INTERFACE, A1 BLIO/OCK SLHEIFVTEELR COANNTDROL VOLWARTILE A0 STATUS REGISTER LOGIC AND WIPER CONTROL CIRCUITRY RL RW GND Pin Configurations Pin Descriptions ISL23315 MSOP µTQFN SYMBOL DESCRIPTION (10TO LPD VMIESWOP) 1 10 VLOGIC I2C bus /logic supply. Range 1.2V to 5.5V VLOGIC 1 10 GND 2 1 SCL Logic Pin - Serial bus clock input SCL 2 9 VCC 3 2 SDA Logic Pin - Serial bus data SDA 3 8 RH input/open drain output A0 4 7 RW 4 3 A0 Logic Pin - Hardwire slave address A1 5 6 RL pin for I2C serial bus. Range: VLOGIC or GND ISL23315 5 4 A1 Logic Pin - Hardwire slave address (10 LD µTQFN) pin for I2C serial bus. TOP VIEW Range: VLOGIC or GND C 6 5 RL DCP “low” terminal GI O L 7 6 RW DCP wiper terminal V 10 8 7 RH DCP “high” terminal SCL 1 9 GND 9 8 VCC Analog power supply. SDA 2 8 VCC Range 1.7V to 5.5V A0 3 7 RH 10 9 GND Ground pin A1 4 6 RW 5 L R FN7778 Rev 2.00 Page 2 of 20 August 12, 2015

ISL23315 Ordering Information RESISTANCE TEMP PART NUMBER PART OPTION RANGE PACKAGE PKG. (Note 5) MARKING (kΩ) (°C) (Pb-free) DWG. # ISL23315TFUZ (Notes 1, 3) 3315T 100 -40 to +125 10 Ld MSOP M10.118 ISL23315UFUZ (Notes 1, 3) 3315U 50 -40 to +125 10 Ld MSOP M10.118 (No longer available,recommended replacement: ISL23315TFUZ-TK) ISL23315WFUZ (Notes 1, 3) 3315W 10 -40 to +125 10 Ld MSOP M10.118 ISL23315TFRUZ-T7A (Notes 2, 4) HB 100 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL23315TFRUZ-TK (Notes 2, 4) HB 100 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A ISL23315UFRUZ-T7A (Notes 2, 4) HA 50 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available,recommended replacement: ISL23315TFUZ-TK) ISL23315UFRUZ-TK (Notes 2, 4) HA 50 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available,recommended replacement: ISL23315TFUZ-TK) ISL23315WFRUZ-T7A (Notes 2, 4) GZ 10 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available,recommended replacement: ISL23315TFUZ-TK) ISL23315WFRUZ-TK (Notes 2, 4) GZ 10 -40 to +125 10 Ld 2.1x1.6 µTQFN L10.2.1x1.6A (No longer available,recommended replacement: ISL23315TFUZ-TK) NOTES: 1. Add “-TK” or “-T7A” suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications. 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23315. For more information on MSL please see techbrief TB363. FN7778 Rev 2.00 Page 3 of 20 August 12, 2015

ISL23315 Absolute Maximum Ratings Thermal Information Supply Voltage Range Thermal Resistance (Typical) JA (°C/W) JC (°C/W) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 10 Ld MSOP Package (Notes 6, 7). . . . . . . 170 70 VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 10 Ld µTQFN Package (Notes 6, 7) . . . . . . 145 90 Voltage on Any DCP Terminal Pin. . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C Voltage on Any Digital Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Wiper current IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV CDM Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . . . . . . . . 1kV Recommended Operating Conditions Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V Latch Up Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7V to 5.5V VLOGIC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.2V to 5.5V DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6.  is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. JA 7. For JC, the “case temp” location is the center top of the package. Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS RTOTAL RH to RL Resistance W option 10 k U option 50 k T option 100 k RH to RL Resistance Tolerance -20 ±2 +20 % End-to-End Temperature Coefficient W option 175 ppm/°C U option 85 ppm/°C T option 70 ppm/°C VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0 VCC V RW Wiper Resistance RH - floating, VRL = 0V, force IW current 70 200  to the wiper, IW = (VCC - VRL)/RTOTAL, VCC = 2.7V to 5.5V VCC = 1.7V 580  CH/CL/CW Terminal Capacitance See “DCP Macro Model” on page9 32 pF ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 < 0.1 0.4 µA Noise Resistor Noise Density Wiper at middle point, W option 16 nV Hz Wiper at middle point, U option 49 nV Hz Wiper at middle point, T option 61 nV Hz Feed Thru Digital Feed-through from Bus to Wiper Wiper at middle point -65 dB PSRR Power Supply Reject Ratio Wiper output change if VCC change -75 dB ±10%; wiper at middle point FN7778 Rev 2.00 Page 4 of 20 August 12, 2015

ISL23315 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity, Guaranteed W option -1.0 ±0.5 +1.0 LSB (Note 13) Monotonic (Note 9) U, T option -0.5 ±0.15 +0.5 LSB (Note 9) DNL Differential Non-linearity, Guaranteed W option -1 ±0.4 +1 LSB (Note 12) Monotonic (Note 9) U, T option -0.4 ±0.1 +0.4 LSB (Note 9) FSerror Full-scale Error W option -3.5 -2 0 LSB (Note 11) (Note 9) U, T option -2 -0.5 0 LSB (Note 9) ZSerror Zero-scale Error W option 0 2 3.5 LSB (Note 10) (Note 9) U, T option 0 0.4 2 LSB (Note 9) TCV Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C (Notes 14) U option, Wiper Register set to 80 hex 4 ppm/°C T option, Wiper Register set to 80 hex 2.3 ppm/°C Large Signal Wiper Settling Time From code 0 to FF hex 300 ns fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz Wiper at middle point U option 250 kHz Wiper at middle point T option 120 kHz RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -2.0 ±1 +2.0 MI (Note 18) Monotonic (Note 15) W option; VCC = 1.7V 10.5 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -1.0 ±0.3 +1.0 MI (Note 15) U, T option; VCC = 1.7V 2.1 MI (Note 15) RDNL Differential Non-linearity, Guaranteed W option; VCC = 2.7V to 5.5V -1 ±0.4 +1 MI (Note 17) Monotonic (Note 15) W option; VCC = 1.7V ±0.6 MI (Note 15) U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI (Note 15) U, T option; VCC = 1.7V ±0.35 MI (Note 15) FN7778 Rev 2.00 Page 5 of 20 August 12, 2015

ISL23315 Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS Roffset Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 0 3 5.5 MI (Note 16) (Note 15) W option; VCC = 1.7V 6.3 MI (Note 15) U, T option; VCC = 2.7V to 5.5V 0 0.5 2 MI (Note 15) U, T option; VCC = 1.7V 1.1 MI (Note 15) TCR Resistance Temperature Coefficient W option; Wiper register set between 220 ppm/°C (Note 19) 32 hex and FF hex U option; Wiper register set between 32 100 ppm/°C hex and FF hex T option; Wiper register set between 32 75 ppm/°C hex and FF hex Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V, 200 µA fSCL = 400 kHz (for I2C active read and write) VLOGIC = 1.2V, VCC = 1.7V, 5 µA fSCL = 400 kHz (for I2C active read and write) ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 18 µA VLOGIC = 1.2V, VCC = 1.7V 10 µA ILOGIC SB VLOGIC Standby Current VLOGIC = VCC = 5.5V, 1.3 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.4 µA I2C interface in standby ICC SB VCC Standby Current VLOGIC = VCC = 5.5V, 1.5 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1 µA I2C interface in standby ILOGIC VLOGIC Shutdown Current VLOGIC = VCC = 5.5V, 1.3 µA SHDN I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 0.4 µA I2C interface in standby ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V, 1.5 µA I2C interface in standby VLOGIC = 1.2V, VCC = 1.7V, 1 µA I2C interface in standby FN7778 Rev 2.00 Page 6 of 20 August 12, 2015

ISL23315 Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note8) (Note 20) UNITS tDCP Wiper Response Time W option; SCL rising edge of the 0.4 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. U option; SCL rising edge of the 1.5 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. T option; SCL rising edge of the 3.5 µs acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. ILkgDig Leakage Current, at Pins A0, A1, SDA, Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA SCL tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit 1.5 µs after ACR data byte to wiper recalled position and RH connection VCC, VLOGIC VCC ,VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms Ramp (Note 21) Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note 8) (Note 20) UNITS VIL Input LOW Voltage -0.3 0.3 x VLOGIC V VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC + 0.3 V Hysteresis SDA and SCL Input Buffer VLOGIC > 2V 0.05 x VLOGIC V Hysteresis VLOGIC <2V 0.1 x VLOGIC VOL SDA Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V IOL = 1.5mA, 0.2 x VLOGIC V VLOGIC <2V Cpin SDA, SCL Pin Capacitance 10 pF fSCL SCL Frequency 400 kHz tsp Pulse Width Suppression Time at Any pulse narrower than the 50 ns SDA and SCL Inputs max spec is suppressed tAA SCL Falling Edge to SDA Output SCL falling edge crossing 30% 900 ns Data Valid of VLOGIC, until SDA exits the 30% to 70% of VLOGIC window tBUF Time the Bus Must be Free Before SDA crossing 70% of VLOGIC 1300 ns the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VLOGIC during the following START condition tLOW Clock LOW Time Measured at the 30% of 1300 ns VLOGIC crossing tHIGH Clock HIGH Time Measured at the 70% of 600 ns VLOGIC crossing tSU:STA START Condition Set-up Time SCL rising edge to SDA falling 600 ns edge; both crossing 70% of VLOGIC FN7778 Rev 2.00 Page 7 of 20 August 12, 2015

ISL23315 Serial Interface Specification for SCL, SDA, A0, A1 Unless Otherwise Noted. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 20) (Note 8) (Note 20) UNITS tHD:STA START Condition Hold Time From SDA falling edge 600 ns crossing 30% of VLOGIC to SCL falling edge crossing 70% of VLOGIC tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 100 ns 70% of VLOGIC window, to SCL rising edge crossing 30% of VLOGIC tHD:DAT Input Data Hold Time From SCL falling edge crossing 0 ns 70% of VCC to SDA entering the 30% to 70% of VCC window tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 600 ns 70% of VLOGIC, to SDA rising edge crossing 30% of VLOGIC tHD:STO STOP Condition Hold Time for Read From SDA rising edge to SCL 1300 ns or Write falling edge; both crossing 70% of VCC (Note11) tDH Output Data Hold Time From SCL falling edge crossing 0 ns 30% of VLOGIC, until SDA enters the 30% to 70% of VLOGIC window. IOL=3mA,VLOGIC > 2V. IOL=0.5mA, VLOGIC < 2V tR SDA and SCL Rise Time From 30% to 70% of VLOGIC 20 + 0.1 x Cb 250 ns tF SDA and SCL Fall Time From 70% to 30% of VLOGIC 20 + 0.1 x Cb 250 ns Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF (Note 11) tSU:A A1, A0 Setup Time Before START condition 600 ns tHD:A A1, A0 Hold Time After STOP condition 600 ns NOTES: 8. Typical values are for TA = +25°C and 3.3V supply voltages. 9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 10. ZS error = V(RW)0/LSB. 11. FS error = [V(RW)255 – VCC]/LSB. 12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255 14. TCV = M------a----x-----V---V---R---R--W--W-----i-i----+-–---2-M--5---i-°-n---C----V------R----W--------i---+----1--1--6--0-5---6-°----C-- fvoor lit a=g 1e6 a tnod 2 M5i5n (d )e icsi mthael ,m T i=n i-m40u°mC v taol u+e1 2of5 t°hCe. wMiapxe(r )v iosl ttahgee m oavxeirm thuem t evmalupee roaft uthree rwainpgeer . 15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 16. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255. 18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255. 19. MaxRi–MinRi 106 for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the TCR = -------------R-----i----+----2---5----°----C------------------+----1----6---5-----°---C-- minimum value of the resistance over the temperature range. 20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 21. It is preferable to ramp up both the VLOGIC and the VCC supplies at the same time. If this is not possible it is recommended to ramp-up the VLOGIC first followed by the VCC. FN7778 Rev 2.00 Page 8 of 20 August 12, 2015

ISL23315 DCP Macro Model RTOTAL RH RL CL CH CW 32pF 32pF 32pF RW Timing Diagrams SDA vs SCL Timing tF tHIGH tLOW tR tsp SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) A0 and A1 Pin Timing START STOP SCL CLK 1 SDA tSU:A tHD:A A0, A1 FN7778 Rev 2.00 Page 9 of 20 August 12, 2015

ISL23315 Typical Performance Curves 0.4 0.30 0.2 0.15 )B )B S S L( L 0 L( L 0 N N D D -0.2 -0.15 -0.4 -0.30 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V 0.4 0.30 0.2 0.15 )B )B S S L 0 L 0 ( L ( L N N I I -0.2 -0.15 -0.4 -0.30 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V 0.4 0.30 0.2 0.15 )IM )IM ( LN 0 (L N 0 D D R R -0.2 -0.15 -0.4 -0.30 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V FN7778 Rev 2.00 Page 10 of 20 August 12, 2015

ISL23315 Typical Performance Curves (Continued) 0.6 0.30 0.4 0.15 0.2 )IM )IM (L NIR 0 ( LNIR 0 -0.2 -0.15 -0.4 -0.6 -0.30 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V 70 60 +125°C +125°C 60 50 +25°C ) ) ( EC 50 +25°C ( EC 40 N N A 40 A T T SIS SIS 30 E 30 E R R RE RE 20 -40°C P 20 P IW IW -40°C 10 10 0 0 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V 300 70 60 250 50 200 )C )C °/m °/m 40 p 150 p p p ( v ( v 30 C C T 100 T 20 50 10 0 0 15 65 115 165 215 15 65 115 165 215 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION FN7778 Rev 2.00 Page 11 of 20 August 12, 2015

ISL23315 Typical Performance Curves (Continued) 600 200 500 150 400 )C )C °/m °/m p 300 p 100 p p (r C (r C T 200 T 50 100 0 0 15 65 115 165 215 15 65 115 165 215 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION 35 120 30 90 25 )C )C °/m 20 °/m p p 60 p p (v C 15 ( Cr T T 10 30 5 0 0 15 65 115 165 215 15 65 115 165 215 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 17. 100k TCv vs TAP POSITION FIGURE 18. 100k TCr vs TAP POSITION SCL CLOCK RW PIN 10mV/DIV 20mV/DIV 1µs/DIV 5µs/DIV FIGURE 19. WIPER DIGITAL FEED-THROUGH FIGURE 20. WIPER TRANSITION GLITCH FN7778 Rev 2.00 Page 12 of 20 August 12, 2015

ISL23315 Typical Performance Curves (Continued) 1V/DIV 1V/DIV 1µs/DIV 0.1s/DIV WIPER SCL 9TH CLOCK OF THE DATA BYTE (ACK) FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE 1.2 CH1: 0.5V/DIV, 0.2µs/DIV RH PIN CH2: 0.2V/DIV, 0.2µs/DIV RW PIN )A 1.0 µ ( C C IT 0.8 VCC = 5.5V, VLOGIC = 5.5V N E R R 0.6 U C Y BD 0.4 N AT VCC = 1.7V, VLOGIC = 1.2V S 0.2 RTOTAL = 10k 0 -40 -15 10 35 60 85 110 -3dB FREQUENCY = 1.4MHz AT MIDDLE TAP TEMPERATURE (°C) FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE Functional Pin Descriptions Bus Interface Pins Potentiometers Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C RH AND RL interface. It receives device address, operation code, wiper The high (RH) and low (RL) terminals of the ISL23315 are address and data from an I2C external master device at the equivalent to the fixed terminals of a mechanical potentiometer. rising edge of the serial clock SCL, and it shifts out data after RH and RL are referenced to the relative position of the wiper and each falling edge of the serial clock. not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, SDA requires an external pull-up resistor, since it is an open drain the wiper is closest to RL. input/output. RW SERIAL CLOCK (SCL) RW is the wiper terminal, and it is equivalent to the movable This input is the serial clock of the I2C serial interface. SCL terminal of a mechanical potentiometer. The position of the requires an external pull-up resistor, since a master is an open wiper within the array is determined by the WR register. drain output. FN7778 Rev 2.00 Page 13 of 20 August 12, 2015

ISL23315 DEVICE ADDRESS (A1, A0) Memory Description The address inputs are used to set the least significant 2 bits of The ISL23315 contains two volatile 8-bit registers: Wiper Register the 7-bit I2C interface slave address. A match in the slave (WR) and Access Control Register (ACR). The memory map of address serial data stream must match with the Address input ISL23315 is shown in Table 1. The Wiper Register (WR) at address 0 pins in order to initiate communication with the ISL23315. A contains current wiper position. The Access Control Register (ACR) maximum of four ISL23315 devices may occupy the I2C serial at address 10h contains information and control bits described bus (see Table 3). in Table 2. VLOGIC TABLE 1. MEMORY MAP This is an input pin, that supplies internal level translator for ADDRESS VOLATILE DEFAULT SETTING serial bus operation from 1.2V to 5.5V. (hex) REGISTER NAME (hex) Principles of Operation 10 ACR 40 0 WR 40 The ISL23315 is an integrated circuit incorporating one DCP with its associated registers and an I2C serial interface providing TABLE 2. ACCESS CONTROL REGISTER (ACR) direct communication between a host and the potentiometer. The resistor array is comprised of individual resistors connected BIT # 7 6 5 4 3 2 1 0 in series. At either end of the array and between each resistor is NAME/ 0 SHDN 0 0 0 0 0 0 an electronic switch that transfers the potential at that point to VALUE the wiper. Shutdown Function The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. The SHDN bit (ACR[6]) disables or enables shutdown mode for all Voltage at any DCP pins, RH, RL or RW, should not exceed VCC DCP channels simultaneously. When this bit is 0, i.e., DCP is forced level at any conditions during power-up and normal operation. to end-to-end open circuit and RW is connected to RL through a 2kΩ serial resistor, as shown in Figure 25. Default value of the The VLOGIC pin needs to be connected to the I2C bus supply SHDN bit is 1. which allows reliable communication with the wide range of RH microcontrollers and independent of the VCC level. This is extremely important in systems where the master supply has lower levels than DCP analog supply. DCP Description RW The DCP is implemented with a combination of resistor elements 2kΩ and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to RL intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE within the DCP is controlled by an 8-bit volatile Wiper Register In the shutdown mode, the RW terminal is shorted to the RL (WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h), terminal with around 2kΩ resistance, as shown in Figure 25. When its wiper terminal (RW) is closest to its “Low” terminal (RL). When the device enters shutdown, all current DCP WR settings are the WR register of a DCP contains all ones (WR[7:0]= FFh), its maintained. When the device exits shutdown, the wipers will return wiper terminal (RW) is closest to its “High” terminal (RH). As the to the previous WR settings after a short settling time (see value of the WR increases from all zeroes (0) to all ones (255 Figure26). decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the In shutdown mode, if there is a glitch on the power supply which resistance between RW and RL increases monotonically, while causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the the resistance between RH and RW decreases monotonically. wipers will be RESET to their mid position. This is done to avoid an undefined state at the wiper outputs. While the ISL23315 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WR can be read or written to directly using the I2C serial interface as described in the following sections. FN7778 Rev 2.00 Page 14 of 20 August 12, 2015

ISL23315 All I2C interface operations must begin with a START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The ISL23315 continuously monitors the SDA and SCL lines for the V) (W START condition and does not respond to any command until this VR POWER-UP MID SCALE = 80H condition is met (see Figure 27). A START condition is ignored E, during the power-up of the device. AG USER PROGRAMMED AFTER SHDN OLT All I2C interface operations must be terminated by a STOP V R SHDN ACTIVATED SHDN RELEASED condition, which is a LOW to HIGH transition of SDA while SCL is PE WIPER RESTORE TO HIGH (see Figure 27). A STOP condition at the end of a read WI THE ORIGINAL POSITION operation or at the end of a write operation places the device in SHDN MODE its standby mode. 0 TIME (s) An ACK (Acknowledge) is a software convention used to indicate FIGURE 26. SHUTDOWN MODE WIPER RESPONSE a successful data transfer. The transmitting device, either master 2 or slave, releases the SDA bus after transmitting eight bits. I C Serial Interface During the ninth clock cycle, the receiver pulls the SDA line LOW The ISL23315 supports an I2C bidirectional bus oriented to acknowledge the reception of the eight bits of data protocol. The protocol defines any device that sends data onto (seeFigure28). the bus as a transmitter and the receiving device as the receiver. The ISL23315 responds with an ACK after recognition of a START The device controlling the transfer is a master and the device condition followed by a valid Identification Byte, and once again being controlled is the slave. The master always initiates data after successful receipt of an Address Byte. The ISL23315 also transfers and provides the clock for both transmit and receive responds with an ACK after receiving a Data Byte of a write operations. Therefore, the ISL23315 operates as a slave device operation. The master must respond with an ACK after receiving in all applications. a Data Byte of a read operation. All communication over the I2C interface is conducted by sending A valid Identification Byte contains 10100 as the five MSBs, and the MSB of each byte of data first. the following two bits matching the logic values present at pins A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Protocol Conventions Read operation and “0” for a Write operation (see Table 3). Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for TABLE 3. IDENTIFICATION BYTE FORMAT indicating START and STOP conditions (see Figure 27). On LOGIC VALUES AT PINS A1 AND A0, RESPECTIVELY power-up of the ISL23315, the SDA pin is in the input mode. 1 0 1 0 0 A1 A0 R/W (MSB) (LSB) SCL SDA START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS FN7778 Rev 2.00 Page 15 of 20 August 12, 2015

ISL23315 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S SIGNALS FROM T S THE MASTER A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 1 0 1 0 0A1A00 0 0 0 SIGNALS FROM A A A THE SLAVE C C C K K K FIGURE 29. BYTE WRITE SEQUENCE READ S S SIGNALS T T S FROM THE A IDENTIFICATION A IDENTIFICATION A A A T MASTER R BYTE WITH ADDRESS R BYTE WITH C C C O T R/W = 0 BYTE T R/W = 1 K K K P SIGNAL AT SDA 1 0 1 0 0A1A00 0 0 0 1 0 1 0 0A1A01 A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 30. READ SEQUENCE FN7778 Rev 2.00 Page 16 of 20 August 12, 2015

ISL23315 Write Operation Applications Information A Write operation requires a START condition, followed by a valid V Requirements Identification Byte, a valid Address Byte, a Data Byte, and a STOP LOGIC condition. After each of the three bytes, the ISL23315 responds It is recommended to keep VLOGIC powered all the time during with an ACK. The data is transferred from I2C block to the normal operation. In a case where turning VLOGIC OFF is corresponding register at the 9th clock of the data byte and necessary, it is recommended to ground the VLOGIC pin of the device enters its standby state (see Figures 28 and 29). ISL23315. Grounding the VLOGIC pin or both VLOGIC and VCC does not affect other devices on the same bus. It is good practice to Read Operation put a 1µF cap in parallel to 0.1µF as close to the VLOGIC pin as A Read operation consists of a three byte instruction followed by possible. one or more Data Bytes (see Figure 30). The master initiates the V Requirements and Placement operation issuing the following sequence: a START, the CC Identification byte with the R/W bit set to “0”, an Address Byte, a It is recommended to put a 1µF capacitor in parallel with 0.1µF second START, and a second Identification byte with the R/W bit decoupling capacitor close to the VCC pin. set to “1”. After each of the three bytes, the ISL23315 responds Wiper Transition with an ACK; then the ISL23315 transmits Data Byte. The master terminates the read operation issuing a NACK (ACK) and a STOP When stepping up through each tap in voltage divider mode, condition following the last bit of the last Data Byte (see some tap transition points can result in noticeable voltage Figure30). transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” to a much higher impedance “break” within a short period of time (<1µs). There are several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to FFh, which have higher transient glitch. Note, that all switching transients will settle well within the settling time as stated in the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients. However, that will also reduce the useful bandwidth of the circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery. FN7778 Rev 2.00 Page 17 of 20 August 12, 2015

ISL23315 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 8/12/15 FN7778.2 Updated Ordering Information table on page3 Changed Products section to About Intersil. Updated POD M10.118 from rev 0 to rev 1. Changes since rev0: Updated to new POD template. Added land pattern 7/29/11 FN7778.1 On page7, “Wiper Response Time” changed text in each option From: CS rising edge to wiper new position, from 10% to 90% of final value. To: SCL rising edge of the acknowledge bit after data byte to wiper new position from 10% to 90% of the final value. 07/28/11 Added “Shutdown Function” section and revised “VLOGIC Standby Current” and “VCC Shutdown Current” limits on page6. On page7, split “Wiper Response Time” up into 3 separate conditions for each option (W, U, T). 12/15/10 FN7778.0 Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2010-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7778 Rev 2.00 Page 18 of 20 August 12, 2015

ISL23315 Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN7778 Rev 2.00 Page 19 of 20 August 12, 2015

ISL23315 Package Outline Drawing L10.2.1x1.6A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 3/10 8. PIN 1 INDEX AREA 2.10 A PIN #1 ID B 0.05 MIN. 1 8. 1 4 0.10 MIN. 4X 0.20 MIN. 0 6 1. 10 5 0.80 10X 0.40 0.10 2X 9 6 6X 0.50 10 X 0.20 4 TOP VIEW 0.10M C AB BOTTOM VIEW M C SEE DETAIL "X" (0.05 MIN) (10 X 0.20) 1 PACKAGE MAX. 0.55 OUTLINE 0.10 C (10X 0.60) C (0.10 MIN.) SEATING PLANE 0.08 C (2.00) SIDE VIEW (0.80) (1.30) 0 . 125 REF C (6X 0.50 ) (2.50) 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. Angles are in degrees. Dimensions in ( ) for Reference Only. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Maximum package warpage is 0.05mm. 6. Maximum allowable burrs is 0.076mm in all directions. 7. Same as JEDEC MO-255UABD except: No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm Lead Length dim. = 0.45mm max. not 0.42mm. 8. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7778 Rev 2.00 Page 20 of 20 August 12, 2015