DATASHEET NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc ISL22414 FN6424 Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI® Rev 2.00 Bus, 256 Taps September 21, 2015 The ISL22414 integrates a single digitally controlled Features potentiometer (DCP), control logic and non-volatile memory • 256 resistor taps on a monolithic CMOS integrated circuit. • SPI serial interface with write/read capability The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The • Daisy Chain Configuration position of the wiper is controlled by the user through the SPI • Shutdown mode serial interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value • Non-volatile EEPROM storage of wiper position Register (IVR) that can be directly written to and read by the • 14 General Purpose non-volatile registers user. The contents of the WR control the position of the • High reliability wiper. At power-up the device recalls the contents of the DCP’s IVR to the WR. - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T 55°C The ISL22414 also has 14 General Purpose non-volatile registers that can be used as storage of lookup table for • Wiper resistance: 70 typical @ 1mA multiple wiper position or any other valuable information. • Standby current <2.5µA max The ISL22414 features a dual supply that is beneficial for • Shutdown current <2.5µA max applications requiring a bipolar range for DCP terminals between V- and VCC. • Dual power supply The DCP can be used as three-terminal potentiometer or as - VCC = 2.25V to 5.5V two-terminal variable resistor in a wide variety of applications - V- = -2.25V to -5.5V including control, parameter adjustments, and signal • 10k 50kor 100k total resistance processing. • Extended industrial temperature range: -40°C to +125°C Pinout • Military temperature range: -55 to +125°C ISL22414 (10 LD MSOP) • 10 Lead MSOP TOP VIEW • Pb-free (RoHS compliant) SCK 1O 10 Vcc SDO 2 9 RH SDI 3 8 RW CS 4 7 RL V- 5 6 GND FN6424 Rev 2.00 Page 1 of 17 September 21, 2015

ISL22414 Ordering Information PART NUMBER PART RESISTANCE OPTION TEMP. RANGE PACKAGE PKG. (NOTES 1, 2) MARKING (k) (°C) (Pb-Free) DWG. # ISL22414TFU10Z 414TZ 100 -40 to +125 10 Ld MSOP M10.118 ISL22414TFU10Z-TK 414TZ 100 -40 to +125 10 Ld MSOP M10.118 ISL22414UFU10Z (No longer available, 414UZ 50 -40 to +125 10 Ld MSOP M10.118 Recommended Replacement ISL22414TFU10Z-TK) ISL22414UFU10Z-TK (No longer 414UZ 50 -40 to +125 10 Ld MSOP M10.118 available, Recommended Replacement ISL22414TFU10Z-TK) ISL22414WFU10Z (No longer 414WZ 10 -40 to +125 10 Ld MSOP M10.118 available, Recommended Replacement ISL22414TFU10Z-TK) ISL22414WFU10Z-T7A 414WZ 10 -40 to +125 10 Ld MSOP M10.118 ISL22414WFU10Z-TK 414WZ 10 -40 to +125 10 Ld MSOP M10.118 ISL22414WMU10Z (No longer 414WM 10 -55 to +125 10 Ld MSOP M10.118 available, Recommended Replacement ISL22414TFU10Z-TK) ISL22414WMU10Z-T7A (No longer 414WM 10 -55 to +125 10 Ld MSOP M10.118 available, Recommended Replacement ISL22414TFU10Z-TK) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 2. Please refer to TB347 for details on reel specifications. FN6424 Rev 2.00 Page 2 of 17 September 21, 2015

ISL22414 Block Diagram VCC V- SCK RH POWER UP SDO INTERFACE, SDI INTESRPFIACE CAONDNTROL WR CS STATUS VOLATILE REGISTER LOGIC AND WIPER CONTROL CIRCUITRY NON-VOLATILE REGISTERS RL RW GND Pin Descriptions MSOP PIN SYMBOL DESCRIPTION 1 SCK SPI interface clock input 2 SDO Data Output of the SPI serial interface 3 SDI Data Input of the SPI serial interface 4 CS Chip Select active low input 5 V- Negative power supply pin 6 GND Device ground pin 7 RL “Low” terminal of DCP 8 RW “Wiper” terminal of DCP 9 RH “High” terminal of DCP 10 VCC Power supply pin FN6424 Rev 2.00 Page 3 of 17 September 21, 2015

ISL22414 Absolute Maximum Ratings Thermal Information Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Thermal Resistance (Typical, Note 3) JA (°C/W) Voltage at any Digital Interface Pin 10 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 with Respect to GND . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3 Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-6V to 0.3V http://www.intersil.com/pbfree/Pb-FreeReflow.asp Voltage at any DCP pin with Respect to GND. . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Recommended Operating Conditions Latchup . . . . . . . . . . . . . . . . . . . . . . . . .Class II, Level A @ +125°C ESD Temperature Range Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Full Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400V Military. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.25V to 5.5V V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. A nalog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 18) (Note4) (Note 18) UNIT RTOTAL RH to RL Resistance W option 10 k U option 50 k T option 100 k RH to RL Resistance Tolerance -20 +20 % End-to-End Temperature W option ±150 ppm/°C Coefficient U, T option ±50 ppm/°C VRH, VRL DCP Terminal Voltage VRH and VRL to GND V- VCC V RW Wiper Resistance RH - floating, VRL = V-, force Iw current to the 70 250  wiper, IW = (VCC - VRL)/RTOTAL CH/CL/CW Potentiometer Capacitance See “DCP Macro Model” on page8 10/10/25 pF ILkgDCP Leakage on DCP Pins Voltage at pin from V- to VCC -1 0.1 1 µA VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity W option -1.5 ±0.5 1.5 LSB (Note 9) Monotonic Over All Tap Positions (Note 5) U, T option -1.0 ±0.2 1.0 LSB (Note 5) DNL Differential Non-linearity W option -1.0 ±0.4 1.0 LSB (Note 8) Monotonic Over All Tap Positions (Note 5) U, T option -0.5 ±0.15 0.5 LSB (Note 5) ZSerror Zero-scale Error W option 0 1 5 LSB (Note6) (Note 5) U, T option 0 0.5 2 FSerror Full-scale Error W option -5 -1 0 LSB (Note7) (Note 5) U, T option -2 -1 0 TCV Ratiometric Temperature DCP register set to 80 hex ±4 ppm/°C (Note10) Coefficient FN6424 Rev 2.00 Page 4 of 17 September 21, 2015

ISL22414 Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over the operating temperature range. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 18) (Note4) (Note 18) UNIT fcutoff -3dB Cut Off Frequency Wiper at midpoint (80hex) W option (10k) 1000 kHz Wiper at midpoint (80hex) U option (50k) 250 kHz Wiper at midpoint (80hex) T option (100k) 120 kHz RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity W option -3 ±1.5 3 MI (Note14) (Note11) U, T option -1 ±0.3 1 MI (Note11) RDNL Differential Non-linearity W option -1.5 ±0.4 1.5 MI (Note13) (Note11) U, T option -0.5 ±0.15 0.5 MI (Note11) Roffset Offset W option 0 1 5 MI (Note12) (Note11) U, T option 0 0.5 2 MI (Note11) TCR Resistance Temperature DCP register set between 32 hex and FF hex ±50 ppm/°C (Notes15) Coefficient Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 18) (Note4) (Note 18) UNIT ICC1 VCC Supply Current VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI 0.36 1 mA (volatilewrite/read) Active, Read and Volatile Write states only) VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI 0.13 0.4 mA Active, Read and Volatile Write states only) IV-1 V- Supply Current V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI -1 -0.18 mA (volatile write/read) Active, Read and Volatile Write states only) V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI -0.4 -0.06 mA Active, Read and Volatile Write states only) ICC2 VCC Supply Current VCC = 5.5V, V- = 5.5V, fSCK = 5MHz; (for SPI 1 2 mA (non-volatilewrite/read) Active, Read and Non-volatile Write states only) VCC = 2.25V, V- = -2.25V, fSCK = 5MHz; (for SPI 0.3 0.7 mA Active, Read and Non-volatile Write states only) IV-2 V- Supply Current V- = -5.5V, VCC = 5.5V, fSCK = 5MHz; (for SPI -2 -1.2 mA (non-volatile write/read) Active, Read and Non-volatile Write states only) V- Supply Current V- = -2.25V, VCC = 2.25V, fSCK = 5MHz; (for SPI -0.7 -0.4 mA (non-volatile write/read) Active, Read and Non-volatile Write states only) ISB VCC Current (standby) VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface 0.2 1.5 µA in standby state VCC = +5.5V, V- = -5.5V @ +125°C, SPI 1 2.5 µA interface in standby state VCC = +2.25V, V- = -2.25V @ +85°C, SPI 0.1 1 µA interface in standby state VCC = +2.25V, V- = -2.25V @ +125°C, SPI 0.5 2 µA interface in standby state FN6424 Rev 2.00 Page 5 of 17 September 21, 2015

ISL22414 Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 18) (Note4) (Note 18) UNIT IV-SB V- Current (Standby) V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface -2.5 -0.7 µA in standby state V- = -5.5V, VCC = +5.5V @ +125°C, SPI -4 -3 µA interface in standby state V- = -2.25V, VCC = +2.25V @ +85°C, SPI -1.5 -0.3 µA interface in standby state V- = -2.25V, VCC = +2.25V @ +125°C, SPI -3 -1 µA interface in standby state ISD VCC Current (Shutdown) VCC = +5.5V, V- = -5.5V @ +85°C, SPI interface 0.2 1.5 µA in standby state VCC = +5.5V, V- = -5.5V @ +125°C, SPI 1 2.5 µA interface in standby state VCC = +2.25V, V- = -2.25V @ +85°C, SPI 0.1 1 µA interface in standby state VCC = +2.25V, V- = -2.25V @ +125°C, SPI 0.5 2 µA interface in standby state IV-SD V- Current (Shutdown) V- = -5.5V, VCC = +5.5V @ +85°C, SPI interface -2.5 -0.7 µA in standby state V- = -5.5V, VCC = +5.5V @ +125°C, SPI -4 -3 µA interface in standby state V- = -2.25V, VCC = +2.25V @ +85°C, SPI -1.5 -0.3 µA interface in standby state V- = -2.25V, VCC = +2.25V @ +125°C, SPI -3 -1 µA interface in standby state ILkgDig Leakage Current, at Pins SCK, SDI, Voltage at pin from GND to VCC -0.5 0.5 µA SDO and CS tWRT DCP Wiper Response Time CS rising edge to wiper new position 1.5 µs tShdnRec DCP Recall Time From Shutdown CS rising edge to wiper stored position and RH 1.5 µs Mode connection Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 1.9 2.1 V VccRamp VCC Ramp Rate 0.2 V/ms tD Power-up Delay VCC above Vpor, to DCP Initial Value Register 5 ms recall completed, and SPI Interface in standby state EEPROM SPECIFICATION EEPROM Endurance 1,000,000 Cycles EEPROM Retention Temperature T 55ºC 50 Years tWC Non-volatile Write Cycle Time 12 20 ms (Note 16) SERIAL INTERFACE SPECIFICATIONS VIL SCK, SDI, and CS Input Buffer LOW -0.3 0.3*VCC V voltage VIH SCK, SDI, and CS Input Buffer HIGH 0.7*VCC VCC+0.3 V Voltage Hysteresis SCK, SDI, and CS Input Buffer 0.05*VCC V Hysteresis VOL SDO Output Buffer LOW Voltage IOL = 4mA for Open Drain output, pull-up 0 0.4 V voltage Vpu = VCC FN6424 Rev 2.00 Page 6 of 17 September 21, 2015

ISL22414 Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits apply over the operating temperature range. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 18) (Note4) (Note 18) UNIT Rpu SDO Pull-up Resistor Off-chip Maximum is determined by tRO and tFO with 2 k (Note 17) maximum bus load Cb = 30pF, fSCK = 5MHz Cpin SCK, SDI, SDO and CS Pin 10 pF Capacitance fSCK SPI Frequency 5 MHz tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns tDIS SDO output Disable Time 0 100 ns tSO SDO Output Setup Time 50 ns tV SDO Output Valid Time 150 ns tHO SDO Output Hold Time 0 ns tRO SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns tCS CS Deselect Time 2 µs NOTES: 4. Typical values are for TA = +25°C and 3.3V supply voltage. 5. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 – VCC]/LSB. 8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 9. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 255 10. TC = -------M-----a----x------V-------R-----W--------i-----–-----M-----i--n------V-------R-----W--------i------------1----0---6----- for i = 16 to 255 decimal, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the V MaxVRW+MinVRW2 TC maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage i i over the temperature range. 11. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 12. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW255/MI, when measuring between RW and RH. 13. RDNL = (RWi – RWi-1)/MI -1, for i = 1 to 255. 14. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 255. 6 15. MaxRi–MinRi 10 for i = 16 to 255, T = -40°C to +125°C or T = -55°C to +125°C. Max( ) is the maximum value of the TC = ------------------------------------------------------------------------------- R MaxRi+MinRi2 TC resistance and Min( ) is the minimum value of the resistance over the temperature range. 16. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 17. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 18. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. FN6424 Rev 2.00 Page 7 of 17 September 21, 2015

ISL22414 DCP Macro Model RTOTAL RH RL CL CH CW 10pF 10pF 25pF RW Timing Diagrams Input Timing tCS CS tLEAD tCYC tLAG SCK ... tSU tH tWL tWH tFI tRI SDI MSB ... LSB HIGH IMPEDANCE SDO Output Timing CS SCK ... tSO tHO tDIS SDO MSB ... LSB tV SDI ADDR XDCP Timing (for All Load Instructions) CS tWRT SCK ... SDI MSB ... LSB VW HIGH IMPEDANCE SDO FN6424 Rev 2.00 Page 8 of 17 September 21, 2015

ISL22414 Typical Performance Curves 80 2.0 T = +125ºC 70 1.5 ANCE () 5600 T = +25ºC NT (µA) 01..50 ICC T E S R SI 40 R 0 E U R C ER 30 BY -0.5 WIP T = -40ºC ND IV- 20 A -1.0 T S 10 -1.5 0 -2.0 0 50 100 150 200 250 -40 0 40 80 120 TAP POSITION (DECIMAL) TEMPERATURE (°C) FIGURE 1. WIPER RESISTANCE vs TAP POSITION FIGURE 2. STANDBY ICC AND IV- vs TEMPERATURE [ I(RW) = VCC/RTOTAL ] FOR 10k (W) 0.50 0.50 T = +25ºC VCC = 5.5V T = +25ºC VCC = 2.25V 0.25 0.25 B) S B) NL (L 0 L (LS 0 D N I -0.25 -0.25 VCC = 5.5V VCC = 2.25V -0.50 -0.50 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) MODE FOR 10k (W) 2.0 0 10k 1.6 -1 VCC = 2.25V 50k SB) 1.2 LSB) -2 VCC = 5.5V R (L OR ( O R RR 0.8 50k ER -3 ZS E VCC = 2.25V VCC = 5.5V FS 10k 0.4 -4 0 -5 -40 0 40 80 120 -40 0 40 80 120 TEMPERATURE (ºC) TEMPERATURE (ºC) FIGURE 5. ZS ERROR vs TEMPERATURE FIGURE 6. FS ERROR vs TEMPERATURE FN6424 Rev 2.00 Page 9 of 17 September 21, 2015

ISL22414 Typical Performance Curves (Continued) 0.5 2.0 T = +25ºC T = +25ºC VCC = 5.5V 1.5 0.25 VCC = 2.25V MI) 1.0 RDNL ( 0 NL (MI) 0.5 RI -0.25 0 VCC = 2.25V VCC = 5.5V -0.50 -0.5 0 50 100 150 200 250 0 50 100 150 200 250 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 10k (W) 1.60 200 10k 1.20 160 %) 10k NGE ( 0.80 5.5V m/ºC) 120 A p H p CTAL 0.40 TCv ( 80 O T R 50k 0.00 40 50k 2.25V -0.40 0 -40 0 40 80 120 16 66 116 166 216 266 TEMPERATURE (ºC) TAP POSITION (DECIMAL) FIGURE 9. END TO END RTOTAL % CHANGE vs FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm TEMPERATURE 500 INPUT OUTPUT 10k 400 C) 300 m/º p p Cr ( 200 T 50k 100 WIPER AT MID POINT (POSITION 80h) 0 RTOTAL = 10k 16 66 116 166 216 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (1MHz) FN6424 Rev 2.00 Page 10 of 17 September 21, 2015

ISL22414 Typical Performance Curves (Continued) CS SCL WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h FIGURE 14. LARGE SIGNAL SETTLING TIME Pin Description CHIP SELECT (CS) CS LOW enables the ISL22414, placing it in the active power Potentiometer Pins mode. A HIGH to LOW transition on CS is required prior to the RH AND RL start of any operation after power up. When CS is HIGH, the ISL22414 is deselected and the SDO pin is at high impedance, The high (RH) and low (RL) terminals of the ISL22414 are and (unless an internal write cycle is underway) the device will equivalent to the fixed terminals of a mechanical be in the standby state. potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the Principles of Operation terminals. With WR set to 255 decimal, the wiper will be closest The ISL22414 is an integrated circuit incorporating one DCP to RH, and with the WR set to 0, the wiper is closest to RL. with its associated registers, non-volatile memory and the SPI RW serial interface providing direct communication between host RW is the wiper terminal and is equivalent to the movable and potentiometer and memory. The resistor array is terminal of a mechanical potentiometer. The position of the comprised of individual resistors connected in a series. At wiper within the array is determined by the WR register. either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the Bus Interface Pins wiper. SERIAL CLOCK (SCK) The electronic switches on the device operate in a “make This is the serial clock input of the SPI serial interface. before break” mode when the wiper changes tap positions. SERIAL DATA OUTPUT (SDO) When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is The SDO is a serial data output pin. During a read cycle, the restored, the content of the IVR is recalled and loaded into the data bits are shifted out on the falling edge of the serial clock WR to set the wiper to the initial position. SCK and will be available to the master on the following rising edge of SCK. DCP Description The output type is configured through ACR[1] bit for Push- Pull The DCP is implemented with a combination of resistor or Open Drain operation. Default setting for this pin is Push- elements and CMOS switches. The physical ends of each DCP Pull. An external pull up resistor is required for Open Drain are equivalent to the fixed terminals of a mechanical output operation. Note, the external pull up voltage not allowed potentiometer (RH and RL pins). The RW pin of the DCP is beyond VCC. connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of SERIAL DATA INPUT (SDI) the wiper terminal within the DCP is controlled by an 8-bit The SDI is the serial data input pin for the SPI interface. It volatile Wiper Register (WR). When the WR of a DCP contains receives device address, operation code, wiper address and all zeroes (WR[7:0]= 00h), its wiper terminal (RW) is closest to data from the SPI remote host device. The data bits are shifted its “Low” terminal (RL). When the WR register of a DCP in at the rising edge of the serial clock SCK, while the CS input contains all ones (WR[7:0]= FFh), its wiper terminal (RW) is is low. FN6424 Rev 2.00 Page 11 of 17 September 21, 2015

ISL22414 closest to its “High” terminal (RH). As the value of the WR The non-volatile IVR and volatile WR registers are accessible increases from all zeroes (0) to all ones (255 decimal), the with the same address. wiper moves monotonically from the position closest to RL to The Access Control Register (ACR) contains information and the closest to RH. At the same time, the resistance between control bits described below in Table 2. RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. The VOL bit (ACR[7]) determines whether the access to wiper registers WR or initial value registers IVR. While the ISL22414 is being powered up, the WR is reset to TABLE 2. ACCESS CONTROL REGISTER (ACR) 80h (128 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes BIT # 7 6 5 4 3 2 1 0 large enough for reliable non-volatile memory reading, the WR BIT VOL SHDN WIP 0 0 0 SDO 0 will be reloaded with the value stored in a non-volatile Initial NAME Value Register (IVR). If VOL bit is 0, the non-volatile IVR register is accessible. If The WR and IVR can be read or written to directly using the VOL bit is 1, only the volatile WR is accessible. Note, value is SPI serial interface as described in the following sections. written to IVR register also is written to the WR. The default value of this bit is 0. Memory Description The ISL22414 contains one non-volatile 8-bit Initial Value The SHDN bit (ACR[6]) disables or enables Shutdown mode. Register (IVR), fourteen non-volatile 8-bit General Purpose When this bit is 0, DCP is in Shutdown mode, i.e. DCP is (GP) registers, volatile 8-bit Wiper Register (WR), and volatile forced to end-to-end open circuit and RW is shorted to RL as 8-bit Access Control Register (ACR). The memory map of shown on Figure 15. Default value of SHDN bit is 1. ISL22414 is in Table 1. RH TABLE 1. MEMORY MAP ADDRESS (hex) NON-VOLATILE VOLATILE RW 10 N/A ACR F Reserved RL E General Purpose N/A FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE D General Purpose N/A Setting SHDN bit to 1 is returned wiper to prior to Shutdown C General Purpose N/A Mode position. B General Purpose N/A The WIP bit (ACR[5]) is a read-only bit. It indicates that non- A General Purpose N/A volatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write 9 General Purpose N/A has been completed. It is impossible to write or read to the WR 8 General Purpose N/A or ACR while WIP bit is 1. 7 General Purpose N/A The SDO bit (ACR[1]) configures type of SDO output pin. The 6 General Purpose N/A default value of SDO bit is 0 for Push - Pull output. SDO pin 5 General Purpose N/A can be configured as Open Drain output for some application. In this case, an external pull up resistor is required. See 4 General Purpose N/A “Applications Information” on page14. 3 General Purpose N/A SPI Serial Interface 2 General Purpose N/A The ISL22414 supports an SPI serial protocol, mode 0. The 1 General Purpose N/A device is accessed via the SDI input and SDO output with data 0 IVR WR clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication The non-volatile register (IVR) at address 0, contains initial with the ISL22414. SCK and CS lines are controlled by the wiper position and volatile register (WR) contains current wiper host or master. The ISL22414 operates only as a slave device. position. All communication over the SPI interface is conducted by The register at address 0Fh is a read-only reserved register. sending the MSB of each byte of data first. Information read from this register should be ignored. FN6424 Rev 2.00 Page 12 of 17 September 21, 2015

ISL22414 Protocol Conventions more Data Bytes to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. Instruction The SPI protocol contains Instruction Byte followed by one or is executed on rising edge of CS. For a write to address 0, the more Data Bytes. A valid Instruction Byte contains instruction MSB of the byte at address 10h (ACR[7]) determines if the as the three MSBs, with the following five register address bits Data Byte is to be written to volatile or both volatile and non- (see Table 3). volatile registers. Refer to “Memory Description” and Figure 16. The next byte sent to the ISL22414 is the Data Byte. Note, the internal non-volatile write cycle starts with the rising edge of CS and requires up to 20ms. During non-volatile write TABLE 3. INSTRUCTION BYTE FORMAT cycle the read operation to ACR register is allowed to check WIP bit. BIT # 7 6 5 4 3 2 1 0 Read Operation I2 I1 I0 R4 R3 R2 R1 R0 A Read operation to the ISL22414 is a four byte operation. It Table 4 contains a valid instruction set for ISL22414. requires first, the CS transition from HIGH to LOW. Then host send a valid Instruction Byte, followed by “dummy” Data Byte, There are only sixteen register addresses possible for this NOP Instruction Byte and another “dummy” Data Byte to SDI DCP. If the [R4:R0] bits are zero, then the read or write is to pin. The SPI host receives the Instruction Byte (instruction either the IVR or the WR register (depends of VOL bit at ACR). code + register address) and requested Data Byte from SDO If the [R4:R0] are 10000, then the operation is on the ACR. pin on the rising edge of SCK during third and fourth bytes Write Operation respectively. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). Reading from A Write operation to the ISL22414 is a two or more bytes the IVR will not change the WR, if its contents are different. operation. It requires first, the CS transition from HIGH to LOW. Then host send a valid Instruction Byte, followed by one or TABLE 4. INSTRUCTION SET INSTRUCTION SET I2 I1 I0 R4 R3 R2 R1 R0 OPERATION 0 0 0 X X X X X NOP 0 0 1 X X X X X ACR READ 0 1 1 X X X X X ACR WRITE 1 0 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR READ 1 1 0 R4 R3 R2 R1 R0 WR, IVR, GP or ACR WRITE where X means “do not care” CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI WR INSTRUCTION ADDR DATA BYTE SDO FIGURE 16. TWO BYTE WRITE SEQUENCE FN6424 Rev 2.00 Page 13 of 17 September 21, 2015

ISL22414 CS 1 8 16 24 32 SCK RD ADDR NOP SDI RD ADDR READ DATA SDO FIGURE 17. FOUR BYTE READ SEQUENCE Applications Information as follow: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1). The write instruction is executed on the rising edge of CS for all N Communicating with ISL22414 DCPs simultaneously. Communication with ISL22414 proceeds using SPI interface Daisy Chain Read Operation through the ACR (address 10000b), IVR (address 00000b), WR (addresses 00000b) and General Purpose registers The read operation consists two parts: first, send read (addresses from 00001b to 01110b). instructions (N two bytes operation) with valid address; second, read the requested data while sending NOP The wiper of the potentiometer is controlled by the WR register. instructions (N two bytes operation) as shown on Figure 20, Writes and reads can be made directly to these register to and Figure 21. control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address The first part starts by HIGH to LOW transition on CS line, 10000b to 1 (ACR[7] = 1). followed by N two bytes read instruction on SDI line with reversed chain access sequence: the instruction byte + The non-volatile IVR stores the power up position of the wiper. dummy data byte for the last DCP in chain is going first, IVR is accessible when MSB bit at address 10000b is set to 0 followed by LOW to HIGH transition on CS line. The read (ACR[7] = 0). Writing a new value to the IVR register will set a instructions are executed during second part of read new power up position for the wiper. Also, writing to this sequence. It also starts by HIGH to LOW transition on CS line, register will load the same value into the corresponding WR as followed by N number of two bytes NOP instructions on SDI the IVR. Reading from the IVR will not change the WR, if its line and LOW to HIGH transition of CS. The data is read on contents are different. every even byte during second part of read sequence while Daisy Chain Configuration every odd byte contains instruction code + address from which the data is being read. When application needs more then one ISL22414, it can communicate with all of them without additional CS lines by Wiper Transition daisy chaining the DCPs as shown on Figure 18. In Daisy When stepping up through each tap in voltage divider mode, Chain configuration the SDO pin of previous chip is connected some tap transition points can result in noticeable voltage to SDI pin of the following chip, and each CS and SCK pins are transients, or overshoot/undershoot, resulting from the sudden connected to the corresponding microcontroller pins in parallel, transition from a very low impedance “make” to a much higher like regular SPI interface implementation. The Daisy Chain impedance “break within an extremely short period of time configuration can also be used for simultaneous setting of (<50ns). Two such code transitions are EFh to F0h, and 0Fh to multiple DCPs. Note, the number of daisy chained DCPs is 10h. Note, that all switching transients will settle well within the limited only by the driving capabilities of SCK and CS pins of settling time as stated in the datasheet. A small capacitor can microcontroller; for larger number of SPI devices buffering of be added externally to reduce the amplitude of these voltage SCK and CS lines is required. transients, but that will also reduce the useful bandwidth of the Daisy Chain Write Operation circuit, thus may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a The write operation starts by HIGH to LOW transition on CS signal chain for fast recovery. line, followed by N number of two bytes write instructions on SDI line with reversed chain access sequence: the instruction byte + data byte for the last DCP in chain is going first, as shown on Figure 19, where N is a number of DCPs in chain. The serial data is going through DCPs from DCP0 to DCP(N-1) FN6424 Rev 2.00 Page 14 of 17 September 21, 2015

ISL22414 N DCP IN A CHAIN CS SCK MOSI DCP0 DCP1 DCP2 DCP(N-1) MISO CS CS CS CS SCK SCK SCK SCK µC SDI SDO SDI SDO SDI SDO SDI SDO FIGURE 18. DAISY CHAIN CONFIGURATION CS SCK 16 CLKLS 16 CLKS 16 CLKS SDI WR D C P2 WR D C P1 WR D C P0 SDO 0 WR D C P2 WR D C P1 SDO 1 WR D C P2 SDO 2 FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDI INSTRUCTION ADDR DATA IN SDO DATA OUT FIGURE 20. TWO BYTE OPERATION FN6424 Rev 2.00 Page 15 of 17 September 21, 2015

ISL22414 CS SCK 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS SDI RD DCP2 RD DCP1 RD DCP0 NOP NOP NOP SDO DCP2 OUT DCP1 OUT DCP0 OUT FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 21, 2015 FN6424 Added Rev History beginning with Rev 2 Added About Intersil Verbiage Updated Ordering Information on page2 Updated POD M8.118 to most current version. Revision change is as follows: Updated to new POD template. Added land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2007-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6424 Rev 2.00 Page 16 of 17 September 21, 2015

ISL22414 Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN6424 Rev 2.00 Page 17 of 17 September 21, 2015