DATASHEET ISL22316 FN6186 Single Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power I2C™ Rev 3.00 August 14, 2015 Bus, 128 Taps The ISL22316 integrates a single digitally controlled Features potentiometer (DCP) and non-volatile memory on a • 128 resistor taps monolithic CMOS integrated circuit. • I2C serial interface The digitally controlled potentiometer is implemented with a - Two address pins, up to four devices/bus combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the • Non-volatile storage of wiper position I2C bus interface. The potentiometer has an associated • Wiper resistance: 70 typical @ VCC = 3.3V volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the • Shutdown mode user. The contents of the WR controls the position of the • Shutdown current 5µA max wiper. At power-up, the device recalls the contents of the DCP’s IVR to the WR. • Power supply: 2.7V to 5.5V • 50kor 10k total resistance The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of • High reliability applications including control, parameter adjustments, and - Endurance: 1,000,000 data changes per bit per register signal processing. - Register data retention: 50 years @ T  +55°C • 10 Ld MSOP or 10 Ld TDFN package • Pb-free (RoHS compliant) Pinouts ISL22316 ISL22316 (10 LD MSOP) (10 LD TDFN) TOP VIEW TOP VIEW SCL 1 10 VCC SCL 1 O 10 VCC SDA 2 9 RH SDA 2 9 RH A1 3 8 RW A1 3 8 RW A0 4 7 RL A0 4 7 RL SHDN 5 6 GND SHDN 5 6 GND Ordering Information PART NUMBER PART RESISTANCE OPTION TEMP. RANGE PACKAGE (Note) MARKING (k) (°C) (Pb-free) PKG. DWG. # ISL22316UFU10Z* 316UZ 50 -40 to +125 10 Ld MSOP M10.118 (No longer available, recommended replacement: (ISL22316WFRT10Z-TK) ISL22316WFU10Z* 316WZ 10 -40 to +125 10 Ld MSOP M10.118 ISL22316UFRT10Z* 316U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B (No longer available, recommended replacement: (ISL22316WFRT10Z-TK) ISL22316WFRT10Z* 316W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6186 Rev 3.00 Page 1 of 16 August 14, 2015

ISL22316 Block Diagram VCC SCL POWER-UP SDA INTERFACE, RH I2C CONTROL A0 INTERFACE AND A1 STATUS LOGIC WR RW RL NON-VOLATILE REGISTERS SHDN GND Pin Descriptions MSOP PIN TDFN PIN NUMBER NUMBER PIN NAME DESCRIPTION 1 1 SCL Open drain I2C interface clock input 2 2 SDA Open drain Serial data I/O for the I2C interface 3 3 A1 Device address input for the I2C interface 4 4 A0 Device address input for the I2C interface 5 5 SHDN Shutdown active low input 6 6 GND Device ground pin 7 7 RL “Low” terminal of DCP 8 8 RW “Wiper” terminal of DCP 9 9 RH “High” terminal of DCP 10 10 VCC Power supply pin FN6186 Rev 3.00 Page 2 of 16 August 14, 2015

ISL22316 Absolute Maximum Ratings Thermal Information Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Voltage at any Digital Interface Pin 10 Lead MSOP (Note 2). . . . . . . . . . . . 162 N/A with Respect to GND . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC+0.3 10 Lead TDFN (Notes 3, 4) . . . . . . . . . 74 7 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V Maximum Junction Temperature (Plastic Package). . . . . . . .+150°C Voltage at any DCP Pin with Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below Respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC http://www.intersil.com/pbfree/Pb-FreeReflow.asp IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 1) . . . . . . . . . . . . . . . . . .Class II, Level B @ +125°C Recommended Operating Conditions ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper Current of each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -1V for all pins. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. A nalog Specifications Over recommended operating conditions, unless otherwise stated. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note5) (Note 19) UNIT RTOTAL RH to RL Resistance W option 10 k U option 50 k RH to RL Resistance Tolerance -20 +20 % End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 18) U option ±80 ppm/°C (Note 18) RW Wiper Resistance VCC = 3.3V, wipercurrent=VCC/RTOTAL 70 200  VRH, VRL VRH and VRL Terminal Voltages VRH and VRL to GND 0 VCC V CH/CL/CW Potentiometer Capacitance 10/10/25 pF (Note 18) ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC 0.1 1 µA VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL Integral Non-linearity Monotonic over all tap positions, W and U -1 1 LSB (Note 10) option (Note 6) DNL Differential Non-linearity Monotonic over all tap positions, W and U -0.5 0.5 LSB (Note 9) option (Note 6) ZSerror Zero-scale Error W option 0 1 5 LSB (Note7) (Note 6) U option 0 0.5 2 FSerror Full-scale Error W option -5 -1 0 LSB (Note8) (Note 6) U option -2 -1 0 TCV Ratiometric Temperature Coefficient DCP register set to 40 hex for W and U ±4 ppm/°C (Notes11, 18) option FN6186 Rev 3.00 Page 3 of 16 August 14, 2015

ISL22316 Analog Specifications Over recommended operating conditions, unless otherwise stated. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note5) (Note 19) UNIT RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL Integral Non-linearity DCP register set between 10 hex and 7F -1 1 MI (Note15) hex; monotonic over all tap positions; (Note12) W and U option RDNL Differential Non-linearity W option -1 1 MI (Note14) (Note12) U option -0.5 0.5 MI (Note12) Roffset Offset W option 0 1 5 MI (Note13) (Note12) U option 0 0.5 2 MI (Note12) Operating Specifications Over the recommended operating conditions, unless otherwise specified. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note5) (Note 19) UNIT ICC1 VCC Supply Current (Volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C, 0.5 mA active, read and write states) ICC2 VCC Supply Current (Non-volatile Write/Read) fSCL = 400kHz; SDA = Open; (for I2C, 3 mA active, read and write states) ISB VCC Current (Standby) VCC = +5.5V @ +85°C, I2C interface in 5 µA standby state VCC = +5.5V @ +125°C, I2C interface in 7 µA standby state VCC = +3.6V @ +85°C, I2C interface in 3 µA standby state VCC = +3.6V @ +125°C, I2C interface in 5 µA standby state ISD VCC Current (Shutdown) VCC = +5.5V @ +85°C, I2C interface in 3 µA standby state VCC = +5.5V @ +125°C, I2C interface in 5 µA standby state VCC = +3.6V @ +85°C, I2C interface in 2 µA standby state VCC = +3.6V @ +125°C, I2C interface in 4 µA standby state ILkgDig Leakage Current, at Pins A0, A1, SHDN, Voltage at pin from GND to VCC, -1 1 µA SDA and SCL SDA is inactive tDCP DCP Wiper Response Time SCL falling edge of last bit of DCP data byte 1.5 µs (Note 18) to wiper new position tShdnRec DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper 1.5 µs (Note 18) stored position and RH connection SCL falling edge of last bit of ACR data byte 1.5 µs to wiper stored position and RH connection Vpor Power-on Recall Voltage Minimum VCC at which memory recall occurs 2.0 2.6 V VCCRamp VCC Ramp Rate 0.2 V/ms tD Power-up Delay VCC above Vpor, to DCP Initial Value 3 ms Register recall completed and I2C Interface in standby state FN6186 Rev 3.00 Page 4 of 16 August 14, 2015

ISL22316 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note5) (Note 19) UNIT EEPROM SPECIFICATION EEPROM Endurance 1,000,000 Cycles EEPROM Retention Temperature T  +55°C 50 Years tWC Non-volatile Write Cycle Time 12 20 ms (Note 17) SERIAL INTERFACE SPECIFICATIONS VIL A1, A0, SHDN, SDA, and SCL Input Buffer -0.3 0.3*VCC V LOW Voltage VIH A1, A0, SHDN, SDA, and SCL Input Buffer 0.7*VCC VCC + 0.3 V HIGH Voltage Hysteresis SDA and SCL Input Buffer Hysteresis 0.05*VCC V VOL SDA Output Buffer LOW Voltage, Sinking 0 0.4 V 4mA Cpin A1, A0, SHDN, SDA, and SCL Pin 10 pF (Note 18) Capacitance fSCL SCL Frequency 400 kHz tsp Pulse Width Suppression Time at SDA and Any pulse narrower than the max spec is 50 ns SCL Inputs suppressed tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VCC, until 900 ns SDA exits the 30% to 70% of VCC window tBUF Time the Bus Must be Free Before the Start SDA crossing 70% of VCC during a STOP 1300 ns of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition tLOW Clock LOW Time Measured at the 30% of VCC crossing 1300 ns tHIGH Clock HIGH Time Measured at the 70% of VCC crossing 600 ns tSU:STA START Condition Setup Time SCL rising edge to SDA falling edge; both 600 ns crossing 70% of VCC tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VCC 600 ns to SCL falling edge crossing 70% of VCC tSU:DAT Input Data Setup Time From SDA exiting the 30% to 70% of VCC 100 ns window, to SCL rising edge crossing 30% of VCC tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VCC 0 ns to SDA entering the 30% to 70% of VCC window tSU:STO STOP Condition Setup Time From SCL rising edge crossing 70% of VCC, 600 ns to SDA rising edge crossing 30% of VCC tHD:STO STOP Condition Hold Time for Read, or From SDA rising edge to SCL falling edge; 1300 ns Volatile Only Write both crossing 70% of VCC tDH Output Data Hold Time From SCL falling edge crossing 30% of 0 ns VCC, until SDA enters the 30% to 70% of VCC window tR SDA and SCL Rise Time From 30% to 70% of VCC 20 + 250 ns 0.1*Cb tF SDA and SCL Fall Time From 70% to 30% of VCC 20 + 250 ns 0.1*Cb Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF FN6186 Rev 3.00 Page 5 of 16 August 14, 2015

ISL22316 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note 19) (Note5) (Note 19) UNIT Rpu SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF 1 k For Cb = 400pF, max is about 2k~2.5k For Cb = 40pF, max is about 15k~20k tSU:A A1 and A0 Setup Time Before START condition 600 ns tHD:A A1 and A0 Hold Time After STOP condition 600 ns NOTES: 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127 11.TC = -------M-----a----x------V-------R-----W--------i-----–-----M-----i--n------V-------R-----W--------i---------------1---0----6-------- for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V MaxVRW+MinVRW2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature i i range. 12. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 13. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 14. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 127. 15. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127. 16. MaxRi–MinRi 106 for i = 16 to 127, T = -40°C to +125°C. Max() is the maximum value of the resistance and Min () is TC = ------------------------------------------------------------------------------------- R MaxRi+MinRi2 +165°C the minimum value of the resistance over the temperature range. 17. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 18. Limits should be considered typical and are not production tested. 19. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN6186 Rev 3.00 Page 6 of 16 August 14, 2015

ISL22316 SDA vs SCL Timing tF tHIGH tLOW tR tsp tHD:STO SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) A0 and A1 Pin Timing START STOP SCL CLK 1 SDA tSU:A tHD:A A0, A1 Typical Performance Curves 100 1.4 VCC = 3.3V, T = +125°C 90 1.2 ) 80 E ( 70 1.0 C N SITA 5600 µA) 0.8 T = +125°C R RESI 40 I (SB 0.6 E 30 0.4 P T = +25°C WI 20 VCC = 3.3V, T = +20°C VCC = 3.3V, T = -40°C 0.2 10 0 0 0 20 40 60 80 100 120 2.7 3.2 3.7 4.2 4.7 5.2 TAP POSITION (DECIMAL) VCC (V) FIGURE 1. WIPER RESISTANCE vs TAP POSITION FIGURE 2. STANDBY ICC vs VCC [ I(RW) = VCC/RTOTAL ] FOR 10k (W) FN6186 Rev 3.00 Page 7 of 16 August 14, 2015

ISL22316 Typical Performance Curves (Continued) 0.2 0.2 T = +25°C T = +25°C VCC = 2.7V 0.1 0.1 VCC = 2.7V SB) B) NL (L 0 L (LS 0 D N I -0.1 -0.1 VCC = 5.5V VCC = 5.5V -0.2 -0.2 0 20 40 60 80 100 120 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W) MODE FOR 10k (W) 1.3 0.0 10k 1.1 -0.3 0.9 VCC = 2.7V 50k VCC = 5.5V B) B) S 0.7 S L L -0.6 (ROR 0.5 VCC = 5.5V VCC = 2.7V (ROR R R -0.9 E 0.3 E S S Z Z 10k 0.1 -1.2 50k -0.1 -0.3 -1.5 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (ºC) FIGURE 5. ZSERROR vs TEMPERATURE FIGURE 6. FSERROR vs TEMPERATURE 0.4 0.4 T = +25°C T = +25°C 0.2 VCC = 5.5V 0.2 VCC = 5.5V B) 0 B) 0 S S DNL (L -0.2 INL (L-0.2 -0.4 -0.4 VCC = 2.7V VCC = 2.7V -0.6 -0.6 16 36 56 76 96 116 16 36 56 76 96 116 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W) 10k (W) FN6186 Rev 3.00 Page 8 of 16 August 14, 2015

ISL22316 Typical Performance Curves (Continued) 1.0 105 %) E ( 90 G N 0.5 A 75 H CAL VCC = 2.7V 50k m/°C) 60 D RTOT 0.0 VCC = 5.5V 10k Cv (pp 45 O EN -0.5 T 30 50k 10k T D 15 N E -1.0 0 -40 -20 0 20 40 60 80 100 120 16 36 56 76 96 TEMPERATURE (ºC) TAP POSITION (DECIMAL) FIGURE 9. END-TO-END RTOTAL % CHANGE vs FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm TEMPERATURE OUTPUT INPUT 300 250 C) 200 m/° p 150 p Cr ( 50k 10k T 100 50 WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5k 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME FN6186 Rev 3.00 Page 9 of 16 August 14, 2015

ISL22316 Pin Description maximum of four ISL22316 devices may occupy the I2C serial bus. Potentiometers Pins Principles of Operation RH AND RL The high (RH) and low (RL) terminals of the ISL22316 are The ISL22316 is an integrated circuit incorporating one DCP equivalent to the fixed terminals of a mechanical with its associated registers, non-volatile memory and an I2C potentiometer. RH and RL are referenced to the relative serial interface providing direct communication between a host position of the wiper and not the voltage potential on the and the potentiometer and memory. The resistor array is terminals. With WR set to 127 decimal, the wiper will be closest comprised of individual resistors connected in series. At either to RH, and with the WR set to 0, the wiper is closest to RL. end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. RW The electronic switches on the device operate in a “make RW is the wiper terminal and is equivalent to the movable before break” mode when the wiper changes tap positions. terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is SHDN restored, the contents of the IVR is recalled and loaded into the The SHDN pin forces the resistor to end-to-end open circuit WR to set the wiper to the initial value. condition on RH and shorts RW to RL. When SHDN is returned DCP Description to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically AND The DCP is implemented with a combination of resistor with the SHDN bit in the ACR register. The I2C interface is still elements and CMOS switches. The physical ends of each DCP available in shutdown mode and all registers are accessible. are equivalent to the fixed terminals of a mechanical This pin must remain HIGH for normal operation. potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the RH wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains RW all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal (RW) is RL closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between Bus Interface Pins RW and RL increases monotonically, while the resistance SERIAL DATA INPUT/OUTPUT (SDA) between RH and RW decreases monotonically. The SDA is a bidirectional serial data input/output pin for I2C While the ISL22316 is being powered up, the WR is reset to interface. It receives device address, operation code, wiper 40h (64 decimal), which locates RW roughly at the center address and data from an I2C external master device at the between RL and RH. After the power supply voltage becomes rising edge of the serial clock SCL, and it shifts out data after large enough for reliable non-volatile memory reading, the WR each falling edge of the serial clock. will be reload with the value stored in a non-volatile Initial Value Register (IVR). SDA requires an external pull-up resistor, since it is an open drain input/output. The WR and IVR can be read or written to directly using the I2C serial interface as described in the following sections. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL Memory Description requires an external pull-up resistor, since it is an open drain The ISL22316 contains one non-volatile 8-bit register, known as input. the Initial Value Register (IVR), and two volatile 8-bit registers, Wiper Register (WR) and Access Control Register (ACR). Table DEVICE ADDRESS (A1, A0) 1 shows the Memory map of the ISL22316. The non-volatile The address inputs are used to set the least significant 2 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22316. A FN6186 Rev 3.00 Page 10 of 16 August 14, 2015

ISL22316 register (IVR) at address 0, contain initial wiper position and All communication over the I2C interface is conducted by volatile registers (WR) contain current wiper position. sending the MSB of each byte of data first. TABLE 1. MEMORY MAP Protocol Conventions ADDRESS NON-VOLATILE VOLATILE Data states on the SDA line must change only during SCL 2 — ACR LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions 1 Reserved (seeFigure 16). On power-up of the ISL22316, the SDA pin is 0 IVR WR in the input mode. All I2C interface operations must begin with a START The non-volatile IVR and volatile WR registers are accessible condition, which is a HIGH to LOW transition of SDA while SCL with the same address. is HIGH. The ISL22316 continuously monitors the SDA and The Access Control Register (ACR) contains information and SCL lines for the START condition and does not respond to control bits described in Table 2. any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. The VOL bit (ACR<7>) determines whether the access is to wiper registers WR or initial value registers IVR. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL TABLE 2. ACCESS CONTROL REGISTER (ACR) is HIGH (see Figure 16). A STOP condition at the end of a read VOL SHDN WIP 0 0 0 0 0 operation, or at the end of a write operation places the device If VOL bit is 0, the non-volatile IVR register is accessible. If in its standby mode. VOL bit is 1, only the volatile WR is accessible. Note, value is An ACK, Acknowledge, is a software convention used to written to IVR register also is written to the WR. The default indicate a successful data transfer. The transmitting device, value of this bit is 0. either master or slave, releases the SDA bus after transmitting The SHDN bit (ACR<6>) disables or enables Shutdown mode. eight bits. During the ninth clock cycle, the receiver pulls the This bit is logically AND with SHDN pin. When this bit is 0, DCP is SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). in Shutdown mode. Default value of SHDN bit is 1. The ISL22316 responds with an ACK after recognition of a The WIP bit (ACR<5>) is read only bit. It indicates that START condition followed by a valid Identification Byte, and non-volatile write operation is in progress. It is impossible to once again after successful receipt of an Address Byte. The write to the WR or ACR while WIP bit is 1. ISL22316 also responds with an ACK after receiving a Data Shutdown Mode Byte of a write operation. The master must respond with an The device can be put in Shutdown mode either by pulling the ACK after receiving a Data Byte of a read operation SHDN pin to GND or setting the SHDN bit in the ACR register to A valid Identification Byte contains 01010 as the five MSBs, 0. The truth table for Shutdown mode is in Table 3. and the following two bits matching the logic values present at TABLE 3. pins A1 and A0. The LSB is the Read/Write bit. Its value is “1” for a Read operation, and “0” for a Write operation (seeTable SHDN pin SHDN bit Mode 4). High 1 Normal operation Low 1 Shutdown Logic values at pins A1 and A0 respectively High 0 Shutdown Low 0 Shutdown 0 1 0 1 0 A1 A0 R/W (MSB) (LSB) 2 I C Serial Interface TABLE 4. IDENTIFICATION BYTE FORMAT The ISL22316 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22316 operates as a slave device in all applications. FN6186 Rev 3.00 Page 11 of 16 August 14, 2015

ISL22316 SCL SDA START DATA DATA DATA STOP STABLE CHANGE STABLE FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE S SIGNALS FROM T S THE MASTER A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 0 1 0 1 0A1A00 0 0 0 00 SIGNALS FROM A A A THE SLAVE C C C K K K FIGURE 18. BYTE WRITE SEQUENCE S S SIGNALS T T S FROM THE A IDENTIFICATION A IDENTIFICATION A A A T MASTER R BYTE WITH ADDRESS R BYTE WITH C C C O T R/W = 0 BYTE T R/W = 1 K K K P SIGNAL AT SDA 0 1 0 1 0A1A00 0 0 0 0 0 1 0 1 0A1A01 A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 19. READ SEQUENCE FN6186 Rev 3.00 Page 12 of 16 August 14, 2015

ISL22316 Write Operation Read Operation A Write operation requires a START condition, followed by a A Read operation consists of a three byte instruction followed valid Identification Byte, a valid Address Byte, a Data Byte, and by one or more Data Bytes (See Figure 19). The master a STOP condition. After each of the three bytes, the ISL22316 initiates the operation issuing the following sequence: a responds with an ACK. At this time, the device enters its START, the Identification byte with the R/W bit set to “0”, an standby state (see Figure 18). Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, The non-volatile write cycle starts after STOP condition is the ISL22316 responds with an ACK. Then the ISL22316 determined and it requires up to 20ms delay for the next non- transmits Data Bytes as long as the master responds with an volatile write. ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and STOP condition) following the last bit of the last Data Byte (see Figure 19). In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. FN6186 Rev 3.00 Page 13 of 16 August 14, 2015

ISL22316 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE August 14, 2015 FN6186.3 - Ordering Information Table on page1. - Added Revision History beginning with Rev 1. - Added About Intersil Verbiage. -Updated L10.3x3B to most recent revision, changes are as follows: -Revision 0 to Revision 1 Changes: Removed from JEDEC format to comply with new standards. Changes include: Removed table and put dimensions on package outline drawing instead Added Typical Recommended Land Pattern Note "Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip." changed to "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. -Revision 1 to Revision 2 changes: 1. Removed mention of "b" from Note 4 since "b" does not exist on the drawing. 2. Added Note 6 callout to lead width on "Bottom View" 3. Corrected the word "indentifier" in Note 6 to read "identifier" -Revision 2 to Revision 3 changes: Removed package outline and included center to center distance between lands on recommended land pattern. Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly. -Revision 3 to Revision 4 Tiebar Note updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends -Updated POD M10.118 to most current version change is as follows: Added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2006-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6186 Rev 3.00 Page 14 of 16 August 14, 2015

ISL22316 Package Outline Drawing L10.3x3B 10 LEAD THIN DUAL FLAT PACKAGE (TDFN) WITH E-PAD Rev 4, 4/15 5 3.00 A PIN #1 INDEX AREA B 10 1 5 5 1 2 PIN 1 0. INDEX AREA 3.00 8 +0.1/ - 0.50 3 2. 0.25 +0.05/ - 0.07 6 (4X) 0.15 1.64 +0.1/ -0.15 10x 0.40 +/- 0.1 TOP VIEW BOTTOM VIEW (10x0.60) SEE DETAIL "X" (10X0.25) 0.10C 5 7 0. SEATING PLANE C 0.08C 0.05 8 3 2. SIDE VIEW (8x 0.50) 1.64 2.80 TYP TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 4 0.05 DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN6186 Rev 3.00 Page 15 of 16 August 14, 2015

ISL22316 Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 PIN# 1 ID 0.95 REF 1 2 0.50 BSC B GAUGE TOP VIEW PLANE 0.25 3°±3° 0.55 ± 0.15 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08MCA-BD 0.10 ± 0.05 0.10C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. (0.50) 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.29) 5. Dimensions are measured at Datum Plane "H". (1.40) 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN6186 Rev 3.00 Page 16 of 16 August 14, 2015