DATASHEET ISL12026, ISL12026A FN8231 Real Time Clock/Calendar with I2C Bus™ and EEPROM Rev 9.00 November 30, 2010 The ISL12026 and the ISL12026A devices are micro power Features real time clocks with timing and crystal compensation, • Real Time Clock/Calendar clock/calender, power-fail indicator, two periodic or polled alarms, intelligent battery backup switching, and integrated - Tracks Time in Hours, Minutes and Seconds 512x8-bit EEPROM configured in 16 Bytes per page. - Day of the Week, Day, Month and Year - 3 Selectable Frequency Outputs The oscillator uses an external, low-cost 32.768kHz crystal. The real time clock tracks time with separate registers for • Two Non-Volatile Alarms hours, minutes, and seconds. The device has calendar - Settable on the Second, Minute, Hour, Day of the Week, registers for date, month, year and day of the week. The Day or Month calendar is accurate through 2099, with automatic leap year - Repeat Mode (Periodic Interrupts) correction. • Automatic Backup to Battery or SuperCap The ISL12026 and ISL12026A have different types of Power • On-Chip Oscillator Compensation Control Settings. The ISL12026 uses the Legacy Mode - Internal Feedback Resistor and Compensation Setting, which follows conditions set in X1226 products. The Capacitors ISL12026A uses the Standard Mode Setting. Please refer to - 64 Position Digitally Controlled Trim Capacitor “Power Control Operation” on page13 for more details. Also, - 6 Digital Frequency Adjustment Settings to ±30ppm please refer to “I2C Communications During Battery Backup” on page22 for important details. • 512x8 Bits of EEPROM - 16-Byte Page Write Mode (32 total pages) Pinouts - 8 Modes of BlockLock™ Protection ISL12026, ISL12026A - Single Byte Write Capability (8 LD SOIC) • High Reliability TOP VIEW - Data Retention: 50 years X1 1 8 VDD - Endurance: >2,000,000 Cycles Per Byte X2 2 7 VBAT • I2C Interface IRQ/FOUT 3 6 SCL - 400kHz Data Transfer Rate GND 4 5 SDA • 800nA Battery Supply Current • Package Options ISL12026, ISL12026A - 8 Ld SOIC and 8 Ld TSSOP Packages (8 LD TSSOP) • Pb-Free (RoHS Compliant) TOP VIEW VBAT 1 8 SCL Applications VDD 2 7 SDA • Utility Meters X1 3 6 GND X2 4 5 IRQ/FOUT • HVAC Equipment • Audio/Video Components • Set-Top Box/Television • Modems • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Fixed Broadband Wireless Equipment • Pagers/PDA • POS Equipment • Test Meters/Fixtures • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive FN8231 Rev 9.00 Page 1 of 24 November 30, 2010

ISL12026, ISL12026A Ordering Information PART NUMBER PART VBAT TRIP POINT BSW BIT DEFAULT TEMP RANGE PACKAGE PKG. (Notes 1, 2, 3) MARKING (V) SETTING (°C) (Pb-Free) DWG. # ISL12026IBZ 12026 IBZ VDD < VBAT BSW = 1 -40 to +85 8 Ld SOIC M8.15 ISL12026IVZ 2026 IVZ VDD < VBAT BSW = 1 -40 to +85 8 Ld TSSOP M8.173 ISL12026AIBZ 12026A IBZ 2.2 BSW = 0 -40 to +85 8 Ld SOIC M8.15 ISL12026AIVZ 2026A IVZ 2.2 BSW = 0 -40 to +85 8 Ld TSSOP M8.173 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12026, ISL12026A. For more information on MSL please see techbrief TB363. Block Diagram OSC COMPENSATION 32.768kHz X1 OSCILLATOR FREQUENCY 1Hz CATLIEMNEDRAR KETEIMPIENG BSAWTITTECRHY VDD X2 DIVIDER LOGIC REGISTERS CIRCUITRY VBAT (SRAM) IRQ/FOUT SELECT SCL SERIAL CDOENCTORDOEL RCEOGNISTTREORLS/ RESGTIASTTUESRS ALARM COMPARE SDA INDTEECROFDAECRE LOGIC (EEPROM) (SRAM) SK ALARM REGS A (EEPROM) M 8 4k EEPROM ARRAY Pin Descriptions PIN NUMBER SOIC TSSOP SYMBOL DESCRIPTION 1 3 X1 The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source (see “Application Section” on page19.) 2 4 X2 The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal (see “Application Section” on page19.) 3 5 IRQ/FOUT Interrupt Output/Frequency Output is a multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the control register. This output is an open drain configuration. 4 6 GND Ground. 5 7 SDA Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 6 8 SCL The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). 7 1 VBAT This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. 8 2 VDD Power Supply. FN8231 Rev 9.00 Page 2 of 24 November 30, 2010

ISL12026, ISL12026A Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT, SCL, SDA, and IRQ/FOUT Pins Thermal Resistance (Typical) JA (°C/W) JC (°C/W) (respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 8 Ld SOIC Package (Notes 5, 6) . . . . . 115 50 Voltage on X1 and X2 Pins 8 Ld TSSOP Package (Notes 5, 6) . . . 140 48 (respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Latchup (Note 4) . . . . . . . . . . . . . . . . . . .Class II, Level B @ +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below ESD Rating http://www.intersil.com/pbfree/Pb-FreeReflow.asp Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±2kV Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: Using a max positive pulse of 8.35V on all pins except X1 and X2, Using a max positive pulse of 2.75V on X1 and X2, and using a max negative pulse of -1V for all pins. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the “case temp” location is taken at the package top center. DC Electrical Specifications Unless otherwise noted, VDD = +2.7V to +5.5V, TA = -40°C to +85°C, Typical values are @ TA = +25°C and VDD = 3.3V. MIN MAX SYMBOL PARAMETER CONDITIONS (Note 16) TYP (Note 16) UNIT NOTES VDD Main Power Supply 2.7 5.5 V VBAT Backup Power Supply 1.8 5.5 V Electrical Specifications MIN MAX SYMBOL PARAMETER CONDITIONS (Note 16) TYP (Note 16) UNIT NOTES IDD1 Supply Current with I2C Active VDD = 2.7V 500 µA 7, 8, 9 VDD = 5.5V 800 µA IDD2 Supply Current for Non-Volatile VDD = 2.7V 2.5 mA 7, 8, 9 Programming VDD = 5.5V 3.5 mA IDD3 Supply Current for Main VDD = VSDA = VSCL = 2.7V 10 µA 9 Timekeeping (Low Power Mode) VDD = VSDA = VSCL = 5.5V 20 µA IBAT Battery Supply Current VBAT = 1.8V, 800 1000 nA 7, 10, 11 VDD = VSDA = VSCL = VRESET = 0 VBAT = 3.0V, 850 1200 nA VDD = VSDA = VSCL = VRESET = 0 IBATLKG Battery Input Leakage VDD = 5.5V, VBAT = 1.8V 100 nA VTRIP VBAT Mode Threshold 1.8 2.2 2.6 V 11 VTRIPHYS VTRIP Hysteresis 30 mV 11, 14 VBATHYS VBAT Hysteresis 50 mV 11, 14 VDD SR- VDD Negative Slew Rate 10 V/ms 12 IRQ/FOUT VOL Output Low Voltage VDD = 5V 0.4 V IOL = 3mA VDD = 1.8V 0.4 V IOL = 1mA ILO Output Leakage Current VDD = 5.5V 100 400 nA VOUT = 5.5V FN8231 Rev 9.00 Page 3 of 24 November 30, 2010

ISL12026, ISL12026A EEPROM Specifications MIN MAX PARAMETER TEST CONDITIONS (Note 16) TYP (Note 16) UNITS NOTES EEPROM Endurance >2,000,000 Cycles EEPROM Retention Temperature 75°C 50 Years Serial Interface (I2C) Specifications DC Electrical Specifications MIN MAX SYMBOL PARAMETER TEST CONDITIONS (Note 16) TYP (Note 16) UNITS NOTES VIL SDA and SCL Input Buffer LOW -0.3 0.3xVDD V Voltage VIH SDA and SCL Input Buffer HIGH 0.7 x VDD VDD + 0.3 V Voltage Hysteresis SDA and SCL Input Buffer 0.05 x VDD V Hysteresis VOL SDA Output Buffer LOW Voltage IOL = 4mA 0 0.4 V ILI Input Leakage Current on SCL VIN = 5.5V 100 nA ILO I/O Leakage Current on SDA VIN = 5.5V 100 nA AC Electrical Specifications MIN MAX SYMBOL PARAMETER TEST CONDITIONS (Note 16) TYP (Note 16) UNITS NOTES fSCL SCL Frequency 400 kHz tIN Pulse width Suppression Time at Any pulse narrower than the max 50 ns SDA and SCL Inputs spec is suppressed. tAA SCL Falling Edge to SDA Output SCL falling edge crossing 30% of 900 ns Data Valid VDD, until SDA exits the 30% to 70% of VDD window. tBUF Time the Bus Must be Free Before SDA crossing 70% of VDD during a 1300 ns the Start of a New Transmission STOP condition, to SDA crossing 70% of VDD during the following START condition. tLOW Clock LOW Time Measured at the 30% of VDD 1300 ns crossing. tHIGH Clock HIGH Time Measured at the 70% of VDD 600 ns crossing. tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge. 600 ns Both crossing 70% of VDD. tHD:STA START Condition Hold Time From SDA falling edge crossing 600 ns 30% of VDD to SCL falling edge crossing 70% of VDD. tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of 100 ns VDD window, to SCL rising edge crossing 30% of VDD. tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% 0 ns of VDD to SDA entering the 30% to 70% of VDD window. FN8231 Rev 9.00 Page 4 of 24 November 30, 2010

ISL12026, ISL12026A AC Electrical Specifications (Continued) MIN MAX SYMBOL PARAMETER TEST CONDITIONS (Note 16) TYP (Note 16) UNITS NOTES tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% 600 ns of VDD, to SDA rising edge crossing 30% of VDD. tHD:STO STOP Condition Hold Time for From SDA rising edge to SCL falling 600 ns Read or Volatile Only Write edge. Both crossing 70% of VDD. tDH Output Data Hold Time From SCL falling edge crossing 30% 0 ns of VDD, until SDA enters the 30% to 70% of VDD window. Cpin SDA and SCL Pin Capacitance 10 pF tWC Non-volatile Write Cycle Time 12 20 ms 14 tR SDA and SCL Rise Time From 30% to 70% of VDD 20 + 0.1xCb 300 ns tF SDA and SCL Fall Time From 70% to 30% of VDD 20 +0.1xCb 300 ns 15 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 15 RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF. 1 k 15 Off-chip For Cb = 400pF, max is about 2k~2.5k. For Cb = 40pF, max is about 15k~20k NOTES: 7. IRQ/FOUT Inactive. 8. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz 9. VDD > VBAT +VBATHYS 10. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT 1.8V 11. Specified at +25°C. 12. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 13. Parameter is not 100% tested. 14. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, it is the time from valid STOP condition at the end of Write sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. 15. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Timing Diagrams Bus Timing tF tHIGH tLOW tR tHD:STO SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) FN8231 Rev 9.00 Page 5 of 24 November 30, 2010

ISL12026, ISL12026A Write Cycle Timing SCL SDA 8TH BIT OF LAST BYTE ACK tWC STOP START CONDITION CONDITION Typical Performance Curves Temperature is +25°C unless otherwise specified. 4.0 0.9 BSW = 0 OR 1 0.8 3.5 0.7 3.0 SCL, SDA PULL-UPS = 0V SCL, SDA PULL-UPS = 0V 0.6 BSW = 0 OR 1 2.5 A) A) 0.5 µ µ (AT 2.0 (AT 0.4 B B I 1.5 I 0.3 1.0 SCL, SDA PULL-UPS = VBAT 0.2 0.5 BSW = 0 OR 1 0.1 0.0 0.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VBAT (V) VBAT (V) FIGURE 1. IBAT vs VBAT, SBIB = 0 FIGURE 2. IBAT vs VBAT, SBIB = 1 5.0 1.4 4.5 1.2 4.0 VDD = 5.5V VBAT = 3.0V 3.5 1.0 A) 3.0 VDD = 3.3V A) 0.8 µ µ (D 2.5 (T D A 0.6 I 2.0 B I 1.5 0.4 1.0 0.2 0.5 0.0 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. IDD3 vs TEMPERATURE FIGURE 4. IBAT vs TEMPERATURE FN8231 Rev 9.00 Page 6 of 24 November 30, 2010

ISL12026, ISL12026A Typical Performance Curves (Continued)Temperature is +25°C unless otherwise specified. 4.5 80 4.0 0 60 3.5 R = T 3.0 A 40 M (µA)D 22..05 E FRO 20 D G I N 1.5 A 0 H C 1.0 M P -20 0.5 P 0.0 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 -32-28-24-20-16-12 -8 -4 0 4 8 12 16 20 24 28 VDD (V) ATR SETTING FIGURE 5. IDD3 vs VDD FIGURE 6. FOUT vs ATR SETTING Description Pin Descriptions The ISL12026 device is a Real Time Clock with clock/calendar, Serial Clock (SCL) two polled alarms with integrated 512x8 EEPROM, oscillator The SCL input is used to clock all data into and out of the device. compensation and battery backup switch. The input buffer on this pin is always active (not gated). The pull- The oscillator uses an external, low-cost 32.768kHz crystal. All up resistor on this pin must use the same voltage source as compensation and trim components are integrated on the chip. V . DD This eliminates several external discrete components and a Serial Data (SDA) trim capacitor, saving board area and component cost. SDA is a bidirectional pin used to transfer data into and out of The Real Time Clock keeps track of time with separate the device. It has an open drain output and may be wire ORed registers for Hours, Minutes and Seconds. The Calendar has with other open drain or open collector outputs. The input separate registers for Date, Month, Year and Day-of-week. The buffer is always active (not gated). calendar is correct through 2099, with automatic leap year correction. This open drain output requires the use of a pull-up resistor. The pull-up resistor on this pin must use the same voltage source as The Dual Alarms can be set to any Clock/Calendar value for a V . The output circuitry controls the fall time of the output DD match. For instance, every minute, every Tuesday, or 5:23 AM signal with the use of a slope controlled pull-down. The circuit is on March 21. The alarms can be polled in the Status Register designed to comply with 400kHz I2C interface speed. or can provide a hardware interrupt (IRQ/F Pin). There is a OUT V pulse mode for the alarms allowing for repetitive alarm BAT functionality. This input provides a backup supply voltage to the device. V supplies power to the device in the event the V supply The IRQ/F pin may be software selected to provide a BAT DD OUT fails. This pin can be connected to a battery, a SuperCap or frequency output of 1Hz, 4096Hz, or 32,768Hz or inactive. tied to ground if not used. The device offers a backup power input pin. This VBAT pin IRQ/F (Interrupt Output/Frequency Output) allows the device to be backed up by battery or SuperCap. The OUT entire ISL12026 device is fully operational from 2.7V to 5.5V This dual function pin can be used as an interrupt or frequency and the clock/calendar portion of the ISL12026 device remains output pin. The IRQ/FOUT mode is selected via the frequency fully operational down to 1.8V (Standby Mode). out control bits of the INT register. The ISL12026 device provides 4k bits of EEPROM with 8 • Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has modes of BlockLock™ control. The BlockLock™ allows a safe, occurred and requests action. It is an open drain active low secure memory for critical user and configuration data, while output. allowing a large user storage area. • Frequency Output Mode. The pin outputs a clock signal which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open drain output. FN8231 Rev 9.00 Page 7 of 24 November 30, 2010

ISL12026, ISL12026A X1, X2 register write is in progress and the RTC continues to run during any non-volatile write sequences. The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is Accuracy of the Real Time Clock used with the ISL12026 to supply a timebase for the real time The accuracy of the Real Time Clock depends on the accuracy clock. Internal compensation circuitry provides high accuracy of the quartz crystal that is used as the time base for the RTC. over the operating temperature range from -40°Cto +85°C. Since the resonant frequency of a crystal is temperature This oscillator compensation network can be used to calibrate dependent, the RTC performance will also be dependent upon the crystal timing accuracy over-temperature either during temperature. The frequency deviation of the crystal is a manufacturing or with an external temperature sensor and function of the turnover temperature of the crystal from the microcontroller for active compensation. X2 is intended to drive crystal’s nominal frequency. For example, a >20ppm frequency a crystal only, and should not drive any external circuit. deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation X1 X2 networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information, see “Application FIGURE 7. RECOMMENDED CRYSTAL CONNECTION Section” on page19. Real Time Clock Operation Clock/Control Registers (CCR) The Real Time Clock (RTC) uses an external 32.768kHz The Control/Clock Registers are located in an area separate quartz crystal to maintain an accurate internal representation of from the EEPROM array and are only accessible following a the second, minute, hour, day, date, month and year. The RTC slave byte of “1101111x” and reads or writes to addresses has leap-year correction. The clock also corrects for months [0000h:003Fh]. The clock/control memory map has memory having fewer than 31 days and has a bit that controls 24 hour addresses from 0000h to 003Fh. The defined addresses are or AM/PM format. When the ISL12026 powers up after the loss described in the Table 1. Writing to and reading from the of both VDD and VBAT, the clock will not operate until at least undefined addresses are not recommended. one byte is written to the clock register. CCR Access Reading the Real Time Clock The contents of the CCR can be modified by performing a byte The RTC is read by initiating a Read command and specifying or a page write operation directly to any address in the CCR. the address corresponding to the register of the Real Time Prior to writing to the CCR (except the status register), Clock. The RTC Registers can then be read in a Sequential however, the WEL and RWEL bits must be set using a three Read Mode. Since the clock runs continuously and a read takes step process (see “Writing to the Clock/Control Registers” on a finite amount of time, there is the possibility that the clock page12). could change during the course of a read operation. In this The CCR is divided into 5 sections. These are: device, the time is latched by the read command (falling edge of the clock on the ACK bit prior to RTC data output) into a 1. Alarm 0 (8 bytes; non-volatile) separate latch to avoid time changes during the read operation. 2. Alarm 1 (8 bytes; non-volatile) The clock continues to run. Alarms occurring during a read are 3. Control (5 bytes; non-volatile) unaffected by the read operation. 4. Real Time Clock (8 bytes; volatile) Writing to the Real Time Clock 5. Status (1 byte; volatile) The time and date may be set by writing to the RTC registers. Each register is read and written through buffers. The RTC Register should be written ONLY with Page Write. To non-volatile portion (or the counter portion of the RTC) is avoid changing the current time by an incomplete write updated only if RWEL is set and only after a valid write operation operation, write to the all 8 bytes in one write operation. When and stop bit. A sequential read or page write operation provides writing the RTC registers, the new time value is loaded into a access to the contents of only one section of the CCR per separate buffer at the falling edge of the clock during the operation. Access to another section requires a new operation. Acknowledge. This new RTC value is loaded into the RTC A read or write can begin at any address in the CCR. Register by a stop bit at the end of a valid write sequence. An invalid write operation aborts the time update procedure and It is not necessary to set the RWEL bit prior to writing the the contents of the buffer are discarded. After a valid write status register. See “Status Register (SR)” on page9. supports operation, the RTC will reflect the newly loaded data beginning a single byte read or write only. Continued reads or writes from with the next “one second” clock cycle after the stop bit is this section terminates the operation. written. The RTC continues to update the time while an RTC FN8231 Rev 9.00 Page 8 of 24 November 30, 2010

ISL12026, ISL12026A The state of the CCR can be read by performing a random AL1, AL0: Alarm Bits - Volatile read at any address in the CCR at any time. This returns the These bits announce if either alarm 0 or alarm 1 match the real contents of that register location. Additional registers are read time clock. If there is a match, the respective bit is set to ‘1’. by performing a sequential read. The read instruction latches The falling edge of the last data bit in a SR Read operation all Clock registers into a buffer, so an update of the clock does resets the flags. Note: Only the AL bits that are set when an SR not change the time being read. A sequential read of the CCR read starts will be reset. An alarm bit that is set by an alarm will not result in the output of data from the memory array. At occurring during an SR read operation will remain set after the the end of a read, the master supplies a stop condition to end read operation is complete. the operation and free the bus. After a read of the CCR, the OSCF: Oscillator Fail Indicator address remains at the previous address +1 so the user can execute a current address read of the CCR and continue This bit is set to “1” if the oscillator is not operating, or is reading the next Register. operating, but has clock jitter which does not affect the accuracy of RTC counting. The bit is set to “0” if the oscillator is Real Time Clock Registers functioning, and does not have clock jitter. This bit is read only, and is set/reset by hardware. SC, MN, HR, DT, MO, YR: Clock/Calendar Registers These registers depict BCD representations of the time. As RWEL: Register Write Enable Latch - Volatile such, SC (Seconds) and MN (Minutes) range from 00 to 59, This bit is a volatile latch that powers up in the LOW (disabled) HR (Hour) is 1 to 12 with an AM or PM indicator (H21 bit) or 0 state. The RWEL bit must be set to “1” prior to any writes to the to 23 (with MIL = 1), DT (Date) is 1 to 31, MO (Month) is 1 to Clock/Control Registers. Writes to RWEL bit do not cause a 12, YR (Year) is 0 to 99. non-volatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the DW: Day of the Week Register CCR requires both the RWEL and WEL bits to be set in a This register provides a Day of the Week status and uses three specific sequence. bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The WEL: Write Enable Latch - Volatile assignment of a numerical value to a specific day of the week The WEL bit controls the access to the CCR during a write is arbitrary and may be decided by the system software operation. This bit is a volatile latch that powers up in the LOW designer. The default value is defined as ‘0’. (disabled) state. While the WEL bit is LOW, writes to the CCR address will be ignored, although acknowledgment is still issued. 24 Hour Time The WEL bit is set by writing a “1” to the WEL bit and zeroes to If the MIL bit of the HR register is 1, the RTC uses a 24-hour the other bits of the Status Register. Once set, WEL remains set format. If the MIL bit is 0, the RTC uses a 12-hour format and H21 until either reset to 0 (by writing a “0” to the WEL bit and zeroes bit functions as an AM/PM indicator with a ‘1’ representing PM. to the other bits of the Status Register) or until the part powers The clock defaults to standard time with H21 = 0. up again. Writes to WEL bit do not cause a non-volatile write Leap Years cycle, so the device is ready for the next operation immediately after the stop condition. Leap years add the day February 29 and are defined as those years that are divisible by 4. RTCF: Real Time Clock Fail Bit - Volatile This bit is set to a “1” after a total power failure. This is a read Status Register (SR) only bit that is set by hardware (ISL12026 internally) when the The Status Register is located in the CCR memory map at device powers up after having lost all power to the device (both address 003Fh. This is a volatile register only and is used to V and V go to 0V). The bit is set regardless of whether DD BAT control the WEL and RWEL write enable latches, read power V or V is applied first. The loss of only one of the DD BAT status and two alarm bits. This register is separate from both supplies does not set the RTCF bit to “1”. On power-up after a the array and the Clock/Control Registers (CCR). total power failure, all registers are set to their default states TABLE 1. STATUS REGISTER (SR) and the clock will not increment until at least one byte is written to the clock register. The first valid write to the RTC section ADDR 7 6 5 4 3 2 1 0 after a complete power failure resets the RTCF bit to “0” 003Fh BAT AL1 AL0 OSCF 0 RWEL WEL RTCF (writing one byte is sufficient). Default 0 0 0 0 0 0 0 1 Unused Bits BAT: Battery Supply - Volatile Bit 3 in the SR is not used, but must be zero. The Data Byte This bit set to “1” indicates that the device is operating from output during a SR read will contain a zero in this bit location. V , not V . It is a read-only bit and is set/reset by hardware BAT DD (ISL12026 internally). Once the device begins operating from V , the device sets this bit to “0”. DD FN8231 Rev 9.00 Page 9 of 24 November 30, 2010

ISL12026, ISL12026A TABLE 2. CLOCK/CONTROL MEMORY MAP ADDR. TYPE REG NAME 7 6 5 4 BIT 3 2 1 0 RANGE ISL12026DEFAULT ISL12026ADEFAULT 003F Status SR BAT AL1 AL0 OSCF 0 RWEL WEL RTCF 01h 01h 0037 RTC Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h 20h (SRAM) 0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h 00h 0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h 00h 0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 01h 01h 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h 00h 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h 00h 0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h 00h 0014 Control PWR SBIB BSW 0 0 0 0 0 0 40h 00h (EEPROM) 0013 DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h 00h 0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h 00h 0011 INT IM AL1E AL0E FO1 FO0 0 0 0 00h 00h 0010 BL BP2 BP1 BP0 0 0 0 0 0 00h 00h 000F Alarm1 Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h 20h (EEPROM) 000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion 000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h 00h 000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h 00h 000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h 00h 0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h 00h 0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h 00h 0007 Alarm0 Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h 20h (EEPROM) 0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h 00h 0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion 0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h 00h 0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h 00h 0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h 00h 0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h 00h 0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h 00h Alarm Registers (Non-Volatile) See “Device Operation” on page12 and “Application Section” on page19 for more information. Alarm0 and Alarm1 Control Registers (Non-Volatile) The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as The Control Bits and Registers described in the following are an enable bit (enable = “1”). These enable bits specify which non-volatile. alarm registers (seconds, minutes, etc.) are used to make the BL Register comparison. Note that there is no alarm byte for year. BP2, BP1, BP0 - Block Protect Bits The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the The Block Protect Bits, BP2, BP1 and BP0, determine which alarm will be triggered once a match occurs between the alarm blocks of the array are write protected. A write to a protected block registers and the RTC registers. Any one alarm register, of memory is ignored. The block protect bits will prevent write multiple registers, or all registers can be enabled for a match. operations to one of eight segments of the array. The partitions are described in Table 3. FN8231 Rev 9.00 Page 10 of 24 November 30, 2010

ISL12026, ISL12026A TABLE 3. Oscillator Compensation Registers 2 1 0 PROTECTED ADDRESSES There are two trimming options. P P P B B B ISL12026 ARRAY LOCK • ATR. Analog Trimming Register 0 0 0 None (Default) None • DTR. Digital Trimming Register 0 0 1 180h – 1FFh Upper 1/4 These registers are non-volatile. The combination of analog 0 1 0 100h – 1FFh Upper 1/2 and digital trimming can give up to -64 to +110 ppm of total 0 1 1 000h – 1FFh Full Array adjustment. 1 0 0 000h – 03Fh First 4 Pages ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1, 1 0 1 000h – 07Fh First 8 Pages ATR0: Analog Trimming Register 1 1 0 000h – 0FFh First 16 Pages 6 analog trimming bits, ATR0 to ATR5, are provided in order to adjust the on-chip load capacitance value for frequency 1 1 1 000h – 1FFh Full Array compensation of the RTC. Each bit has a different weight for INT Register: Interrupt Control and capacitance adjustment. For example, using a Citizen CFS- 206 crystal with different ATR bit combinations provides an Frequency Output Register estimated ppm adjustment range from -34 to +80ppm to the IM, AL1E, AL0E - Interrupt Control and Status Bits nominal frequency compensation. There are two Interrupt Control bits, Alarm 1 Interrupt Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically enable or disable the alarm interrupt signal output X1 (IRQ/F ). The interrupts are enabled when either the AL1E OUT or AL0E or both bits are set to ‘1’ and both the FO1 and FO0 CX1 CRYSTAL bits are set to 0 (FOUT disabled). OSCILLATOR X2 The IM bit enables the pulsed interrupt mode. To enter this mode, the AL0E or AL1E bits are set to “1”, and the IM bit to “1”. CX2 The IRQ/F output will now be pulsed each time an alarm OUT occurs. This means that once the interrupt mode alarm is set, it will continue to alarm for each occurring match of the alarm and present time. This mode is convenient for hourly or daily FIGURE 8. DIAGRAM OF ATR hardware interrupts in microcontroller applications such as security cameras or utility meter reading. The effective on-chip series load capacitance, C , ranges LOAD from 4.5pF to 20.25pF with a mid-scale value of 12.5pF In the case that both Alarm 0 and Alarm 1 are enabled, the (default). C is changed via two digitally controlled IRQ/F pin will be pulsed each time either alarm matches LOAD OUT capacitors, C and C , connected from the X1 and X2 pins the RTC (both alarms can provide hardware interrupt). If the IM X1 X2 to ground (see Figure 8). The value of C and C is given by bit is also set to "1", the IRQ/F will be pulsed for each of the X1 X2 OUT Equation 1: alarms as well. FO1, FO0 - Programmable Frequency Output Bits CX = 16b5+8b4+4b3+2b2+1b1+0.5b0+9pF (EQ. 1) These are two output control bits. They select one of three divisions of the internal oscillator, that is applied to the The effective series load capacitance is the combination of CX1 IRQ/FOUT output pin. Table 4 shows the selection bits for this and CX2: output. When using this function, the Alarm output function is 1 C = ----------------------------------- disabled. LOAD -----1------+-----1------ C C  X1 X2 TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS FO1 FO0 OUTPUT FREQUENCY C = 1---6--------b---5----+-----8-------b---4-----+----4-------b----3----+----2--------b---2----+----1--------b---1----+-----0---.-5-------b----0----+----9--pF LOAD  2  (EQ. 2) 0 0 Alarm output (FOUT disabled) 0 1 32.768kHz For example, C (ATR = 00000) = 12.5pF, C LOAD LOAD 1 0 4096Hz (ATR = 100000) = 4.5pF, and CLOAD(ATR = 011111) = 20.25pF. The entire range for the series combination of load capacitance 1 1 1Hz goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these are typical values. FN8231 Rev 9.00 Page 11 of 24 November 30, 2010

ISL12026, ISL12026A DTR Register - DTR2, DTR1, DTR0: Digital Trimming Device Operation Register Writing to the Clock/Control Registers The digital trimming Bits DTR2, DTR1 and DTR0 adjust the Changing any of the bits of the clock/control registers requires number of counts per second and average the ppm error to the following steps: achieve better accuracy. 1. Write a 02h to the Status Register to set the Write Enable DTR2 is a sign bit. DTR2 = 0 means frequency compensation Latch (WEL). This is a volatile operation, so there is no is > 0. DTR2 = 1 means frequency compensation is < 0. delay after the write (operation preceded by a start and DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm ended with a stop). adjustment and DTR0 gives 20 ppm adjustment. 2. Write a 06h to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a A range from -30ppm to +30ppm can be represented by using volatile cycle. The zeros in the data byte are required the three DTR bits. (operation proceeded by a start and ended with a stop). TABLE 5. DIGITAL TRIMMING REGISTERS Write all 8 bytes to the RTC registers, or one byte to the SR, or DTR REGISTER one to five bytes to the control registers. This sequence starts ESTIMATED FREQUENCY with a start bit, requires a slave byte of “11011110” and an DTR2 DTR1 DTR0 PPM address within the CCR and is terminated by a stop bit. A write 0 0 0 0 to the EEPROM registers in the CCR will initiate a non-volatile 0 1 0 +10 write cycle and will take up to 20ms to complete. A write to the RTC registers (SRAM) will require much shorter cycle time (t = 0 0 1 +20 t ). Writes to undefined areas have no effect. The RWEL bit BUF 0 1 1 +30 is reset by the completion of a write to the CCR, so the 1 0 0 0 sequence must be repeated to again initiate another change to the CCR contents. If the sequence is not completed for any 1 1 0 -10 reason (by sending an incorrect number of bits or sending a 1 0 1 -20 start instead of a stop, for example), the RWEL bit is not reset 1 1 1 -30 and the device remains in an active mode. Writing all zeros to the status register resets both the WEL and RWEL bits. A read PWR Register: SBIB, BSW operation occurring between any of the previous operations will not interrupt the register write operation. SBIB: - Serial Bus Interface (Enable) Alarm Operation The serial bus can be disabled in battery backup mode by setting this bit to “1”. This will minimize power drain on the Since the alarm works as a comparison between the alarm battery. The Serial Interface can be enabled in battery backup registers and the RTC registers, it is ideal for notifying a host mode by setting this bit to “0”. (default is “0”). See “BSW: processor of a particular time event, which triggers some Power Control Bit” on page12. action as a result. The host can be notified by either a hardware interrupt (the IRQ/F pin) or by polling the Status OUT BSW: Power Control Bit Register (SR) Alarm bits. These two volatile bits (AL1for Alarm The Power Control bit, BSW, determines the conditions for 1 and AL0 for Alarm 0), indicate if an alarm has happened. The switching between V and Backup Battery. There are two bits are set on an alarm condition regardless of whether the DD options. IRQ/F interrupt is enabled. The AL1 and AL0 bits in the OUT status register are reset by the falling edge of the eighth clock Option 1. Standard Mode: Set “BSW = 0” of status register read. Option 2. Legacy Mode: Set “BSW = 1” There are two alarm operation modes: Single Event and See “Power Control Operation” on page13 for more details. periodic Interrupt Mode: Also see “I2C Communications During Battery Backup” on 1. Single Event Mode is enabled by setting the AL0E or AL1E page22 for important details. bit to “1”, the IM bit to “0”, and disabling the frequency TABLE 6. VBAT TRIP POINT WITH DIFFERENT BSW SETTING output. This mode permits a one-time match between the alarm registers and the RTC registers. Once this match VBAT TRIP POINT occurs, the AL0 or AL1 bit is set to “1” and the IRQ/FOUT BSW BIT (V) POWER CONTROL SETTING output will be pulled low and will remain low until the AL0 or 0 2.2 Standard Mode (ISL12026A) AL1 bit is read, which will automatically resets it. Both Alarm registers can be set at the same time to trigger alarms. The 1 VDD < VBAT Legacy Mode (ISL12026) IRQ/F output will be set by either alarm, and will need OUT to be cleared to enable triggering by a subsequent alarm. Polling the SR will reveal which alarm has been set. FN8231 Rev 9.00 Page 12 of 24 November 30, 2010

ISL12026, ISL12026A 2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is If the Alarm1 is used, SCA1 would need to have the correct enabled by setting the AL0E or AL1E bit to “1” the IM bit to data written. “1”, and disabling the frequency output. If both AL0E and Power Control Operation AL1E bits are set to "1", then both AL0E and AL1E PIM alarms will function. The IRQ/FOUT output will now be The power control circuit accepts a VDD and a VBAT input. pulsed each time each of the alarms occurs. This means Many types of batteries can be used with Intersil RTC that once the interrupt mode alarm is set, it will continue to products. For example, 3.0V or 3.6V Lithium batteries are alarm for each occurring match of the alarm and present appropriate, and battery sizes are available that can power an time. This mode is convenient for hourly or daily hardware Intersil RTC device for up to 10 years. Another option is to use interrupts in microcontroller applications such as security a SuperCap for applications where V is interrupted for up to DD cameras or utility meter reading. Interrupt Mode CANNOT a month. See “Application Section” on page19 for more be used for general periodic alarms, however, since a information. specific time period cannot be programmed for interrupt, only matches to a specific time of day. The interrupt mode There are two options for setting the change-over conditions is only stopped by disabling the IM bit or the Alarm Enable from V to Battery backup mode. The BSW bit in the PWR DD bits. register controls this operation: Writing to the Alarm Registers • Option 1 - Standard Mode (ISL12026A Default) The Alarm Registers are non-volatile but require special attention • Option 2 - Legacy Mode (ISL12026 Default) to insure a proper non-volatile write takes place. Specifically, byte writes to individual registers are good for all but registers 0006h Note that the I2C bus may or may not be operational during and 0000Eh, which are the DWA0 and DWA1 registers, battery backup. That function is controlled by the SBIB bit. That respectively. Those registers will require a special page write for operation is covered after the power control section. non-volatile storage. The recommended page write sequences OPTION 1- STANDARD POWER CONTROL MODE are as follows: (ISL12026A DEFAULT) 1. 16-byte page writes: The best way to write or update the In the Standard mode, the supply will switch over to the battery Alarm Registers is to perform a 16-byte write beginning at when VDD drops below VTRIP or VBAT, whichever is lower. In address 0001h (MNA0) and wrapping around and ending at this mode, accidental operation from the battery is prevented address 0000h (SCA0). This will insure that non-volatile storage takes place. This means that the code must be since the battery backup input will only be used when the VDD supply is shut off. designed so that the Alarm0 data is written starting with Minutes register, and then all the Alarm1 data, with the last To select Option 1, BSW bit in the Power Register must be set byte being the Alarm0 Seconds (the page ends at the to “BSW = 0”. A description of power switchover follows. Alarm1 Y2k register and then wraps around to address 0000h). Standard Mode Power Switchover Alternatively, the 16-byte page write could start with • Normal Operating Mode (V ) to Battery Backup Mode DD address 0009h, wrap around and finish with address (V ) BAT 0008h. Note that any page write ending at address 0007h To transition from the V to V mode, both of the following or 000Fh (the highest byte in each Alarm) will not trigger a DD BAT conditions must be met: non-volatile write, so wrapping around or overlapping to the following Alarm's Seconds register is advised. - Condition 1: V < V - V 2. Other non-volatile writes: It is possible to do writes of less DD BAT BATHYS where V  50mV than an entire page, but the final byte must always be BATHYS - Condition 2: addresses 0000h through 0004h or 0008h though 000Ch to V < V trigger a non-volatile write. Writing to those blocks of DD TRIP where V  2.2V 5bytes sequentially, or individually, will trigger a TRIP non-volatile write. If the DWA0 or DWA1 registers need to • Battery Backup Mode (V ) to Normal Mode (V ) BAT DD be set, then enough bytes will need to be written to overlap with the other Alarm register and trigger the non-volatile The ISL12026 device will switch from the VBAT to VDD mode write. For Example, if the DWA0 register is being set, then when one of the following conditions occurs: the code can start with a multiple byte write beginning at - Condition 1: address 0006h, and then write 3 bytes ending with the V > V + V SCA1 register as follows: DD BAT BATHYS where V  50mV BATHYS Addr Name - Condition 2: 0006h DWA0 V > V + V DD TRIP TRIPHYS 0007h Y2K0 where V  30mV TRIPHYS 0008h SCA1 FN8231 Rev 9.00 Page 13 of 24 November 30, 2010

ISL12026, ISL12026A There are two discrete situations that are possible when using The Legacy Mode power control conditions are illustrated in Standard Mode: VBAT < VTRIP and VBAT > VTRIP. These two Figure 11. power control situations are illustrated in Figures 9 and 10. VDD VOLTAGE BATTERY BACKUP ON VDD MODE VBAT In Off VTRIP 2.2V VBAT 1.8V FIGURE 11. BATTERY SWITCHOVER IN LEGACY MODE VBAT - VBATHYS VBAT + VBATHYS Serial Communication FIGURE 9. BATTERY SWITCHOVER WHEN VBAT < VTRIP The device supports the I2C protocol. Clock and Data Data states on the SDA line can change only during SCL LOW. BATTERY BACKUP SDA state changes during SCL HIGH are reserved for MODE indicating start and stop conditions (see Figure 12). VDD Start Condition VBAT 3.0V All commands are preceded by the start condition, which is a VTRIP 2.2V HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the VTRIP VTRIP + VTRIPHYS start condition and will not respond to any command until this condition has been met (see Figure 13). FIGURE 10. BATTERY SWITCHOVER WHEN VBAT > VTRIP Stop Condition OPTION 2 -LEGACY POWER CONTROL MODE (ISL12026 All communications must be terminated by a stop condition, DEFAULT) which is a LOW to HIGH transition of SDA when SCL is HIGH. The Legacy Mode follows conditions set in X1226 products. In The stop condition is also used to place the device into the this mode, switching from V to V is simply done by Standby power mode after a read sequence. A stop condition DD BAT comparing the voltages and the device operates from whichever can only be issued after the transmitting device has released is the higher voltage. Care should be taken when changing from the bus (see Figure 13). Normal to Legacy Mode. If the V voltage is higher than V , BAT DD Acknowledge then the device will enter battery back up and unless the battery Acknowledge is a software convention used to indicate is disconnected or the voltage decreases, the device will no successful data transfer. The transmitting device, either master longer operate from V . DD or slave, will release the bus after transmitting 8 bits. During To select the Option 2, BSW bit in the Power Register must be the ninth clock cycle, the receiver will pull the SDA line LOW to set to “BSW = 1” acknowledge that it received the 8 bits of data (see Figure 14). • Normal Mode (VDD) to Battery Backup Mode (VBAT) The device will respond with an acknowledge after recognition To transition from the V to V mode, the following of a start condition and if the correct Device Identifier and DD BAT conditions must be met: Select bits are contained in the Slave Address Byte. If a write operation is selected, the device will respond with an V < V - V DD BAT BATHYS acknowledge after the receipt of each subsequent 8-bit word. • Battery Backup Mode (V ) to Normal Mode (V ) The device will not acknowledge if the slave address byte is BAT DD incorrect. The device will switch from the V to V mode when the BAT DD following condition occurs: V > V +V DD BAT BATHYS FN8231 Rev 9.00 Page 14 of 24 November 30, 2010

ISL12026, ISL12026A SCL SDA DATA STABLE DATA CHANGE DATA STABLE FIGURE 12. VALID DATA CHANGES ON THE SDA BUS SCL SDA START STOP FIGURE 13. VALID START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 DATA OUTPUT FROMTRANSMITTER DATA OUTPUT FROMRECEIVER START ACKNOWLEDGE FIGURE 14. ACKNOWLEDGE RESPONSE FROM RECEIVER In the read mode, the device will transmit 8 bits of data, release Bit 3 through Bit 1 of the slave byte specifies the device select the SDA line, then monitor the line for an acknowledge. If an bits. These are set to ‘111’. acknowledge is detected and no stop condition is generated by The last bit of the Slave Address Byte defines the operation to the master, the device will continue to transmit data. The be performed. When this R/W bit is a one, then a read device will terminate further data transmissions if an operation is selected. A zero selects a write operation acknowledge is not detected. The master must then issue a (see Figure 15). stop condition to return the device to Standby mode and place the device into a known state. After loading the entire Slave Address Byte from the SDA bus, the ISL12026 compares the device identifier and device select Device Addressing bits with ‘1010111’ or ‘1101111’. Upon a correct compare, the Following a start condition, the master must output a Slave device outputs an acknowledge on the SDA line. Address Byte. The first 4 bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM array. Slave bits ‘1101’ access the CCR. When shipped from the factory, EEPROM array is UNDEFINED, and should be programmed by the customer to a known state. FN8231 Rev 9.00 Page 15 of 24 November 30, 2010

ISL12026, ISL12026A DEVICE IDENTIFIER ARRAY 1 0 1 0 SLAVE ADDRESS BYTE 1 1 0 1 1 1 1 R/W BYTE 0 CCR WORD ADDRESS 1 0 0 0 0 0 0 0 A8 BYTE 1 WORD ADDRESS 0 A7 A6 A5 A4 A3 A2 A1 A0 BYTE 2 DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 BYTE 3 FIGURE 15. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES (16 BYTE PAGES) S SIGNALS FROM T S THE MASTER A T R SLAVE WORD WORD O T ADDRESS ADDRESS 1 ADDRESS 0 DATA P SDA BUS 1 1 110 0000000 A A A A SIGNALS FROM C C C C THE SLAVE K K K K FIGURE 16. BYTE WRITE SEQUENCE Following the Slave Byte is a two byte word address. The word address bytes the ISL12026 awaits the 8 bits of data. After address is either supplied by the master device or obtained receiving the 8 data bits, the ISL12026 again responds with an from an internal counter. On power up the internal address acknowledge. The master then terminates the transfer by counter is set to address 0h, so a current address read of the generating a stop condition. The ISL12026 then begins an EEPROM array starts at address 0. When required, as part of internal write cycle of the data to the non-volatile memory. a random read, the master must supply the 2 Word Address During the internal write cycle, the device inputs are disabled, Bytes as shown in Figure 15. so the device will not respond to any requests from the master. The SDA output is at high impedance (see Figure 16). In a random read operation, the slave byte in the “dummy write” portion must match the slave byte in the “read” section. A write to a protected block of memory is ignored, but will still That is if the random read is from the array the slave byte must receive an acknowledge. At the end of the write command, the be 1010111x in both instances. Similarly, for a random read of ISL12026 will not initiate an internal write cycle, and will the Clock/Control Registers, the slave byte must be 1101111x continue to ACK commands. in both places. Byte writes to all of the non-volatile registers are allowed, Write Operations except the DWAn registers which require multiple byte writes or page writes to trigger non-volatile writes. See “Device Byte Write Operation” on page12 for more information. For a write operation, the device requires the Slave Address Page Write Byte and the Word Address Bytes. This gives the master The ISL12026 has a page write operation. It is initiated in the access to any one of the words in the array or CCR. (Note: same manner as the byte write operation; but instead of Prior to writing to the CCR, the master must write a 02h, then terminating the write cycle after the first data byte is 06h to the status register in two preceding operations to enable transferred, the master can transmit up to 15 more bytes to the the write operation. See “Writing to the Clock/Control memory array and up to 7 more bytes to the clock/control Registers” on page12). Upon receipt of each address byte, the registers. The RTC registers require a page write (8 bytes), ISL12026 responds with an acknowledge. After receiving both individual register writes are not allowed. (Note: Prior to writing FN8231 Rev 9.00 Page 16 of 24 November 30, 2010

ISL12026, ISL12026A to the CCR, the master must write a 02h, then 06h to the status bytes in a page, then the previously loaded data is over-written register in two preceding operations to enable the write by the new data, one byte at a time. Refer to Figure 18. The operation. See “Writing to the Clock/Control Registers” on master terminates the Data Byte loading by issuing a stop page12). condition, which causes the ISL12026 to begin the non-volatile write cycle. As with the byte write operation, all inputs are After the receipt of each byte, the ISL12026 responds with an disabled until completion of the internal write cycle. Refer to acknowledge, and the address is internally incremented by Figure 17 for the address, acknowledge, and data transfer one. The address pointer remains at the last address byte sequence. written. When the counter reaches the end of the page, it “rolls over” and goes back to the first address on the same page. Stops and Write Modes This means that the master can write 16 bytes to a memory Stop conditions that terminate write operations must be sent by array page or 8 bytes to a CCR section starting at any location the master after sending at least 1 full data byte and it’s on that page. For example, if the master begins writing at associated ACK signal. If a stop is issued in the middle of a location 10 of the memory and loads 15 bytes, then the first 6 data byte, or before 1 full data byte + ACK is sent, then the bytes are written to addresses 10 through 15, and the last 6 ISL12026 resets itself without performing the write. The bytes are written to columns 0 through 5. Afterwards, the contents of the array are not affected. address counter would point to location 6 on the page that was just written. If the master supplies more than the maximum 1  N  16 FOR EEPROM ARRAY S 1  N  8 FOR CCR SIGNALS FROM AT S THEMASTER R SLAVE WORD WORD DATA DATA T T ADDRESS ADDRESS 1 ADDRESS 0 (1) (n) OP SDA BUS 1 1 1 1 0 0 0 0 00 0 0 A A A A SIGNALS FROM C C C C THESLAVE K K K K FIGURE 17. PAGE WRITE SEQUENCE 6 BYTES 6 BYTES ADDRESS = 5 ADDRESS ADDRESS ADDRESS POINTER ENDS 10 15 AT ADDR = 5 FIGURE 18. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10 FN8231 Rev 9.00 Page 17 of 24 November 30, 2010

ISL12026, ISL12026A Acknowledge Polling In a similar operation called “Set Current Address,” the device sets the address if a stop is issued instead of the second start Disabling of the inputs during non-volatile write cycles can be shown in Figure 21. The ISL12026 then goes into standby used to take advantage of the 12ms (typ) write cycle time. mode after the stop and all bus activity will be ignored until a Once the stop condition is issued to indicate the end of the master’s byte load operation, the ISL12026 initiates the start is detected. This operation loads the new address into the internal non-volatile write cycle. Acknowledge polling can address counter. The next Current Address Read operation will begin immediately. To do this, the master issues a start read from the newly loaded address. This operation could be condition followed by the Memory Array Slave Address Byte for useful if the master knows the next address it needs to read, a write or read operation (AEh or AFh). If the ISL12026 is still but is not ready for the data. busy with the non-volatile write cycle then no ACK will be S returned. When the ISL12026 has completed the write T S operation, an ACK is returned and the host can proceed with SIGNALS FROM A SLAVE T THEMASTER R ADDRESS O the read or write operation. Refer to the flow chart in Figure20. T P Note: Do not use the CCR Slave byte (DEh or DFh) for Acknowledge Polling. SDA BUS 1 1 1 1 1 Read Operations A There are three basic read operations: Current Address Read, SIGNTAHLESS FLRAOVME CK DATA Random Read and Sequential Read. Current Address Read FIGURE 19. CURRENT ADDRESS READ SEQUENCE Internally the ISL12026 contains an address counter that maintains the address of the last word read incremented by BYTE LOAD one. Therefore, if the last read was to address n, the next read COMPLETED BY ISSUING STOP. operation would access data from address n + 1. On power-up, ENTER ACK POLLING the 16-bit address is initialized to 00h. In this way, a current address read immediately after the power on reset can download the entire contents of memory starting at the first ISSUE START location. Upon receipt of the Slave Address Byte with the R/W bit set to one, the ISL12026 issues an acknowledge, then transmits 8 data bits. The master terminates the read operation ISSUE MEMORY ARRAY SLAVE by not responding with an acknowledge during the ninth clock ADDRESS BYTE ISSUE STOP AFH (READ) OR AEH (WRITE) and issuing a stop condition. Refer to Figure 19 for the address, acknowledge, and data transfer sequence. NO It should be noted that the ninth clock cycle of the read ACK operation is not a “don’t care.” To terminate a read operation, RETURNED? the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then YES issue a stop condition. NO NON-VOLATILE WRITE Random Read CYCLE COMPLETE. CONTINUE ISSUE STOP COMMAND SEQUENCE? Random read operations allow the master to access any location in the ISL12026. Prior to issuing the Slave Address YES Byte with the R/W bit set to zero, the master must first perform a “dummy” write operation. CONTINUE NORMAL READ OR The master issues the start condition and the slave address WRITE COMMAND byte, receives an acknowledge, then issues the word address SEQUENCE bytes. After acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the R/W bit set to one. This is followed PROCEED by an acknowledge from the device and then by the 8-bit data word. The master terminates the read operation by not responding with an acknowledge and then issuing a stop FIGURE 20. ACKNOWLEDGE POLLING SEQUENCE condition. Refer to Figure 21 for the address, acknowledge and data transfer sequence. FN8231 Rev 9.00 Page 18 of 24 November 30, 2010

ISL12026, ISL12026A S S SIGTNHAELMSA FSRTOEMR ART ADSDLARVEES S ADWDROERSDS 1 ADWDROERSDS 0 ART ADSDLARVEES S OST T T P SDA BUS 1 1 11 0 0000000 1 1 1 11 A A A A SIGNALS FROM C C C C K K K K DATA THE SLAVE FIGURE 21. RANDOM ADDRESS READ SEQUENCE S SIGNALS FROM SLAVE A A A T THEMASTER ADDRESS C C C O K K K P SDA BUS 1 SIGNALS FROM A THESLAVE C DATA DATA DATA DATA K (1) (2) (n-1) (n) (n is any integer greater than 1) FIGURE 22. SEQUENTIAL READ SEQUENCE Sequential Read The Intersil RTC family uses an oscillator circuit with on-chip crystal compensation network, including adjustable Sequential reads can be initiated as either a current address load-capacitance. The only external component required is the read or random address read. The first data byte is transmitted crystal. The compensation network is optimized for operation as with the other modes; however, the master now responds with certain crystal parameters which are common in many of with an acknowledge, indicating it requires additional data. The the surface mount or tuning-fork crystals available today. Table device continues to output data for each acknowledge received. 7 summarizes these parameters. The master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. TABLE 7. CRYSTAL PARAMETERS REQUIRED FOR INTERSIL RTCs The data output is sequential, with the data from address n followed by the data from address n + 1. The address counter PARAMETER MIN TYP MAX UNITS NOTES for read operations increments through all page and column Frequency 32.768 kHz addresses, allowing the entire memory contents to be serially Frequency ±100 ppm Down to 20ppm read during one operation. At the end of the address space, Tolerance if desired the counter “rolls over” to the start of the address space, and the ISL12026 continues to output data for each acknowledge Turnover 20 25 30 °C Typically the value Temperature used for most received. Refer to Figure 22 for the acknowledge and data crystals transfer sequence. Operating Temp -40 85 °C Application Section Range Parallel Load 12.5 pF Crystal Oscillator and Temperature Compensation Capacitance Intersil has now integrated the oscillator compensation circuity Equivalent 50 k For best oscillator on-chip, to eliminate the need for external components and Series performance adjust for crystal drift over temperature and enable very high Resistance accuracy time keeping (<5ppm drift). Table 8 contains some crystal manufacturers and part numbers that meet the requirements for the Intersil RTC products. FN8231 Rev 9.00 Page 19 of 24 November 30, 2010

ISL12026, ISL12026A TABLE 8. CRYSTAL MANUFACTURERS Layout Considerations TEMP +25°C FREQ. The crystal input at X1 has a very high impedance and will pick PART RANGE TOLERANCE up high frequency signals from other circuits on the board. MANUFACTURER NUMBER (°C) (ppm) Since the X2 pin is tied to the other side of the crystal, it is also Citizen CM201, CM202, CM200S -40 to +85 ±20ppm a sensitive node. These signals can couple into the oscillator circuit and produce double clocking or mis-clocking, seriously Epson MC-405, MC-406 -40 to +85 ±20ppm affecting the accuracy of the RTC. Care needs to be taken in Raltron RSM-200S-A or B -40 to +85 ±20ppm layout of the RTC circuit to avoid noise pickup. In Figure 23 is a SaRonix 32S12A or B -40 to +85 ±20ppm suggested layout for the ISL12026 or ISL12027 devices in 8 Ld SO package. Ecliptek ECPSM29T-32.768K -10 to +60 ±20ppm ECS ECX-306/ECX-306I -10 to +60 ±20ppm Fox FSM-327 -40 to +85 ±20ppm The turnover temperature in Table 7 describes the temperature where the apex of the of the drift vs temperature curve occurs. This curve is parabolic with the drift increasing as (T - T0)2. For an Epson MC-405 device, for example, the turnover temperature is typically +25°C, and a peak drift of >110ppm U1 occurs at the temperature extremes of -40°C and +85°C. It is R5 possible to address this variable drift by adjusting the load capacitance of the crystal, which will result in predictable X1 change to the crystal frequency. The Intersil RTC family allows this adjustment over temperature since the devices include on- 47k chip load capacitor trimming. This control is handled by the Analog Trimming Register, or ATR, which has 6-bits of control. The load capacitance range covered by the ATR circuit is approximately 3.25pF to 18.75pF, in 0.25pF increments. Note FIGURE 23. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8 that actual capacitance would also include about 2pF of package related capacitance. In-circuit tests with commercially The X1 and X2 connections to the crystal are to be kept as available crystals demonstrate that this range of capacitance short as possible. A thick ground trace around the crystal is allows frequency control from +80ppm to -34ppm, using a advised to minimize noise intrusion, but ground near the X1 12.5pF load crystal. and X2 pins should be avoided as it will add to the load In addition to the analog compensation afforded by the capacitance at those pins. Keep in mind these guidelines for adjustable load capacitance, a digital compensation feature is other PCB layers in the vicinity of the RTC device. A small available for the Intersil RTC family. There are 3-bits known as decoupling capacitor at the VDD pin of the chip is mandatory, the Digital Trimming Register or DTR, and they operate by with a solid connection to ground. adding or skipping pulses in the clock signal. The range The ISL12026 product has a special consideration. The provided is ±30ppm in increments of 10ppm. The default IRQ/F - pin on the 8 Ld SOIC package is located next to the OUT setting is 0ppm. The DTR control can be used for coarse X2 pin. When this pin is used as a frequency output (IRQ/ adjustments of frequency drift over-temperature or for crystal F ) and is set to 32.768kHz, noise can couple to the X1 or OUT initial accuracy correction. X2 pins and cause double-clocking. The layout in Figure 23 A final application for the ATR control is in-circuit calibration for minimizes this by running the IRQ/FOUT output away from the high accuracy applications, along with a temperature sensor X1 and X2 pins. Also, reducing the switching current at this pin chip. Once the RTC circuit is powered up with battery backup, by careful selection of the pull-up resistor value will reduce the IRQ/F output is set at 32.768kHz and frequency drift is noise. Intersil suggests a minimum value of 5.1k for OUT measured. The ATR control is then adjusted to a setting which 32.768kHz, and higher values (up to 20k) for lower frequency minimizes drift. Once adjusted at a particular temperature, it is IRQ/FOUT outputs. possible to adjust at other discrete temperatures for minimal For other RTC products, the same rules previously stated overall drift, and store the resulting settings in the EEPROM. should be observed, but slightly adjusted since the Extremely low overall temperature drift is possible with this packages and pinouts are different. method. The Intersil evaluation board contains the circuitry necessary to implement this control. Oscillator Measurements When a proper crystal is selected and the layout guidelines above are observed, the oscillator should start-up in most FN8231 Rev 9.00 Page 20 of 24 November 30, 2010

ISL12026, ISL12026A circuits in less than one second. Some circuits may take slightly longer, but start-up should definitely occur in less than 5 seconds. When testing RTC circuits, the most common impulse is to apply a scope probe to the circuit at the X2 pin 2.7V TO 5.5V VDD VBAT SUPERCAP (oscillator output) and observe the waveform. DO NOT DO THIS! Although in some cases you may see a usable VSS waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful information in that waveform other than the fact that the circuit FIGURE 24. SUPERCAPACITOR CHARGING CIRCUIT is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be Alarm Operation Examples affected by the parasitic elements in the scope probe. Applying Following are examples of both Single Event and periodic a scope probe can possibly cause a faulty oscillator to start up, Interrupt Mode alarms. hiding other issues (although in the Intersil RTCs, the internal EXAMPLE 1 circuitry assures start-up when using the proper crystal and layout). Alarm 0 set with single interrupt (IM = ”0”) The best way to analyze the RTC circuit is to power it up and A single alarm will occur on January 1 at 11:30am. read the real time clock as time advances, or if the chip has the A. Set Alarm 0 registers as follows: IRQ/F output, look at the output of that pin on an OUT oscilloscope (after enabling it with the control register, and BIT ALARM0 using a pull-up resistor for an open-drain output). Alternatively, REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION the ISL12026 device has an IRQ/F output, which can be OUT SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled checked by setting an alarm for each minute. Using the pulse interrupt mode setting, the once-per-minute interrupt functions MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, as an indication of proper oscillation. enabled Backup Battery Operation HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, enabled Many types of batteries can be used with the Intersil RTC DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, products. 3.0V or 3.6V Lithium batteries are appropriate, and enabled sizes are available that can power a Intersil RTC device for up to 10 years. Another option is to use a SuperCap for MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled applications where V may disappear intermittently for short DD periods of time. Depending on the value of SuperCap used, DWA0 0 0 0 0 0 0 0 0 00h Day of week backup time can last from a few days to two weeks (with >1F). disabled A simple silicon or Schottky barrier diode can be used in series with V to charge the SuperCap, which is connected to the B. Also the AL0E bit must be set as follows: DD V pin. Try to use Schottky diodes with very low leakages, BAT <1µA desirable. Do not use the diode to charge a battery BIT CONTROL (especially lithium batteries!) REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION There are two possible modes for battery backup operation; INT 0 0 1 0 0 0 0 0 x0h Enable Alarm Standard and Legacy mode. In Standard mode, there are no operational concerns when switching over to battery backup After these registers are set, an alarm will be generated when the since all other devices functions are disabled. Battery drain is RTC advances to exactly 11:30am on January 1 (after seconds minimal in Standard mode, and return to Normal VDD powered changes from 59 to 00) by setting the AL0 bit in the status register operations is predictable. In Legacy mode, the VBAT pin can to “1” and also bringing the IRQ/FOUT output low. power the chip if the voltage is above V and less than V . DD TRIP EXAMPLE 2 In this mode, it is possible to generate the alarm and communicate with the device, unless SBI = 1, but the supply Pulsed interrupt once per minute (IM = ”1”) current drain is much higher than the Standard mode and Interrupts at one minute intervals when the seconds register is backup time is reduced. In this case, if alarms are used in at 30 seconds. backup mode, the IRQ/F pull-up resistor must be OUT connected to V voltage source. A. Set Alarm 0 registers as follows: BAT B. Set the Interrupt register as follows: FN8231 Rev 9.00 Page 21 of 24 November 30, 2010

ISL12026, ISL12026A • Mode A - In this mode, selection bits indicate a Standard BIT ALARM0 Mode switchover combined with I2C operation in battery REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION backup mode. When the V voltage drops below the lower DD of V or V , then the device will enter battery backup SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, TRIP BAT mode. If the microcontroller and bus pull-ups are also enabled powered by the battery, then the ISL12026 can communicate MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled in battery backup mode. HRA0 0 0 0 0 0 0 0 0 00h Hours disabled • Mode B - In this mode, selection bits indicate Legacy mode DTA0 0 0 0 0 0 0 0 0 00h Date disabled switchover combined with I2C operation in battery backup mode. When the V voltage drops below V , the device MOA0 0 0 0 0 0 0 0 0 00h Month disabled DD BAT will enter battery backup mode. If the microcontroller and bus DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled pull-ups are also powered by the battery, then the ISL12026 can communicate in battery backup mode. This mode places the ISL12026 device in the same operating mode as the BIT CONTROL X1226 legacy device. REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION • Mode C - This mode combines Standard mode battery INT 1 0 1 0 0 0 0 0 x0h Enable Alarm and Int switchover with no I2C operation in battery backup mode. Mode When the V voltage drops below the lower of V or DD TRIP V , then the device will enter battery backup mode and the BAT Once the registers are set, the following waveform will be seen I2C interface will be disabled, minimizing V current drain. BAT at IRQ/F : OUT • Mode D - This mode combines Legacy mode battery RTC AND ALARM REGISTERS ARE BOTH “30” SEC switchover with no I2C operation in battery backup mode. When the V voltage drops below V , the device will DD BAT enter battery backup mode and the I2C interface will be disabled, minimizing V current drain. BAT Note that the IRQ/F open drain output pin is active in OUT battery backup for all modes, allowing clocking of devices while 60s in battery backup mode. The pull-up on the pin will need to go Note that the status register AL0 bit will be set each time the to V , and thus battery mode current draw will increase BAT alarm is triggered, but does not need to be read or cleared. accordingly. I2C Communications During Battery Backup Operation in Battery Backup mode is affected by the BSW and SBIB bits as described earlier. These bits allow flexible operation of the serial bus and EEPROM in battery backup mode, but certain operational details need to be clear before utilizing the different modes. Table 9 describes 4 different modes possible with using the BSW and SBIB bits, and how they are affect the serial interface and battery backup operation. TABLE 9. VBAT I2C ACTIVE IN EE PROM WRITE/ SWITCHOVER BATTERY READ IN BATTERY FREQ/IRQ MODE SBIB BIT BSW BIT VOLTAGE BACKUP? BACKUP? ACTIVE? NOTES A 0 0 Standard Mode, Yes NO YES, needs VBAT switchover at lower of VBAT or VTRIP = 2.2V typ pull-up to VBAT VTRIP. Pull-ups needed on I2C to VBAT to operate in Battery Backup. B (X1226 0 1 Legacy Mode, Yes NO YES, needs VBAT switchover at <VDD. Pull-ups Mode) VDD < VBAT pull-up to VBAT needed on I2C to VBAT to operate in Battery Backup. C 1 0 Standard Mode, NO NO YES, needs VBAT switchover at lower of VBAT or VTRIP = 2.2V typ pull-up to VBAT VTRIP. D 1 1 Legacy Mode, NO NO YES, needs VBAT switchover at <VDD. VDD < VBAT pull-up to VBAT FN8231 Rev 9.00 Page 22 of 24 November 30, 2010

ISL12026, ISL12026A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - 1 2 3 L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0075 0.0098 0.19 0.25 - -A- D 0.1890 0.1968 4.80 5.00 3 D A h x 45° E 0.1497 0.1574 3.80 4.00 4 -C- e 0.050 BSC 1.27 BSC -  H 0.2284 0.2440 5.80 6.20 - e A1 C h 0.0099 0.0196 0.25 0.50 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 8 8 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2005-2010. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8231 Rev 9.00 Page 23 of 24 November 30, 2010

ISL12026, ISL12026A Package Outline Drawing M8.173 8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 01/10 A 2 4 3.0 ±0.5 SEE DETAIL "X" 8 5 6.40 4.40 ±0.10 CL 3 4 PIN 1 ID MARK 0.20CBA 1 4 0.65 B 0.09-0.20 TOP VIEW END VIEW 1.00 REF H 0.05 C 0.90 +0.15/-0.10 1.20 MAX SEATING GAUGE PLANE PLANE 0.25 0.25 +0.05/-0.06 6 0.10C 0.10 CBA 0.05 MIN 0°-8° 0.15 MAX 0.60 ±0.15 SIDE VIEW DETAIL "X" (1.45) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimension does not include mold flash, protrusions or (5.65) gate burrs. Mold flash, protrusions or gate burrs shall PACKAGE BODY not exceed 0.15 per side. OUTLINE 3. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.15 per side. 4. Dimensions are measured at datum plane H. 5. Dimensioning and tolerancing per ASME Y14.5M-1994. 6. Dimension on lead width does not include dambar protrusion. (0.35 TYP) Allowable protrusion shall be 0.08 mm total in excess of (0.65 TYP) dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. TYPICAL RECOMMENDED LAND PATTERN 7. Conforms to JEDEC MO-153, variation AC. Issue E FN8231 Rev 9.00 Page 24 of 24 November 30, 2010