ISL12022 FN6659 Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation Rev.3.01 ±5ppm with Auto Daylight Saving Oct 24, 2019 The ISL12022 device is a low power real time clock with an Features embedded Temp sensor for oscillator compensation, clock/calendar, power fail, low battery monitor, brownout • Real Time Clock/Calendar indicator, single periodic or polled alarms, intelligent - Tracks Time in Hours, Minutes and Seconds battery-backup switching, Battery Reseal™ function, and - Day of the Week, Day, Month, and Year 128bytes of battery-backed user SRAM. • On-chip Oscillator Compensation Over the Operating The oscillator uses an external, low-cost 32.768kHz crystal. Temperature Range The real time clock tracks time with separate registers for - ±5ppm Over -40°C to +85°C hours, minutes, and seconds. The device has calendar • 10-bit Digital Temperature Sensor Output registers for date, month, year, and day of the week. The - ±2°C Accuracy calendar is accurate through 2099, with automatic leap year correction. • Customer Programmable Day Light Saving Time • 15 Selectable Frequency Outputs Daylight Savings time adjustment is done automatically, using parameters entered by the user. Power fail and battery • 1 Alarm monitors offer user-selectable trip levels. A time stamp - Settable to the Second, Minute, Hour, Day of the Week, function records the time and date of switchover from VDD to Day, or Month VBAT power, and also from VBAT to VDD power. - Single Event or Pulse Interrupt Mode Applications • Battery Reseal™ Function to Extend Battery Shelf Life • Automatic Backup to Battery or Super Capacitor • Utility Meters - Operation to VBAT = 1.8V • POS Equipment - 1.0µA Battery Supply Current • Medical Devices • Battery Status Monitor • Security Systems - 2 User Programmable Levels • Vending Machines - Seven Selectable Voltages for Each Level • White Goods • Power Status Brownout Monitor • Printers and Copiers - Six Selectable Trip Levels, from 2.295V to 4.675V • Oscillator Failure Detection Related Literature • Time Stamp for First VDD to VBAT, and Last VBAT to VDD For a full list of related documents, visit our website • 128 Bytes Battery-Backed User SRAM •ISL12022 device page • I2C Bus™ - 400kHz Clock Frequency • 1µA Typical Battery Current • Pb-Free (RoHS Compliant) VDD = 2.7V ISL12022 JBAT DBAT TO 5.5V BAT43W VDD VBAT +VBAT = 1.8V CIN CBAT TO 3.2V 0.1µF 0.1µF GND FIGURE 1. TYPICAL APPLICATION CIRCUIT FN6659 Rev.3.01 Page 1 of 32 Oct 24, 2019

ISL12022 Table of Contents Control and Status Registers (CSR). . . . . . . . . . . . . . . . . . . 15 Addresses [07h to 0Fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Status Register (SR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Interrupt Control Register (INT). . . . . . . . . . . . . . . . . . . . . . . . 16 VDD Brownout Trip Voltage BITS (VDDTrip<2:0) . . . . . . . . . . 17 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Battery Voltage Trip Voltage Register (PWR_VBAT). . . . . . . 17 Initial AT and DT Setting Register (ITRO). . . . . . . . . . . . . . . . 17 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 BETA Register (BETA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Final Analog Trimming Register (FATR). . . . . . . . . . . . . . . . . 20 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . .5 Final Digital Trimming Register (FDTR). . . . . . . . . . . . . . . . . 20 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ALARM Registers (10h to 15h). . . . . . . . . . . . . . . . . . . . . . . . 21 Time Stamp VDD to Battery Registers (TSV2B) . . . . . . . . . . 22 DC Operating Characteristics - RTC . . . . . . . . . . . . . . . . . . . .5 Time Stamp Battery to VDD Registers (TSB2V) . . . . . . . . . . 22 Power-Down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 DST Control Registers (DSTCR). . . . . . . . . . . . . . . . . . . . . . . . 22 I2C Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TEMP Registers (TEMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 NPPM Registers (NPPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SDA vs SCL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 XT0 Registers (XT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ALPHA Hot Register (ALPHAH) . . . . . . . . . . . . . . . . . . . . . . . . 24 Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 User Registers (Accessed by Using Slave Address Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . .9 1010111x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Addresses [00h to 7Fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Protocol Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 X1, X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 VBAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 IRQ/FOUT (Interrupt Output/Frequency Output) . . . . . . . . . .10 Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 VDD, GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Application Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Power Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 26 Normal Mode (VDD) to Battery-Backup Mode (VBAT) . . . . . .11 Battery-Backup Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Battery-Backup Mode (VBAT) to Normal Mode (VDD) . . . . . .11 Oscillator Crystal Requirements. . . . . . . . . . . . . . . . . . . . . . . 27 Power Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Brownout Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Battery Level Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Crystal Oscillator Frequency Compensation . . . . . . . . . . . . . 28 Real Time Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .12 Measuring Oscillator Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 28 Single Event and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Temperature Compensation Operation. . . . . . . . . . . . . . . . . 29 Frequency Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Daylight Savings Time (DST) Example. . . . . . . . . . . . . . . . . . 29 General Purpose User SRAM . . . . . . . . . . . . . . . . . . . . . . . . . .12 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Oscillator Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .15 Addresses [00h to 06h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 FN6659 Rev.3.01 Page 2 of 32 Oct 24, 2019

ISL12022 Block Diagram SDA BUSFDFAER I2C SECONDS SCL BUSFCFLER INTERFACE COLNOTGRICOL MINUTES REGISTERS HOURS DAY OF WEEK X1 CRYSTAL RTC DATE OSCILLATOR DIVIDER X2 MONTH VDD POR FREQUENCY YEAR OUT ALARM CONTROL VTRIP REGISTERS SWITCH USER SRAM VBAT INTERNAL SUPPLY IRQ/FOUT GND TEMPERATURE FREQUENCY SENSOR CONTROL Ordering Information PART NUMBER PART VDD RANGE TEMP RANGE TAPE AND REEL PACKAGE PKG. (Notes2, 3) MARKING (V) (°C) (Units) (Note1) (RoHS Compliant) DWG. # ISL12022IBZ 12022 IBZ 2.7 to 5.5 -40 to +85 - 8 Ld SOIC M8.15 ISL12022IBZ-T 12022 IBZ 2.7 to 5.5 -40 to +85 2.5k 8 Ld SOIC M8.15 ISL12022IBZ-T7A 12022 IBZ 2.7 to 5.5 -40 to +85 250 8 Ld SOIC M8.15 NOTES: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL12022 device page. For more information about MSL, see TB363. FN6659 Rev.3.01 Page 3 of 32 Oct 24, 2019

ISL12022 Pin Configuration Pin Descriptions ISL12022 PIN # SYMBOL DESCRIPTION (8 LD SOIC) 1 X1 Crystal Input. The X1 pin is the input of an inverting TOP VIEW amplifier and is intended to be connected to one pin of an external 32.768kHz quartz crystal. X1 can also be X1 1 8 VDD driven directly from a 32.768kHz source. 2 X2 Crystal Output. The X2 pin is the output of an inverting X2 2 7 IRQ/FOUT amplifier and is intended to be connected to one pin of VBAT 3 6 SCL an external 32.768kHz quartz crystal. X2 should be left open when X1 is driven from external source. GND 4 5 SDA 3 VBAT Backup Supply. This input provides a backup supply voltage to the device. VBAT supplies power to the device in the event that the VDD supply fails. This pin should be tied to ground if not used. 4 GND Ground. 5 SDA Serial Data. SDA is a bi-directional pin used to transfer serial data into and out of the device. It has an open drain output and may be wire OR’ed with other open drain or open collector outputs. 6 SCL Serial Clock. The SCL input is used to clock all serial data into and out of the device. 7 IRQ/FOUT Interrupt Output/Frequency Output. Multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. It is an open-drain output. 8 VDD Power Supply. FN6659 Rev.3.01 Page 4 of 32 Oct 24, 2019

ISL12022 Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT and IRQ/FOUT pins Thermal Resistance (Typical) JA (°C/W) JC (°C/W) (respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 8 Ld SOIC (Notes4, 5) . . . . . . . . . . . . . . . . . 102 46 Voltage on SCL and SDA pins Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C (respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Voltage on X1 and X2 pins (respect to ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Per MIL-STD-883 Method 3014) . . . . . . . . . . >3kV Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldfacelimits apply over the operating temperature range, -40°C to +85°C MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note13) (Note9) (Note13) UNIT NOTES VDD Main Power Supply (Note15) 2.7 5.5 V VBAT Battery Supply Voltage (Note15) 1.8 5.5 V 6 IDD1 Supply Current. (I2CnotActive, Temperature VDD = 5V 4.1 15 µA 7, 8 Conversion not Active, FOUT not Active) VDD = 3V 3.5 14 µA 7, 8 IDD2 Supply Current. (I2C Active, Temperature VDD = 5V 200 500 µA 7, 8 Conversion not Active, FOUT not Active) IDD3 Supply Current. (I2CnotActive, Temperature VDD = 5V 120 400 µA 7, 8 Conversion Active, FOUT not Active) IBAT Battery Supply Current VDD = 0V, VBAT = 3V, TA= +25°C 1.0 1.6 µA 7 VDD = 0V, VBAT = 3V 1.0 5.0 µA 7 IBATLKG Battery Input Leakage VDD = 5.5V, VBAT = 1.8V 100 nA ILI Input Leakage Current on SCL VIL = 0V, VIH = 5.5V -1.0 ±0.1 1.0 µA ILO I/O Leakage Current on SDA VIL = 0V, VIH = 5.5V -1.0 ±0.1 1.0 µA VBATM Battery Level Monitor Threshold -100 +100 mV VPBM Brownout Level Monitor Threshold -100 +100 mV VTRIP VBAT Mode Threshold (Note15) 2.0 2.2 2.4 V VTRIPHYS VTRIP Hysteresis 30 mV 11 VBATHYS VBAT Hysteresis 50 mV 11 FoutT Oscillator Stability vs Temperature VDD  3.3V -5 +5 ppm 14 FoutV Oscillator Stability vs Voltage 2.7V  VDD  5.5V -3 +3 ppm 14 ATLSB AT Sensitivity per LSB BETA (4:0) = 10000 0.5 1 2 ppm 14 Temp Temperature Sensor Accuracy VDD = VBAT = 3.3V ±2 °C 11 IRQ/FOUT (OPEN DRAIN OUTPUT) VOL Output Low Voltage VDD = 5.5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V FN6659 Rev.3.01 Page 5 of 32 Oct 24, 2019

ISL12022 Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldfacelimits apply over the operating temperature range, -40°C to +85°C MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note13) (Note9) (Note13) UNIT NOTES VDD SR- VDD Negative Slew Rate 10 V/ms 10 VDDSR+ VDD Positive Slew Rate, Minimum 0.05 V/ms 16 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. Boldfacelimitsapply over the operating temperature range, -40°C to +85°C MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note13) (Note9) (Note13) UNIT NOTES VIL SDA and SCL Input Buffer LOW Voltage -0.3 0.3 x VDD V VIH SDA and SCL Input Buffer HIGH Voltage 0.7 x VDD VDD + 0.3 V Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x VDD V 11, 12 VOL SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA 0 0.02 0.4 V Sinking 3mA CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, VDD = 5V, 10 pF 11, 12 VIN=0V, VOUT = 0V fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at SDA Any pulse narrower than the max 50 ns and SCL Inputs spec is suppressed. tAA SCL Falling Edge To SDA Output Data SCL falling edge crossing 30% of 900 ns Valid VDD, until SDA exits the 30% to 70% of VDD window. tBUF Time the Bus Must be Free Before the SDA crossing 70% of VDD during 1300 ns Start of a New Transmission a STOP condition, to SDA crossing 70% of VDD during the following START condition. tLOW Clock LOW Time Measured at the 30% of VDD 1300 ns crossing. tHIGH Clock HIGH Time Measured at the 70% of VDD 600 ns crossing. tSU:STA START Condition Setup Time SCL rising edge to SDA falling 600 ns edge. Both crossing 70% of VDD. tHD:STA START Condition Hold Time From SDA falling edge crossing 600 ns 30% of VDD to SCL falling edge crossing 70% of VDD. tSU:DAT Input Data Setup Time From SDA exiting the 30% to 100 ns 70% of VDD window, to SCL rising edge crossing 30% of VDD. tHD:DAT Input Data Hold Time From SCL falling edge crossing 0 900 ns 30% of VDD to SDA entering the 30% to 70% of VDD window. tSU:STO STOP Condition Setup Time From SCL rising edge crossing 600 ns 70% of VDD, to SDA rising edge crossing 30% of VDD. tHD:STO STOP Condition Hold Time From SDA rising edge to SCL 600 ns falling edge. Both crossing 70% of VDD. tDH Output Data Hold Time From SCL falling edge crossing 0 ns 30% of VDD, until SDA enters the 30% to 70% of VDD window. FN6659 Rev.3.01 Page 6 of 32 Oct 24, 2019

ISL12022 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. Boldfacelimitsapply over the operating temperature range, -40°C to +85°C (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note13) (Note9) (Note13) UNIT NOTES tR SDA and SCL Rise Time From 30% to 70% of VDD. 20 +0.1 x Cb 300 ns 12 tF SDA and SCL Fall Time From 70% to 30% of VDD. 20 +0.1 x Cb 300 ns 12 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 12 RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR 1 kΩ 12 Off-chip and tF. For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ NOTES: 6. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT <1.8V. 7. IRQ/FOUT inactive. 8. VDD > VBAT +VBATHYS. 9. Specified at +25°C. 10. To ensure proper timekeeping, the VDD SR- specification must be followed. 11. Limits should be considered typical and are not production tested. 12. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. Specifications are typical and require using a recommended crystal (see “Application Section” on page26). 15. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested. 16. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only. FN6659 Rev.3.01 Page 7 of 32 Oct 24, 2019

ISL12022 SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change Will change from LOW from LOW to HIGH to HIGH May change Will change from HIGH from HIGH to LOW to LOW Don’t Care: Changing: Changes Allowed State Not Known N/A Center Line is High Impedance EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V 5.0V FOR VOL= 0.4V 1533 SDA AND IOL = 3mA AND IRQ/FOUT 100pF FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VDD = 5.0V FN6659 Rev.3.01 Page 8 of 32 Oct 24, 2019

ISL12022 Typical Performance Curves Temperature is +25°C unless otherwise specified. 1050 1600 1000 1400 A) n T ( RREN 950 (nA)T 1200 VBAT = 5.5V CU 900 BA 1000 BAT I VBAT = 3.0V V 850 800 VBAT = 1.8V 800 600 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 -40 -20 0 20 40 60 80 VBAT VOLTAGE (V) TEMPERATURE (°C) FIGURE 3. IBAT vs VBAT FIGURE 4. IBAT vs TEMPERATURE 6 4.4 4.2 5 VDD = 5.5V 4.0 A) A) 3.8 (µD1 4 (µD1 3.6 D D I VDD = 2.7V I 3.4 3 VDD = 3.3V 3.2 2 3.0 -40 -20 0 20 40 60 80 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) VDD (V) FIGURE 5. IDD1 vs TEMPERATURE FIGURE 6. IDD1 vs VDD 6 5.5 A) 5.0 5 VDD = 5.5V NT (µ 4.5 FOUT = 32kHz A) RE I (µDD 4 LY CUR 34..50 FOUT = 1Hz and 64Hz 3 VDD = 3.3V VDD = 2.7V UPP S 3.0 2 2.5 0.01 0.1 1 10 100 1k 10k 100k -40 -20 0 20 40 60 80 FREQUENCY OUTPUT (Hz) TEMPERATURE (°C) FIGURE 7. FOUT vs IDD FIGURE 8. IDD vs TEMPERATURE, 3 DIFFERENT FOUT FN6659 Rev.3.01 Page 9 of 32 Oct 24, 2019

ISL12022 Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 110 110 100 100 90 90 VDD = 5.5V 80 VBAT = 5.5V I (µA)DD 678000 VDD = 3.3V VDD = 2.7V I (µA)BAT 567000 VBAT = 3.0V VBAT = 1.8V 40 50 30 40 20 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. IDD WITH TSE = 1 vs TEMPERATURE FIGURE 10. IBAT with TSE = 1, BTSE = 1 vs TEMPERATURE General Description Pin Descriptions The ISL12022 device is a low power real time clock (RTCs) with X1, X2 embedded temperature sensors. It contains crystal frequency compensation circuitry over the operating temperature range, The X1 and X2 pins are the input and output, respectively, of an clock/calendar, power fail and low battery monitors, brownout inverting amplifier. An external 32.768kHz quartz crystal is used indicator, 1 periodic or polled alarm, intelligent battery-backup with the device to supply a timebase for the real time clock. Internal compensation circuitry with internal temperature sensor switching and 128 Bytes of battery-backed user SRAM. provides frequency corrections for selected popular crystals to The oscillator uses an external, low cost 32.768kHz crystal. The ±5ppm over the operating temperature range from -40°Cto real time clock tracks time with separate registers for hours, +85°C. (See “Application Section” on page26 for recommended minutes and seconds. The device has calendar registers for date, crystal). The ISL12022 allows the user to input via I2C serial bus month, year and day of the week. The calendar is accurate the temperature variation profile of an individual crystal. The through 2099, with automatic leap year correction. In addition, oscillator compensation network can also be used to calibrate the ISL12022 can be programmed for automatic Daylight the initial crystal timing accuracy to less than 1ppm error at Savings Time (DST) adjustment by entering local DST room temperature. The device can also be driven directly from a information. 32.768kHz source at pin X1. The ISL12022’s alarm can be set to any clock/calendar value for a match, for example, every minute, every Tuesday or at 5:23 AM on March 21. The alarm status is available by checking the X1 Status Register, or the device can be configured to provide a X2 hardware interrupt via the IRQ/FOUT pin. There is a repeat mode for the alarm allowing a periodic interrupt every minute, every hour, every day, etc. FIGURE 11. RECOMMENDED CRYSTAL CONNECTION The device also offers a backup power input pin. This VBAT pin V allows the device to be backed up by battery or super capacitor BAT with automatic switchover from VDD to VBAT. The ISL12022 This input provides a backup supply voltage to the device. VBAT device is specified for VDD = 2.7V to 5.5V and the clock/calendar supplies power to the device in the event that the VDD supply portion of the device remains fully operational in battery-backup fails. Device power will automatically switch to the VBAT input mode down to 1.8V (Standby Mode). The VBAT level is monitored when VDD drops below the switchover trip level (VTRIP). This pin and reported against preselected levels. The first report is can be connected to a battery, a super capacitor or tied to ground registered when the VBAT level falls below 85% of nominal level, if not used. the second level is set for 75%. Battery levels are stored in PWR_VBAT registers. IRQ/FOUT (Interrupt Output/Frequency Output) The ISL12022 offers a “Brownout” alarm once the VDD falls below a pre-selected trip level. This allows system Micro to save This dual function pin can be used as an interrupt or frequency vital information to memory before complete power loss. There output pin. The IRQ/FOUT mode is selected via the frequency out are six VDD levels that could be selected for initiation of the control bits of the control/status register. It is an open drain Brownout alarm. output. FN6659 Rev.3.01 Page 10 of 32 Oct 24, 2019

ISL12022 •Interrupt Mode. The pin provides an interrupt signal output. Condition 1: This signal notifies a host processor that an alarm has VDD > VBAT + VBATHYS occurred and requests action. It is an active low output. where VBATHYS 50mV •Frequency Output Mode. The pin outputs a clock signal, which Condition 2: is related to the crystal frequency. The frequency is user selectable and enabled via the I2C bus. VDD > VTRIP + VTRIPHYS where VTRIPHYS  30mV Serial Clock (SCL) These power control situations are illustrated in Figures12 The SCL input is used to clock all serial data into and out of the and13. device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. BATTERY-BACKUP MODE Serial Data (SDA) VDD SDA is a bi-directional pin used to transfer data into and out of VTRIP 2.2V the device. It has an open drain output and may be ORed with VBAT 1.8V other open drain or open collector outputs. The input buffer is a lways active (not gated) in normal mode. VBAT - VBATHYS VBAT + VBATHYS An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the FIGURE 12. BATTERY SWITCHOVER WHEN VBAT < VTRIP use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. V , GND DD Chip power supply and ground pins. The device will operate with BATTERY-BACKUP MODE a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is VDD recommended on the VDD pin to ground. The VDD Negative and VDD Positive Slew Rate specifications have to be observed. VBAT 3.0V VTRIP 2.2V Functional Description VTRIP VTRIP + VTRIPHYS Power Control Operation The power control circuit accepts a VDD and a VBAT input. Many types of batteries can be used with Intersil RTC products. For FIGURE 13. BATTERY SWITCHOVER WHEN VBAT > VTRIP example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL12022 for up to The I2C bus is deactivated in battery-backup mode to reduce 10 years. Another option is to use a super capacitor for power consumption. Aside from this, all RTC functions are applications where VDD is interrupted for up to a month. See the operational during battery-backup mode. Except for SCL and SDA, “Application Section” on page26 for more information. all the inputs and outputs of the ISL12022 are active during battery-backup mode unless disabled via the control register. Normal Mode (V ) to Battery-Backup Mode DD The device Time Stamps the switchover from VDD to VBAT and (V ) BAT VBAT to VDD, and the time is stored in tSV2B and tSB2V registers To transition from the VDD to VBAT mode, both of the following respectively. If multiple VDD power-down sequences occur before conditions must be met: status is read, the earliest VDD to VBAT power-down time is stored and the most recent VBAT to VDD time is stored. Condition 1: Temperature conversion and compensation can be enabled in VDD < VBAT - VBATHYS battery-backup mode. Bit BTSE in the BETA register controls this where VBATHYS  50mV operation, as described in “BETA Register (BETA)” on page19. Condition 2: Power Failure Detection VDD < VTRIP where VTRIP  2.2V The ISL12022 provides a Real Time Clock Failure Bit (RTCF) to detect total power failure. It allows users to determine if the Battery-Backup Mode (VBAT) to Normal Mode device has powered up after having lost all power to the device (VDD) (both VDD and VBAT). The ISL12022 device will switch from the VBAT to VDD mode when one of the following conditions occurs: FN6659 Rev.3.01 Page 11 of 32 Oct 24, 2019

ISL12022 Brownout Detection when the frequency output function is enabled, the alarm function is disabled. The ISL12022 monitors the VDD level continuously and provides warning if the VDD level drops below prescribed levels. There are The standard alarm allows for alarms of time, date, day of the six (6) levels that can be selected for the trip level. These values week, month, and year. When a time alarm occurs in single are 85% below popular VDD levels. The LVDD bit in the Status event mode, the IRQ/FOUT pin will be pulled low and the alarm Register will be set to “1” when brownout is detected. Note that status bit (ALM) will be set to “1”. the I2C serial bus remains active unless the Battery VTRIP levels The pulsed interrupt mode allows for repetitive or recurring alarm are reached. functionality. Hence, once the alarm is set, the device will Battery Level Monitor continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only The ISL12022 has a built in warning feature once the Back-up the nth second is set) or as infrequently as once a year (if at least battery level drops first to 85% and then to 75% of the battery’s the nth month is set). During pulsed interrupt mode, the nominal VBAT level. When the battery voltage drops to between IRQ/FOUT pin will be pulled low for 250ms and the alarm status 85% and 75%, the LBAT85 bit is set in the status register. When bit (ALM) will be set to “1”. the level drops below 75%, both LBAT85 and LBAT75 bits are set in the status register. The ALM bit can be reset by the user or cleared automatically using the auto reset mode (see ARST bit). The alarm function can The battery level monitor is not functional in battery backup be enabled/disabled during battery-backup mode using the mode. In order to read the monitor bits after powering up VDD, FOBATB bit. For more information on the alarm, please see instigate a battery level measurement by setting the TSE bit to “ALARM Registers (10h to 15h)” on page21. "1" (BETA register), and then read the bits. Frequency Output Mode There is a Battery Time Stamp Function available. Once the VDD is low enough to enable switchover to the battery, the RTC The ISL12022 has the option to provide a clock output signal time/date are written into the TSV2B register. This information using the IRQ/FOUT open drain output pin. The frequency output can be read from the TSV2B registers to discover the point in mode is set by using the FO bits to select 15 possible output time of the VDD power-down. If there are multiple power-down frequency values from 1/32Hz to 32kHz. The frequency output cycles before reading these registers, the first values stored in can be enabled/disabled during battery-backup mode using the these registers will be retained. These registers will hold the FOBATB bit. original power-down value until they are cleared by setting CLRTS General Purpose User SRAM = 1 to clear the registers. The normal power switching of the ISL12022 is designed to The ISL12022 provides 128 bytes of user SRAM. The SRAM will sTwhiistc whi liln eton sbuartet etrhya-bt athcek udpe vmicoed cea onn alyc cife tphte a V wDiDd ep orawnegr eis o lfo st. cboen ntiontueed ttoh aotp tehrea tIe2 Cin b buast itse rdyi-sbaabclkeudp i nm boadtete. rHyo-bwaecvkeurp, imt sohdoeu.l d backup voltages from many types of sources while reliably 2 I C Serial Interface switching into backup mode. The ISL12022 has an I2C serial bus interface that provides Note that the ISL12022 is not guaranteed to operate with access to the control and status registers and the user SRAM. VBAT<1.8V. If the battery voltage is expected to drop lower than The I2C serial interface is compatible with other industry I2C this minimum, correct operation of the device, especially after a serial bus protocols using a bi-directional data signal (SDA) and a VDD power-down cycle, is not guaranteed. clock signal (SCL). The minimum VBAT to insure SRAM is stable is 1.0V. Below that, Oscillator Compensation the SRAM may be corrupted when VDD power resumes. The ISL12022 provides both initial timing correction and Real Time Clock Operation temperature correction due to variation of the crystal oscillator. Analog and digital trimming control is provided for initial The Real Time Clock (RTC) uses an external 32.768kHz quartz adjustment, and a temperature compensation function is crystal to maintain an accurate internal representation of provided to automatically correct for temperature drift of the second, minute, hour, day of week, date, month, and year. The crystal. Initial values are preset and recalled on initial power-up RTC also has leap-year correction. The clock also corrects for for the Initial AT and DT settings (IATR, IDTR), temperature months having fewer than 31 days and has a bit that controls coefficient (ALPHA), crystal capacitance (BETA), and the crystal 24-hour or AM/PM format. When the ISL12022 powers up after turn-over temperature (XTO). These initial values are typical of the loss of both VDD and VBAT, the clock will not begin units available on the market, although the user may program incrementing until at least one byte is written to the clock specific values after testing for best accuracy. The function can register. be enabled/disabled at any time and can be used in battery mode as well. Single Event and Interrupt The alarm mode is enabled via the MSB bit. Choosing single event or interrupt alarm mode is selected via the IM bit. Note that FN6659 Rev.3.01 Page 12 of 32 Oct 24, 2019

ISL12022 Register Descriptions 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch The battery-backed registers are accessible following a slave 10.Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh byte of “1101111x” and reads or writes to addresses [00h:2Fh]. The defined addresses and default values are described in the 11.Scratch Pad (2 bytes): Address 2Eh and 2Fh Table1. The battery backed general purpose SRAM has a Write capability is allowable into the RTC registers (00h to 06h) different slave address (1010111x), so it is not possible to only when the WRTC bit (bit 6 of address 08h) is set to “1”. A read/write that section of memory while accessing the registers. multi-byte read or write operation should be limited to one section per operation for best RTC time keeping performance. REGISTER ACCESS The contents of the registers can be modified by performing a A register can be read by performing a random read at any byte or a page write operation directly to any register address. address at any time. This returns the contents of that register location. Additional registers are read by performing a sequential The registers are divided into 8 sections. They are: read. For the RTC and Alarm registers, the read instruction latches all clock registers into a buffer, so an update of the clock 1. Real Time Clock (7 bytes): Address 00h to 06h. does not change the time being read. At the end of a read, the 2. Control and Status (9 bytes): Address 07h to 0Fh. master supplies a stop condition to end the operation and free 3. Alarm (6 bytes): Address 10h to 15h. the bus. After a read, the address remains at the previous 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. address +1 so the user can execute a current address read and continue reading the next register. When the previous address is 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. 2Fh, the next address will wrap around to 00h. 6. Daylight Savings Time (8 bytes): 20h to 27h. It is not necessary to set the WRTC bit prior to writing into the 7. TEMP (2 bytes): 28h to 29h control and status, alarm, and user SRAM registers. TABLE 1. REGISTER MEMORY MAP BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 00h SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h 03h RTC DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 01h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 01h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0 to 6 00h 07h SR BUSY OSCF DSTADJ ALM LVDD LBAT85 LBAT75 RTCF N/A 01h 08h INT ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 N/A 01h 09h PWR_VDD CLRTS D D D D VDDTrip2 VDDTrip1 VDDTrip0 N/A 00h 0Ah PWR_VBAT RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A 00h 0Bh CSR ITRO IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 N/A 20h 0Ch ALPHA D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A 46h 0Dh BETA TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 N/A 00h 0Eh FATR 0 0 FFATR5 FATR4 FATR3 FATR2 FATR1 FATR0 N/A 00h 0Fh FDTR 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 N/A 00h 10h SCA0 ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 00 to 59 00h 11h MNA0 EMNA0 MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59 00h 12h HRA0 EHRA0 D HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23 00h ALARM 13h DTA0 EDTA0 D DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 01 to 31 00h 14h MOA0 EMOA00 D D MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12 00h 15h DWA0 EDWA0 D D D D DWA02 DWA01 DWA00 0 to 6 00h FN6659 Rev.3.01 Page 13 of 32 Oct 24, 2019

ISL12022 TABLE 1. REGISTER MEMORY MAP (Continued) BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 16h VSC 0 VSC22 VSC21 VSC20 VSC13 VSC12 VSC11 VSC10 0 to 59 00h 17h VMN 0 VMN22 VMN21 VMN20 VMN13 VMN12 VMN11 VMN10 0 to 59 00h 18h TSV2B VHR VMIL 0 VHR21 VHR20 VHR13 VHR12 VHR11 VHR10 0 to 23 00h 19h VDT 0 0 VDT21 VDT20 VDT13 VDT12 VDT11 VDT10 1 to 31 00h 1Ah VMO 0 0 0 VMO20 VMO13 VMO12 VMO11 VMO10 1 to 12 00h 1Bh BSC 0 BSC22 BSC21 BSC20 BSC13 BSC12 BSC11 BSC10 0 to 59 00h 1Ch BMN 0 BMN22 BMN21 BMN20 BMN13 BMN12 BMN11 BMN10 0 to 59 00h 1Dh TSB2V BHR BMIL 0 BHR21 BHR20 BHR13 BHR12 BHR11 BHR10 0 to 23 00h 1Eh BDT 0 0 BDT21 BDT20 BDT13 BDT12 BDT11 BDT10 1 to 31 00h 1Fh BMO 0 0 0 BMO20 BMO13 BMO12 BMO11 BMO10 1 to 12 00h 20h DstMoFd DSTE D D DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10 1 to 12 00h 21h DstDwFd D DstDwFdE DstWkFd12 DstWkFd11 DstWkFd10 DstDwFd12 DstDwFd11 DstDwFd10 0 to 6 00h 22h DstDtFd D D DstDtFd21 DstDtFd20 DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10 1 to 31 00h 23h DstHrFd D D DstHrFd21 DstHrFd20 DstHrFd13 DstHrFd12 DstHrFd11 DstHrFd10 0 to 23 00h DSTCR 24h DstMoRv D D D XDstMoRv20 DstMoRv13 DstMoR12v DstMoRv11 DstMoRv10 01 to 12 00h 25h DstDwRv D DstDwRvE DstWkrv12 DstWkRv11 DstWkRv10 DstDwRv12 DstDwRv11 DstDwRv10 0 to 6 00h 26h DstDtRv D D DstDtRv21 DstDtRv20 DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10 01 to 31 00h 27h DstHrRv D D DstHrRv21 DstHrRv20 DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10 0 to 23 00h 28h TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 00 to FF 00h TEMP 29h TK0M 0 0 0 0 0 0 TK09 TK08 00 to 03 00h 2Ah NPPML NPPM7 NPPM6 NPPM5 NPPM4 NPPM3 NPPM2 NPPM1 NPPM0 00 to FF 00h NPPM 2Bh NPPMH 0 0 0 0 0 NPPM10 NPPM9 NPPM8 00 to 07 00h 2Ch XT0 XT0 D D D XT4 XT3 XT2 XT1 XT0 00 to FF 00h 2Dh ALPHAH ALPHAH D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 00 to 7F 46h 2Eh GPM1 GPM17 GPM16 GPM15 GPM14 GPM13 GPM12 GPM11 GPM10 00 to FF 00h GPM 2Fh GPM2 GPM27 GPM26 GPM25 GPM24 GPM23 GPM22 GPM21 GPM20 00 to FF 00h FN6659 Rev.3.01 Page 14 of 32 Oct 24, 2019

ISL12022 Real Time Clock Registers OSCILLATOR FAIL BIT (OSCF) Oscillator Fail Bit indicates that the oscillator has failed. The Addresses [00h to 06h] oscillator frequency is either zero or very far from the desired 32.768kHz due to failure, PC board contamination or mechanical RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) issues. These registers depict BCD representations of the time. As such, DAYLIGHT SAVINGS TIME CHANGE BIT (DSTADJ) SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, DSTADJ is the Daylight Savings Time Adjusted Bit. It indicates the MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW (Day of the daylight saving time forward adjustment has happened. If a DST Week) is 0 to 6. Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit will stay high after the DSTFD event happens, and will be reset to The DW register provides a Day of the Week status and uses three “0” when the DST Reverse event happens. It is read-only and bits DW2 to DW0 to represent the seven days of the week. The cannot be written. Setting time during a DST forward period will counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… not set this bit to “1”. Theassignment of a numerical value to a specific day of the week is arbitrary and may be decided by the system software The DSTE bit must be enabled when the RTC time is more than designer. The default value is defined as “0”. one hour before the DST Forward or DST Reverse event time setting, or the DST event correction will not happen. 24 HOUR TIME DSTADJ is reset to “0” upon power-up. It will reset to ”0” when the If the MIL bit of the HR register is “1”, the RTC uses a DSTE bit in Register 15h is set to “0” (DST disabled), but no time 24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour adjustment will happen. format and HR21 bit functions as an AM/PM indicator with a “1” representing PM. The clock defaults to 12-hour format time with ALARM BIT (ALM) HR21 = “0”. This bit announces if the alarm matches the real time clock. If LEAP YEARS there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by Leap years add the day February 29 and are defined as those years enabling the auto-reset bit (see ARST bit). A write to this bit in the that are divisible by 4. Years divisible by 100 are not leap years, SR can only set it to “0”, not “1”. An alarm bit that is set by an unless they are also divisible by 400. This means that the year 2000 alarm occurring during an SR read operation will remain set after is a leap year and the year 2100 is not. The ISL12022 does not the read operation is complete. correct for the leap year in the year 2100. LOW V INDICATOR BIT (LVDD) DD Control and Status Registers This bit indicates when VDD has dropped below the pre-selected (CSR) trip level (Brownout Mode). The trip points for the brownout levels are selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in Addresses [07h to 0Fh] PWR_ VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set The Control and Status Registers consist of the Status Register, whenever the VDD has dropped below the pre-selected trip level, Interrupt and Alarm Register, Analog Trimming and Digital and self clears whenever the VDD is above the pre-selected trip Trimming Registers. level. Status Register (SR) LOW BATTERY INDICATOR 85% BIT (LBAT85) The Status Register is located in the memory map at address In Normal Mode (VDD), this bit indicates when the battery level 07h. This is a volatile register that provides either control or has dropped below the pre-selected trip levels. The trip points are status of RTC failure (RTCF), Battery Level Monitor (LBAT85, selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the LBAT75), alarm trigger, Daylight Savings Time, crystal oscillator PWR_VBAT registers. The LBAT85 detection happens enable and temperature conversion in progress bit. automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TABLE 2. STATUS REGISTER (SR) TSE bit in BETA register to “1”. The LBAT85 bit is set when the ADDR 7 6 5 4 3 2 1 0 VBAT has dropped below the pre-selected trip level, and will self 07h BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. BUSY BIT (BUSY) In Battery Mode (VBAT), this bit indicates the device has entered Busy Bit indicates temperature sensing is in progress. In this into battery mode by polling once every 10 minutes. The LBAT85 mode, Alpha, Beta and ITRO registers are disabled and cannot be detection happens automatically once when the minute register accessed. reaches x9h or x0h minutes. FN6659 Rev.3.01 Page 15 of 32 Oct 24, 2019

ISL12022 Example - When the LBAT85 is Set To “1” In Battery Mode: ARST is cleared to “0”, the user must manually reset the ALM, LVDD, LBAT85, and LBAT75 bits. The minute the register changes to 19h when the device is in battery mode, the LBAT85 is set to “1” the next time the device WRITE RTC ENABLE BIT (WRTC) switches back to Normal Mode. The WRTC bit enables or disables write capability into the RTC Example - When the LBAT85 Remains at “0” In Battery Mode: Timing Registers. The factory default setting of this bit is “0”. If the device enters into battery mode after the minute register Upon initialization or power-up, the WRTC must be set to “1” to reaches 20h and switches back to Normal Mode before the enable the RTC. Upon the completion of a valid write (STOP), the minute register reaches 29h, then the LBAT85 bit will remain at RTC starts counting. The RTC internal 1Hz signal is synchronized “0” the next time the device switches back to Normal Mode. to the STOP condition during a valid write cycle. LOW BATTERY INDICATOR 75% BIT (LBAT75) INTERRUPT/ALARM MODE BIT (IM) In Normal Mode (VDD), this bit indicates when the battery level This bit enables/disables the interrupt mode of the alarm has dropped below the pre-selected trip levels. The trip points are function. When the IM bit is set to “1”, the alarm will operate in selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the the interrupt mode, where an active low pulse width of 250ms PWR_VBAT registers. The LBAT75 detection happens will appear at the IRQ/FOUT pin when the RTC is triggered by the automatically once every minute when seconds register reaches alarm, as defined by the alarm registers (0Ch to 11h). When the 59. The detection can also be manually triggered by setting the IM bit is cleared to “0”, the alarm will operate in standard mode, TSE bit in BETA register to “1”. The LBAT75 bit is set when the where the IRQ/FOUT pin will be set low until the ALM status bit is VBAT has dropped below the pre-selected trip level, and will self cleared to “0”. clear when the VBAT is above the pre-selected trip level at the TABLE 4. next detection cycle either by manual or automatic trigger. IM BIT INTERRUPT/ALARM FREQUENCY In Battery Mode (VBAT), this bit indicates the device has entered into battery mode by polling once every 10 minutes. The LBAT85 0 Single Time Event Set By Alarm detection happens automatically once when the minute register 1 Repetitive/Recurring Time Event Set By Alarm reaches x9h or x0h minutes. Example - When the LBAT75 is Set to “1” in Battery Mode: FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) The minute register changes to 30h when the device is in battery This bit enables/disables the IRQ/FOUT pin during mode, the LBAT75 is set to “1” the next time the device switches battery-backup mode (i.e., VBAT power source active). When the back to Normal Mode. FOBATB is set to “1”, the IRQ/FOUT pin is disabled during battery-backup mode. This means that both the frequency output Example - When the LBAT75 Remains at “0” in Battery Mode: and alarm output functions are disabled. When the FOBATB is If the device enters into battery mode after the minute register cleared to “0”, the IRQ/FOUT pin is enabled during battery-backup reaches 49h and switches back to Normal Mode before minute mode. Note that the open drain IRQ/FOUT pin will need a pull-up register reaches 50h, then the LBAT75 bit will remain at “0” the to the battery voltage to operate in battery-backup mode. next time the device switches back to Normal Mode. FREQUENCY OUT CONTROL BITS (FO<3:0>) REAL TIME CLOCK FAIL BIT (RTCF) These bits enable/disable the frequency output function and select This bit is set to a “1” after a total power failure. This is a read the output frequency at the IRQ/FOUT pin. See Table5 for frequency only bit that is set by hardware (ISL12022 internally) when the selection. Default for the ISL12022 is FO<3:0> = 1h, or 32.768kHz device powers up after having lost all power (defined as VDD = 0V output. When the frequency mode is enabled, it will override the and VBAT = 0V). The bit is set regardless of whether VDD or VBAT alarm mode at the IRQ/FOUT pin. is applied first. The loss of only one of the supplies does not set the RTCF bit to “1”. The first valid write to the RTC section after a TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN complete power failure resets the RTCF bit to “0” (writing one FREQUENCY, byte is sufficient). FOUT UNITS FO3 FO2 FO1 FO0 Interrupt Control Register (INT) 0 Hz 0 0 0 0 32768 Hz 0 0 0 1 TABLE 3. INTERRUPT CONTROL REGISTER (INT) 4096 Hz 0 0 1 0 ADDR 7 6 5 4 3 2 1 0 08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 1024 Hz 0 0 1 1 64 Hz 0 1 0 0 AUTOMATIC RESET BIT (ARST) 32 Hz 0 1 0 1 This bit enables/disables the automatic reset of the ALM, LVDD, 16 Hz 0 1 1 0 LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the 8 Hz 0 1 1 1 respective status register (with a valid STOP condition). When the FN6659 Rev.3.01 Page 16 of 32 Oct 24, 2019

ISL12022 TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN (Continued) unused. Once VDD is powered up, this bit is reset and the VBAT pin is then connected to the internal circuitry. FREQUENCY, FOUT UNITS FO3 FO2 FO1 FO0 The application for this bit involves placing the chip on a board with a battery and testing the board. Once the board is tested 4 Hz 1 0 0 0 and ready to ship, it is desirable to disconnect the battery to keep 2 Hz 1 0 0 1 it fresh until the board or unit is placed into final use. Setting 1 Hz 1 0 1 0 RESEALB = “1” initiates the battery disconnect, and after VDD power is cycled down and up again, the RESEAL bit is cleared 1/2 Hz 1 0 1 1 to“0”. 1/4 Hz 1 1 0 0 BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>) 1/8 Hz 1 1 0 1 Three bits select the first alarm (85% of Nominal VBAT) level for the 1/16 Hz 1 1 1 0 battery voltage monitor. There are total of 7 levels that could be selected for the first alarm. Any of the of levels could be selected as 1/32 Hz 1 1 1 1 the first alarm with no reference as to nominal Battery voltage level. See Table8. POWER SUPPLY CONTROL REGISTER (PWR_VDD) TABLE 8. VB85T ALARM LEVEL Clear Time Stamp Bit (CLRTS) BATTERY ALARM TRIP LEVEL ADDR 7 6 5 4 3 2 1 0 VB85Tp2 VB85Tp1 VB85Tp0 (V) 09h CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0 0 0 0 2.125 This bit clears Time Stamp VDD to Battery (TSV2B) and Time 0 0 1 2.295 Stamp Battery to VDD Registers (TSB2V). The default setting is 0 0 1 0 2.550 (CLRTS=0) and the Enabled setting is 1 (CLRTS= 1). 0 1 1 2.805 V Brownout Trip Voltage BITS (V Trip<2:0) DD DD 1 0 0 3.060 These bits set the 6 trip levels for the VDD alarm, indicating that VDD has dropped below a preset level. In this event, the LVDD bit 1 0 1 4.250 in the Status Register is set to “1”. See Table6. 1 1 0 4.675 TABLE 6. VDD TRIP LEVELS BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) TRIP VOLTAGE VDDTrip2 VDDTrip1 VDDTrip0 (V) Three bits select the second alarm (75% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be 0 0 0 2.295 selected for the second alarm. Any of the of levels could be selected 0 0 1 2.550 as the second alarm with no reference as to nominal Battery voltage level. See Table9. 0 1 0 2.805 0 1 1 3.060 TABLE 9. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) 1 0 0 4.250 BATTERY ALARM TRIP LEVEL 1 0 1 4.675 VB75Tp2 VB75Tp1 VB75Tp0 (V) Battery Voltage Trip Voltage Register 0 0 0 1.875 (PWR_VBAT) 0 0 1 2.025 This register controls the trip points for the two VBAT alarms, with 0 1 0 2.250 levels set to approximately 85% and 75% of the nominal battery 0 1 1 2.475 level. 1 0 0 2.700 TABLE 7. 1 0 1 3.750 ADDR 7 6 5 4 3 2 1 0 0Ah D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 1 1 0 4.125 Initial AT and DT Setting Register (ITRO) RESEAL BIT (RESEALB) This is the Reseal bit for actively disconnecting VBAT pin from the These bits are used to trim the initial error (at room temperature) internal circuitry. Setting this bit allows the device to disconnect the of the crystal. Both Digital Trimming (DT) and Analog Trimming battery and eliminate standby current drain while the device is (AT) methods are available. The digital trimming uses clock pulse skipping and insertion for frequency adjustment. Analog FN6659 Rev.3.01 Page 17 of 32 Oct 24, 2019

ISL12022 trimming uses load capacitance adjustment to pull the oscillator TABLE 12. IATR0 TRIMMING RANGE (Continued) frequency. A range of +62.5ppm to -61.5ppm is possible with TRIMMING combined digital and analog trimming. IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE AGING AND INITIAL TRIM DIGITAL TRIMMING BITS 0 0 1 1 1 0 +18 (IDTR0<1:0>) 0 0 1 1 1 1 +17 These bits allow ±30.5ppm initial trimming range for the crystal 0 1 0 0 0 0 +16 frequency. This is meant to be a coarse adjustment if the range needed is outside that of the IATR control. SeeTable10. The 0 1 0 0 0 1 +15 IDTR0 register should only be changed while the TSE (Temp 0 1 0 0 1 0 +14 Sense Enable) bit is “0”. 0 1 0 0 1 1 +13 TABLE 10. IDTR0 TRIMMING RANGE 0 1 0 1 0 0 +12 IDTR01 IDTR00 TRIMMING RANGE 0 1 0 1 0 1 +11 0 0 Default/Disabled 0 1 0 1 1 0 +10 0 1 +30.5ppm 0 1 0 1 1 1 +9 1 0 0ppm 0 1 1 0 0 0 +8 1 1 -30.5ppm 0 1 1 0 0 1 +7 AGING AND INITIAL ANALOG TRIMMING BITS 0 1 1 0 1 0 +6 (IATR0<5:0>) 0 1 1 0 1 1 +5 The analog trimming register allows +32ppm to -31ppm 0 1 1 1 0 0 +4 adjustment in 1ppm/bit increments. This enables fine frequency adjustment for trimming initial crystal accuracy error or to correct 0 1 1 1 0 1 +3 for aging drift. The IATR0 register should only be changed while the 0 1 1 1 1 0 +2 TSE (Temp Sense Enable) bit is “0”. 0 1 1 1 1 1 +1 TABLE 11. INITIAL AT AND DT SETTING REGISTER 1 0 0 0 0 0 0 ADDR 7 6 5 4 3 2 1 0 1 0 0 0 0 1 -1 0Bh IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 1 0 0 0 1 0 -2 Aging adjustment is normally a few ppm and can be handled by 1 0 0 0 1 1 -3 writing to the IATR section. 1 0 0 1 0 0 -4 TABLE 12. IATR0 TRIMMING RANGE 1 0 0 1 0 1 -5 TRIMMING 1 0 0 1 1 0 -6 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE 1 0 0 1 1 1 -7 0 0 0 0 0 0 +32 1 0 1 0 0 0 -8 0 0 0 0 0 1 +31 1 0 1 0 0 1 -9 0 0 0 0 1 0 +30 1 0 1 0 1 0 -10 0 0 0 0 1 1 +29 1 0 1 0 1 1 -11 0 0 0 1 0 0 +28 1 0 1 1 0 0 -12 0 0 0 1 0 1 +27 1 0 1 1 0 1 -13 0 0 0 1 1 0 +26 1 0 1 1 1 0 -14 0 0 0 1 1 1 +25 1 0 1 1 1 1 -15 0 0 1 0 0 0 +24 1 1 0 0 0 0 -16 0 0 1 0 0 1 +23 1 1 0 0 0 1 -17 0 0 1 0 1 0 +22 1 1 0 0 1 0 -18 0 0 1 0 1 1 +21 1 1 0 0 1 1 -19 0 0 1 1 0 0 +20 1 1 0 1 0 0 -20 0 0 1 1 0 1 +19 FN6659 Rev.3.01 Page 18 of 32 Oct 24, 2019

ISL12022 TABLE 12. IATR0 TRIMMING RANGE (Continued) TEMPERATURE SENSOR ENABLED BIT (TSE) TRIMMING This bit enables the Temperature Sensing operation, including the IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE temperature sensor, A/D converter and AT/DT register adjustment. The default mode after power-up is disabled (TSE = 0). To enable the 1 1 0 1 0 1 -21 operation, TSE should be set to 1 (TSE = 1). When the temperature 1 1 0 1 1 0 -22 sensor is disabled, the initial values for IATR and IDTR registers are used for frequency control. 1 1 0 1 1 1 -23 All changes to the IDTR, IATR, ALPHA and BETA registers must be 1 1 1 0 0 0 -24 made with TSE = 0. After loading the new values, TSE can be 1 1 1 0 0 1 -25 enabled and the new values are used. When TSE is set to 1, the 1 1 1 0 1 0 -26 temperature conversion cycle begins and will end when two temperature conversions are completed. The average of the two 1 1 1 0 1 1 -27 conversions is in the TEMP registers. The total time for 1 1 1 1 0 0 -28 temperature sense and conversion is approximately 22ms from the time TSE = 1 write is completed. 1 1 1 1 0 1 -29 1 1 1 1 1 0 -30 TEMP SENSOR CONVERSION IN BATTERY MODE BIT 1 1 1 1 1 1 -31 (BTSE) This bit enables the Temperature Sensing and Correction in battery Note that setting the IATR to the lowest settings (-31ppm) with mode. BTSE = 0 (default) no conversion, Temp Sensing or the default 32kHz output can cause the oscillator frequency to Compensation in battery mode. BTSE = 1 indicates Temp Sensing become unstable on power-up. The lowest settings for IATR and Compensation enabled in battery mode. The BTSE is disabled should be avoided to insure oscillator frequency integrity. If the when the battery voltage is lower than 2.7V. No temperature lowest IATR settings are needed, then the user is advised to compensation will take place with VBAT<2.7V. disable the FOUT and enable again to insure placing the oscillator in a stable condition. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT (BTSR) ALPHA REGISTER (ALPHA) This bit controls the frequency of Temperature Sensing and TABLE 13. ALPHA REGISTER Correction. BTSR = 0 default mode is every 10 minutes, BTSR=1 is every 1.0 minute. Note that BTSE has to be enabled in both ADDR 7 6 5 4 3 2 1 0 cases. See Table15. 0Ch D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND CORRECTION BIT The Alpha variable is 8 bits and is defined as the temperature coefficient of Crystal from -40°C to T0, or the Alpha Cold (There BTSE BTSR TC PERIOD IN BATTERY MODE is an Alpha Hot register that must be programmed as well). It is 0 0 OFF normally given in units of ppm/°C2, with a typical value of - 0.034. The ISL12022 device uses a scaled version of the 0 1 OFF absolute value of this coefficient in order to get an integer value. 1 0 10 Minutes Therefore, Alpha<7:0> is defined as the (|Actual Alpha Value| x 1 1 1 Minute 2048) and converted to binary. For example, a crystal with Alpha of -0.034ppm/°C2 is first scaled (|2048*(-0.034)| = 70d) and The temperature measurement conversion time is the same for then converted to a binary number of 01000110b. battery mode as for VDD mode, approximately 22ms. The battery The practical range of Actual Alpha values is from mode current will increase during this conversion time to -0.020 to -0.060. typically 68µA. The average increase in battery current is much lower than this due to the small duty cycle of the ON-time versus The ALPHA register should only be changed while the TSE (Temp OFF-time for the conversion. Sense Enable) bit is “0”. Note that both the ALPHA and the ALPHA Hot registers need to be programmed with values for full To figure the average increase in battery current, we take the range temperature compensation. change in current times the duty cycle. For the 1 minute temperature period the average current is shown in Equation1: BETA Register (BETA) 0.022s I =------------------68A= 250nA (EQ. 1) BAT 60s TABLE 14. For the 10 minute temperature period the average current is ADDR 7 6 5 4 3 2 1 0 shown in Equation2: 0Dh TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 0.022s I =------------------68A= 25nA (EQ. 2) BAT 600s FN6659 Rev.3.01 Page 19 of 32 Oct 24, 2019

ISL12022 If the application has a stable temperature environment that TABLE 16. BETA VALUES (Continued) doesn’t change quickly, the 10 minute option will work well and BETA<4:0> AT STEP ADJUSTMENT the backup battery lifetime impact is minimized. If quick temperature variations are expected (multiple cycles of more 10111 1.5000 than 10° within an hour), then the 1 minute option should be 11000 1.5625 considered and the slightly higher battery current figured into overall battery life. 11001 1.6250 11010 1.6875 GAIN FACTOR OF AT BIT (BETA<4:0>) 11011 1.7500 Beta is specified to take care of the Cm variations of the crystal. Most crystals specify Cm around 2.2fF. For example, if Cm>2.2fF, 11100 1.8125 the actual AT steps may reduce from 1ppm/step to 11101 1.8750 approximately 0.80ppm/step. Beta is then used to adjust for this variation and restore the step size to 1ppm/step. 11110 1.9375 BETA values are limited in the range from 01000 to 11111 as 11111 2.0000 shown in Table16. To use Table16, the device is tested at two AT settings as shown in Equation3: Final Analog Trimming Register (FATR) BETAVALUES = ATmax–ATmin/63 (EQ. 3) This register shows the final setting of AT after temperature correction. It is read-only; the user cannot overwrite a value to this where: register. This value is accessible as a means of monitoring the AT(max) = FOUT in ppm (at AT = 00H) and temperature compensation function. See Table17. AT(min) = FOUT in ppm (at AT = 3FH). TABLE 17. FINAL ANALOG TRIMMING REGISTER The BETA VALUES result is indexed in the right hand column and ADDR 7 6 5 4 3 2 1 0 the resulting Beta factor (for the register) is in the same row in the left column. 0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 The value for BETA should only be changed while the TSE (Temperature Sense Enable) bit is “0”. The procedure for writing Final Digital Trimming Register (FDTR) the BETA register involves two steps. First, write the new value of This Register shows the final setting of DT after temperature BETA with TSE = 0. Then write the same value of BETA with correction. It is read-only; the user cannot overwrite a value to TSE=1. This will insure the next temperature sense cycle will use this register. The value is accessible as a means of monitoring the new BETA value. the temperature compensation function. The corresponding clock adjustment values are shown in Table19. The DT setting TABLE 16. BETA VALUES has both positive and negative settings to adjust for any offset in BETA<4:0> AT STEP ADJUSTMENT the crystal. 01000 0.5000 . TABLE 18. FINAL DIGITAL TRIMMING REGISTER 00111 0.5625 ADDR 7 6 5 4 3 2 1 0 00110 0.6250 0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 00101 0.6875 TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL 00100 0.7500 TRIMMING REGISTER 00011 0.8125 FDTR<4:0> DECIMAL ppm ADJUSTMENT 00010 0.8750 00000 0 0 00001 0.9375 00001 1 30.5 00000 1.0000 00010 2 61 10000 1.0625 00011 3 91.5 10001 1.1250 00100 4 122 10010 1.1875 00101 5 152.5 10011 1.2500 00110 6 183 10100 1.3125 00111 7 213.5 10101 1.3750 01000 8 244 10110 1.4375 01001 9 274.5 FN6659 Rev.3.01 Page 20 of 32 Oct 24, 2019

ISL12022 TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL Following are examples of both Single Event and periodic TRIMMING REGISTER (Continued) Interrupt Mode alarms. FDTR<4:0> DECIMAL ppm ADJUSTMENT Example 1 01010 10 305 • Alarm set with single interrupt (IM = ”0”) 10000 0 0 • A single alarm will occur on January 1 at 11:30 a.m. 10001 -1 -30.5 • Set Alarm registers as follows: 10010 -2 -61 BIT ALARM 10011 -3 -91.5 REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION 10100 -4 -122 SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled 10101 -5 -152.5 MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, 10110 -6 -183 enabled HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, 10111 -7 -213.5 enabled 11000 -8 -244 DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, 11001 -9 -274.5 enabled 11010 -10 -305 MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled ALARM Registers (10h to 15h) DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable After these registers are set, an alarm will be generated when the bit (enable = “1”). These enable bits specify which alarm RTC advances to exactly 11:30 a.m. on January 1 (after seconds registers (seconds, minutes, etc.) are used to make the changes from 59 to 00) by setting the ALM bit in the status register comparison. Note that there is no alarm byte for year. to “1” and also bringing the IRQ/FOUT output low. The alarm function works as a comparison between the alarm Example 2 registers and the RTC registers. As the RTC advances, the alarm • Pulsed interrupt once per minute (IM = ”1”) will be triggered once a match occurs between the alarm registers • Interrupts at one minute intervals when the seconds register is and the RTC registers. Any one alarm register, multiple registers, or at 30s. all registers can be enabled for a match. • Set Alarm registers as follows: There are two alarm operation modes: Single Event and periodic Interrupt Mode: BIT ALARM •Single Event Mode is enabled by setting the bit 7 on any of the REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0”, and SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, disabling the frequency output. This mode permits a one-time enabled match between the Alarm registers and the RTC registers. MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled Once this match occurs, the ALM bit is set to “1” and the IRQ/FOUT output will be pulled low and will remain low until HRA0 0 0 0 0 0 0 0 0 00h Hours disabled the ALM bit is reset. This can be done manually or by using the DTA0 0 0 0 0 0 0 0 0 00h Date disabled auto-reset feature. MOA0 0 0 0 0 0 0 0 0 00h Month disabled •Interrupt Mode is enabled by setting the bit 7 on any of the DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1”, and disabling the frequency output. The IRQ/FOUT output will now Once the registers are set, the following waveform will be seen at be pulsed each time an alarm occurs. This means that once IRQ/FOUT: the interrupt mode alarm is set, it will continue to alarm for RTC AND ALARM REGISTERS ARE BOTH “30s” each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in microcontroller applications such as security cameras or utility meter reading. To clear a single event alarm, the ALM bit in the status register 60s must be set to “0” with a write. Note that if the ARST bit is set to1 (address 08h, bit 7), the ALM bit will automatically be FIGURE 14. IRQ/FOUT WAVEFORM cleared when the status register is read. Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared. FN6659 Rev.3.01 Page 21 of 32 Oct 24, 2019

ISL12022 Time Stamp V to Battery Registers (TSV2B) DST Control Registers (DSTCR) DD The TSV2B Register bytes are identical to the RTC register bytes, 8 bytes of control registers have been assigned for the Daylight except they do not extend beyond the Month. The Time Stamp Savings Time (DST) functions. DST beginning (set Forward) time captures the FIRST VDD to Battery Voltage transition time, and will is controlled by the registers DstMoFd, DstDwFd, DstDtFd, and not update upon subsequent events, until cleared (only the first DstHrFd. DST ending time (set Backward or Reverse) is controlled event is captured before clearing). Set CLRTS = 1 to clear this by DstMoRv, DstDwRv, DstDtRv and DstHrRv. register (Add 09h, PWR_VDD register). Tables20 and 21 describe the structure and functions of the DSTCR. Note that the time stamp registers are cleared to all “0”, DST FORWARD REGISTERS (20H TO 23H) including the month and day, which is different from the RTC and alarm registers (those registers default to 01h). This is the DST forward is controlled by the following DST Registers: indicator that no time stamping has occurred since the last clear DST Enable or initial power-up. Once a time stamp occurs, there will be a non- zero time stamp. DSTE is the DST Enabling Bit located in Bit 7 of register 20h (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon Time Stamp Battery to V Registers (TSB2V) DD powering up for the first time (including battery), the DSTE bit The Time Stamp Battery to VDD Register bytes are identical to defaults to “0”. When DSTE is set to “1” the RTC time must be at the RTC register bytes, except they do not extend beyond Month. least one hour before the scheduled DST time change for the The Time Stamp captures the LAST transition of VBAT to VD (only correction to take place. When DSTE is set to “0”, the DSTADJ bit the last event of a series of power-up/down events is retained). in the Status Register automatically resets to “0”. Set CLRTS = 1 to clear this register (Add 09h, PWR_VDD register). DST Month Forward DstMoFd sets the Month that DST starts. The format is the same as for the RTC register month, from 1 to 12. The default value for the DST begin month is 00h. TABLE 20. DST FORWARD REGISTERS ADDRESS FUNCTION 7 6 5 4 3 2 1 0 20h Month Forward DSTE 0 0 MoFd20 MoFd13 MoFd12 MoFd11 MoFd10 21h Day Forward 0 DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10 22h Date Forward 0 0 DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10 23h Hour Forward 0 0 HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10 TABLE 21. DST REVERSE REGISTERS ADDRESS NAME 7 6 5 4 3 2 1 0 24h Month Reverse 0 0 0 MoRv20 MoRv13 MoRv12 MoRv11 MoRv10 25h Day Reverse 0 DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10 26h Date Reverse 0 0 DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10 27h Hour Reverse 0 0 HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10 FN6659 Rev.3.01 Page 22 of 32 Oct 24, 2019

ISL12022 DST Day/Week Forward DST Date Reverse DstDwFd contains both the Day of the Week and the Week of the DstDtRv controls which Date DST ends. The format for the Date is Month data for DST Forward control. DST can be controlled either the same as for the RTC register, from 1 to 31. The default value by actual date or by setting both the Week of the month and the for DST Date Reverse is 00h. The DstDtRv is only effective if the Day of the Week. DstDwFdE sets the priority of the Day/Week DwRvE = 0. over the Date. For DstDwFdE = 1, Day/Week is the priority. You DST Hour Reverse must have the correct Day of Week entered in the RTC registers for the Day/Week correction to work properly. DstHrRv controls the hour that DST ends. The RTC hour and DstHrFd registers have the same formats except there is no • Bits 0, 1, 2 contain the Day of the week information which sets Military bit for DST hour. The user sets the DST hour with the the Day of the Week that DST starts. Note that Day of the week same format as used for the RTC hour (AM/PM or MIL) but counts from 0 to 6, like the RTC registers. The default for the without the MIL bit, and the DST will still advance as if the MIL bit DST Forward Day of the Week is 00h (normally Sunday). were there. The default value for DST hour Reverse is 00h. • Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST starts. The range is from 1 to 5, and Week 7 TEMP Registers (TEMP) is used to indicate the last week of the month. The default for The temperature sensor produces an analog voltage output the DST Forward Week of the Month is 00h. which is input to an A/D converter and produces a 10-bit DST Date Forward temperature value in degrees Kelvin. TK07:00 are the LSBs of the DstDtfd controls which Date DST begins. The format for the Date code, and TK09:08 are the MSBs of the code. The temperature is the same as for the RTC register, from 1 to 31. The default result is actually the average of two successive temperature value for DST forward date is 00h. DstDtFd is only effective if measurements to produce greater resolution for the temperature DstDwFdE = 0. control. The output code can be converted to degrees Centigrade (°C) by first converting from binary to decimal, dividing by 2, and DST Hour Forward then subtracting 273d, as shown in Equation4: DstHrFd controls the hour that DST begins. The RTC hour and Temperature in °C = [(TK <9:0>)/2] - 273 (EQ. 4) DstHrFd registers have the same formats except there is no Military bit for DST hour. The user sets the DST hour with the The practical range for the temp sensor register output is from 446d same format as used for the RTC hour (AM/PM or MIL) but to 726d, or -50°C to +90°C. The temperature compensation without the MIL bit, and the DST will still advance as if the MIL bit function is only guaranteed over -40°C to +85°C. The TSE bit must were there. The default value for DST hour Forward is 00h. be set to “1” to enable temperature sensing. DST REVERSE REGISTERS (24H TO 27H) TABLE 22. DST end (reverse) is controlled by the following DST Registers: TEMP 7 6 5 4 3 2 1 0 DST Month Reverse TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 DstMoRv sets the Month that DST ends. The format is the same as for the RTC register month, from 1 to 12. The default value for TK0M 0 0 0 0 0 0 TK09 TK08 the DST end month is October (10h). NPPM Registers (NPPM) DST Day/Week Reverse The NPPM value is exactly 2x the net correction required to bring the DstDwRv contains both the Day of the Week and the Week of the oscillator to 0ppm error. The value is the combination of oscillator Month data for DST Reverse control. DST can be controlled either Initial Correction (IPPM) and crystal temperature dependent by actual date or by setting both the Week of the month and the correction (CPPM). Day of the Week. DstDwRvE sets the priority of the Day/Week over the Date. For DstDwRvE = 1, Day/Week is the priority. You IPPM is used to compensate the oscillator offset at room must have the correct Day of Week entered in the RTC registers temperature and is controlled by the ITR0 and BETA registers, for the Day/Week correction to work properly. which are fixed during factor test. • Bits 0, 1, 2 contain the Day of the week information which sets The CPPM compensates the oscillator frequency fluctuation over the Day of the Week that DST ends. Note that Day of the week temperature. It is determined by the temperature (T), crystal counts from 0 to 6, like the RTC registers. The default for the curvature parameter (ALPHA), and crystal turnover temperature DST Reverse Day of the Week is 00h (normally Sunday). (XT0). T is the result of the temp sensor/ADC conversion, whose decimal result is 2x the actual temperature in Kelvin. ALPHA is • Bits 3, 4, 5 contain the Week of the Month information that sets the week that DST ends. The range is from 1 to 5, and from either the ALPHA (cold) or ALPHAH (hot) register depending Week 7 is used to indicate the last week of the month. The on T, and XT0 is from the XT0 register. default for the DST Reverse Week of the Month is 00h. FN6659 Rev.3.01 Page 23 of 32 Oct 24, 2019

ISL12022 NPPM is governed by Equation5: TABLE 24. XT0 VALUES (Continued) 2 NPPM = IPPMITRO,BETA+ALPHAT-T0 XT<4:0> TURNOVER TEMPERATURE NPPM = IPPM+CPPM 00001 25.5 2 NPPM = IPPM+A-----L----P----H-----A------------T-----–-----T----0-------- (EQ. 5) 00000 25.0 4096 10000 25.0 where: 10001 24.5 ALPHA = 2048 10010 24.0 T is the reading of the ADC, result is 2 x temperature in degrees 10011 23.5 Kelvin. 10100 23.0 T = 2298+XT0 (EQ. 6) 10101 22.5 or T = 596+XT0 10110 22.0 Note that NPPM can also be predicted from the FATR and FDTR register by the relationship (all values in decimal): 10111 21.5 NPPM = 2*(BETA*FATR - (FDTR-16)) 11000 21.0 11001 20.5 XT0 Registers (XT0) 11010 20.0 TURNOVER TEMPERATURE (XT<3:0>) 11011 19.5 The apex of the Alpha curve occurs at a point called the turnover 11100 19.0 temperature, or XT0. Crystals normally have a turnover temperature between +20°C and +30°C, with most occurring 11101 18.5 near +25°C. 11110 18.0 TABLE 23. TURNOVER TEMPERATURE 11111 17.5 ADDR 7 6 5 4 3 2 1 0 ALPHA Hot Register (ALPHAH) 2Ch 0 0 0 XT4 XT3 XT2 XT1 XT0 TABLE 25. ALPHAH REGISTER The ISL12022 allows setting the turnover temperature so that temperature compensation can more exactly fit the curve of a ADDR 7 6 5 4 3 2 1 0 crystal. Table24 shows the values available, with a range from 2Dh D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 +17.5°C to +32.5°C in +0.5°C increments. The default value is 00000b or +25°C. The Alpha Hot variable is 7 bits and is defined as the temperature TABLE 24. XT0 VALUES coefficient of Crystal from the T0 value to +85°C. (both Alpha Hot and Alpha Cold must be programmed to provide full temperature XT<4:0> TURNOVER TEMPERATURE compensation). It is normally given in units of ppm/°C2, with a 01111 32.5 typical value of -0.034. Like the Alpha Cold version, a scaled version of the absolute value of this coefficient is used in order to 01110 32.0 get an integer value. Therefore, AlphaH<7:0> is defined as the 01101 31.5 (|Actual AlphaH Value| x 2048) and converted to binary. For example, a crystal with AlphaH of -0.034ppm/°C2 is first scaled 01100 31 (|2048*(-0.034)| = 70d) and then converted to a binary number 01011 30.5 of 0100110b. 01010 30 The practical range of Actual AlphaH values is from -0.020to-0.060. 01001 29.5 01000 29.0 The ALPHAH register should only be changed while the TSE (Temp Sense Enable) bit is “0”. 00111 28.5 00110 28.0 00101 27.5 00100 27.0 00011 26.5 00010 26.0 FN6659 Rev.3.01 Page 24 of 32 Oct 24, 2019

ISL12022 User Registers (Accessed by indicating START and STOP conditions (see Figure15). On power- up of the ISL12022, the SDA pin is in the input mode. Using Slave Address 1010111x) All I2C interface operations must begin with a START condition, Addresses [00h to 7Fh] which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL12022 continuously monitors the SDA and SCL lines for the These registers are 128 bytes of battery-backed user SRAM. START condition and does not respond to any command until this 2 condition is met (see Figure15). A START condition is ignored I C Serial Interface during the power-up sequence. The ISL12022 supports a bi-directional bus oriented protocol. The All I2C interface operations must be terminated by a STOP protocol defines any device that sends data onto the bus as a condition, which is a LOW to HIGH transition of SDA while SCL is transmitter and the receiving device as the receiver. The device HIGH (see Figure15). A STOP condition at the end of a read controlling the transfer is the master and the device being controlled operation or at the end of a write operation to memory only is the slave. The master always initiates data transfers and provides places the device in its standby mode. the clock for both transmit and receive operations. Therefore, the An acknowledge (ACK) is a software convention used to indicate a ISL12022 operates as a slave device in all applications. successful data transfer. The transmitting device, either master or All communication over the I2C interface is conducted by sending slave, releases the SDA bus after transmitting eight bits. During the MSB of each byte of data first. the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure16). Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for SCL SDA DATA DATA DATA START STOP STABLE CHANGE STABLE FIGURE 15. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER WRITE SIGNALS FROM S THE MASTER T S A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 1 1 0 1 1 1 1 0 0 0 0 0 SIGNALS FROM A A A THE ISL12022 C C C K K K FIGURE 17. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN) FN6659 Rev.3.01 Page 25 of 32 Oct 24, 2019

ISL12022 The ISL12022 responds with an ACK after recognition of a START Read Operation condition followed by a valid Identification Byte, and once again, after successful receipt of an Address Byte. The ISL12022 also A Read operation consists of a three byte instruction, followed by responds with an ACK after receiving a Data Byte of a write one or more Data Bytes (see Figure19). The master initiates the operation. The master must respond with an ACK after receiving operation issuing the following sequence: a START, the Identification a Data Byte of a read operation. byte with the R/W bit set to “0”, an Address Byte, a second START, and a second Identification byte with the R/W bit set to “1”. After Device Addressing each of the three bytes, the ISL12022 responds with an ACK. Then the ISL12022 transmits Data Bytes as long as the master responds Following a start condition, the master must output a Slave Address with an ACK during the SCL cycle following the eighth bit of each Byte. The 7 MSBs are the device identifiers. These bits are byte. The master terminates the read operation (issuing a STOP “1101111” for the RTC registers and “1010111” for the User SRAM. condition) following the last bit of the last Data Byte (see Figure19). The last bit of the Slave Address Byte defines a read or write The Data Bytes are from the memory location indicated by an operation to be performed. When this R/W bit is a “1”, a read internal pointer. This pointer’s initial value is determined by the operation is selected. A “0” selects a write operation (refer to Address Byte in the Read operation instruction, and increments Figure18). by one during transmission of each Data Byte. After reaching the memory location 2Fh, the pointer “rolls over” to 00h, and the After loading the entire Slave Address Byte from the SDA bus, the device continues to output data for each ACK received. ISL12022 compares the device identifier and device select bits with “1101111” or “1010111”. Upon a correct compare, the device Application Section outputs an acknowledge on the SDA line. Following the Slave Byte is a one byte word address. The word Power Supply Considerations address is either supplied by the master device or obtained from an The ISL12022M contains programmed EEPROM registers which internal counter. On power-up, the internal address counter is set to are recalled to volatile RAM registers during initial power-up. address 00h, so a current address read starts at address 00h. When These registers contain DC voltage, frequency and temperature required, as part of a random read, the master must supply the 1 calibration settings. Initial power-up can be either application of Word Address Bytes, as shown in Figure19. VBAT or VDD power, whichever is first. It is important that the In a random read operation, the slave byte in the “dummy write” initial power-up meet the power supply slew rate specification to portion must match the slave byte in the “read” section. For a avoid faulty EEPROM power-up recall. Also, any glitches or low random read of the Control/Status Registers, the slave byte must be voltage DC pauses should be avoided, as these may activate “1101111x” in both places. recall at a low voltage and load erroneous data into the calibration registers. Note that a very slow VDD ramp rate SLAVE 1 1 0 1 1 1 1 R/W (outside data sheet limits) will almost always trigger erroneous ADDRESS BYTE recall and should be avoided entirely. A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS Battery-Backup Details The ISL12022 has automatic switchover to battery-backup when D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE the VDD drops below the VBAT mode threshold. A wide variety of backup sources can be used, including standard and FIGURE 18. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES rechargeable lithium, super capacitors, or regulated secondary sources. The serial interface is disabled in battery-backup, while Write Operation the oscillator and RTC registers are operational. The SRAM register contents are powered to preserve their contents as well. A Write operation requires a START condition, followed by a valid The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind Identification Byte, a valid Address Byte, a Data Byte, and a STOP the temperature compensation only operates for VBAT > 2.7V. condition. After each of the three bytes, the ISL12022 responds Note that the device is not guaranteed to operate with a with an ACK. At this time, the I2C interface enters a standby state. VBAT<1.8V, so the battery should be changed before SIGNALS S S FROM THE T IDENTIFICATION T IDENTIFICATION S MASTER A BYTE WITH ADDRESS A BYTE WITH A A T R R/W = 0 BYTE R R/W = 1 C C O T T K K P SIGNAL AT 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 SDA A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 19. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) FN6659 Rev.3.01 Page 26 of 32 Oct 24, 2019

ISL12022 discharging to that level. It is strongly advised to monitor the low TABLE 26. SUGGESTED SURFACE MOUNT CRYSTALS battery indicators in the status registers and take action to MANUFACTURER PART NUMBER replace discharged batteries. Citizen CM200S If a supercapacitor is used, it is possible that it may discharge to Epson MC-405, MC-406 below 1.8V during prolonged power-down. Once powered up, the device may lose serial bus communications until both VDD and VBAT Raltron RSM-200S are powered down together. To avoid that situation, including SaRonix 32S12 situations where a battery may discharge deeply, the circuit in Ecliptek ECPSM29T-32.768K Figure20 can be used. ECS ECX-306 Fox FSM-327 VDD = 2.7V ISL12022 JBAT DBAT TO 5.5V BAT43W Layout Considerations VDD VBAT +VBAT = 1.8V CIN CBAT TO 3.2V The crystal input at X1 has a very high impedance, and oscillator 0.1µF 0.1µF circuits operating at low frequencies (such as 32.768kHz) are GND known to pick up noise very easily if layout precautions are not followed. Most instances of erratic clocking or large accuracy errors can be traced to the susceptibility of the oscillator circuit to interference from adjacent high speed clock or data lines. Careful FIGURE 20. SUGGESTED BATTERY-BACKUP CIRCUIT layout of the RTC circuit will avoid noise pickup and insure accurate clocking. The diode, DBAT will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. Figure21 shows a suggested layout for the ISL12022 device using The jumper is added as a safeguard should the battery ever need a surface mount crystal. Two main precautions should be followed: to be disconnect from the circuit. • Do not run the serial bus lines or any high speed logic lines in The VDD negative slew rate should be limited to below the data the vicinity of the crystal. These logic level lines can induce noise sheet spec (10V/ms) otherwise battery switchover can be in the oscillator circuit, causing misclocking. delayed, resulting in SRAM contents corruption and oscillator • Add a ground trace around the crystal with one end terminated operation interruption. at the chip ground. This will provide termination for emitted Some applications will require separate supplies for the RTC VDD noise in the vicinity of the RTC device. and the I2C pull-ups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require serial bus communication with the RTC VDD powered down, the SDA pin must be pulled low during the time the RTC VDD ramps down to 0V. Otherwise, the device may lose serial bus communications once VDD is powered up, and will return to normal operation ONLY once VDD and VBAT are both powered down together. Oscillator Crystal Requirements The ISL12022 uses a standard 32.768kHz crystal. Either through hole or surface mount crystals can be used. Table26 lists some FIGURE 21. SUGGESTED LAYOUT FOR ISL12022 AND CRYSTAL recommended surface mount crystals and the parameters of each. This list is not exhaustive and other surface mount devices can be In addition, it is a good idea to avoid a ground plane under the X1 used with the ISL12022 if their specifications are very similar to the and X2 pins and the crystal, as this will affect the load devices listed. The crystal should have a required parallel load capacitance and therefore the oscillator accuracy of the circuit. If capacitance of 12.5pF and an equivalent series resistance of less the ~IRQ/FOUT pin is used as a clock, it should be routed away than 50k. The crystal’s temperature range specification should from the RTC device as well. The traces for the VBAT and VDD pins match the application. Many crystals are rated for -10°C to +60°C can be treated as a ground, and should be routed around the (especially through-hole and tuning fork types), so an appropriate crystal. crystal should be selected if extended temperature range is required. FN6659 Rev.3.01 Page 27 of 32 Oct 24, 2019

ISL12022 Applications Information Normally, the crystal frequency is adjusted at room temperature to zero out the frequency error using the IATRxx register bits Crystal Oscillator Frequency Compensation (initial Analog Trimming). In addition, the IATRxx setting is varied up and down to record the variation in oscillator frequency CRYSTAL CHARACTERISTICS compared to the step change in IATRxx. Once that value is known then the BETA register is used to adjust the step size to be as The ISL12022 device contains a complete system for adjusting close to 1ppm per IATRxx step as possible. After that adjustment the frequency of the crystal oscillator to compensate for is made, then any ISL12022 temperature compensation temperature variation. A typical 32.768kHz crystal used with RTC adjustments will use a 1ppm change for each bit change in the devices has a temperature versus frequency curve, as shown in internal AT adjustment. Figure22. The Digital Trimming (DT) uses clock pulse add/subtract logic to 0 change the RTC timing during temperature compensation. The DT steps are much coarser than the AT steps and are therefore -20 used for large adjustments. The DT steps are 30.5ppm, and the -40 range is from -305ppm to +305ppm. The Frequency Output -60 function will show the clock variation with DT settings, except for M the 32,768Hz setting which only shows the AT control. P -80 P -100 ACTIVE TEMPERATURE COMPENSATION -120 The ISL12022 contains an intelligent logic circuit which takes the temperature sensor digital value as the only input variable. It -140 then uses the register values for the crystal variables  and T0, -160 and combines those with calibration from the BETA and ITR0 -40-30-20-10 0 10 20 30 40 50 60 70 80 registers to produce “Final” values for the AT and DT, known as TEMPERATURE (°C) FATR (Final AT Register) and FDTR (Final DT Register). Those AT FIGURE 22. RTC CRYSTAL TEMPERATURE DRIFT and DT values combine to directly compensate for the temperature error shown in Figure22. The curve in Figure22 follows Equation7: The temperature sensor produces a new value every 60s (or up to 10 minutes in battery mode), which triggers the logic to calculate 2 f = T–T  (EQ. 7) 0 a new AT/DT value set. For every temperature calculation result, there can only be one corresponding AT/DT correction value. Where  is the temperature constant, with a typical value of 0.034 ppm/°C. Measuring Oscillator Accuracy T0 is the turnover temperature of the crystal, which is the apex of The best way to analyze the ISL12022 frequency accuracy is to the parabolic curve. If the two factors  and T0 are known, it is set the IRQ/FOUT pin for a specific frequency, and look at the possible to correct for crystal temperature error to very high output of that pin on a high accuracy frequency counter (at least accuracy. 7 digits accuracy). Note that the IRQ/FOUT is a drain output and will require a pull-up resistor. The crystal will have an initial accuracy error at room temperature, typically specified at ±20°C. The other important characteristic is Using the 1.0Hz output frequency is the most convenient as the the capacitances associated with the crystal. The load capacitance ppm error is as expressed in Equation8: is normally specified at 12.5pF, although it can be lower in some cases. There is also a motional capacitance which affects the ppm error = FOUT–11e6 (EQ. 8) ability of the load capacitance to pull the oscillation frequency, and Other frequencies may be used for measurement but the error it is usually in the range of 2.2fF to 4.0fF. calculation becomes more complex. RTC CLOCK CONTROL When the proper layout guidelines are observed, the oscillator The ISL12022 uses two mechanisms to adjust the RTC clock and should start up in most circuits in less than 1s. When testing RTC correct for the temperature error of the external crystal. circuits, a common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe the waveform. DO The Analog Trimming (AT) adjusts the load capacitance seen by NOT DO THIS! Although in some cases you may see a usable the crystal. Analog switches connect the appropriate capacitance waveform, due to the parasitics (usually 10pF to ground) applied to change the frequency in increments of 1ppm. The adjustment with the scope probe, there will be no useful information in that range for the ISL12022 is +32/-31ppm. waveform other than the fact that the circuit is oscillating. The X2 The AT can be further refined using the BETA register. the BETA output is sensitive to capacitive impedance so the voltage levels register function is to allow for changes in CM (motional and the frequency will be affected by the parasitic elements in the capacitance) which will affect the incremental frequency change scope probe. Use the FOUT output and a frequency counter for the of the AT adjustment. A simple test procedure uses the BETA most accurate results. register to bring the step size back to 1ppm. FN6659 Rev.3.01 Page 28 of 32 Oct 24, 2019

ISL12022 Temperature Compensation Operation For further information on the operation of the ISL12022 and temperature compensated RTC’s, see Intersil Application Note The ISL12022 temperature compensation feature needs to be AN1389, “Using Intersil’s High Accuracy Real Time Clock enabled by the user. This must be done in a specific order as Module”. follows. Daylight Savings Time (DST) Example 1. Read register 0Dh, the BETA register. This register contains the 5-bit BETA trimmed value which is automatically loaded on initial DST involves setting the forward and back times and allowing the power-up. Mask off the 5LSB’s of the value just read. RTC device to automatically advance the time or set the time back. 2. Bit 7 of the BETA register is the master enable control for This can be done for current year, and future years. Many regions temperature sense operation. Set this to “1” to allow have DST rules that use standard months, weeks and time of the continuous temperature frequency correction. Frequency day which permit a pre-programmed, permanent setting. correction will then happen every 60s with VDD applied. Table27 shows the example setup for the ISL12022. 3. Bits 5 and 6 of the BETA register control temperature compensation in battery-backup mode (see Table15). Set the TABLE 27. DST EXAMPLE values for the operation desired. VARIABLE VALUE REGISTER VALUE 4. Write back to register 0Dh making sure not to change the 5 Month Forward and DST Enable April 15h 84h LSB values, and include the desired compensation control bits. Week and Day Forward and select 1st Week and 16h 48h Note that every time the BETA register is written with the TSE Day/Week, not Date Sunday bit= 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the FATR/FDTR registers Date Forward not used 17h 00h (if the temperature changed since the last conversion). Hour Forward 2am 18h 02h Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA Month Reverse October 19h 10h registers, should not be changed. If they must be written be sure Week and Day Reverse and select Last Week and 1Ah 78h to write the same values that are recalled from initial power-up. Day/Week, not Date Sunday The ITR0 register may be written if the user wishes to re-calibrate the oscillator frequency at room temperature for aging or board Date Reverse not used 1Bh 00h mounting. The original recalled value can be re-written if desired Hour Reverse 2am 1Ch 02h after testing. The Enable bit (DSTE) is in the Month forward register, so the BCD value for that register is altered with the additional bit. The Week and Day values along with Week/Day vs Date select bit is in the Week/Day register, so that value is also not straight BCD. Hour and Month are normal BCD, but the Hour doesn’t use the MIL bit since Military time PM values are already discretely different from AM/PM time PM values. The DST reverse setting utilizes the option to select the last week of the month for October, which could have 4 or 5 weeks but needs to have the time change on the last Sunday. Note that the DSTADJ bit in the status register monitors whether the DST forward adjustment has happened. When it is “1”, DST forward has taken place. When it is “0”, then either DST reverse has happened, or it has been reset either by initial power-up or if the DSTE bit has been set to “0”. FN6659 Rev.3.01 Page 29 of 32 Oct 24, 2019

ISL12022 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Oct 24, 2019 FN6659.3.01 Updated links throughout. Added Related Literature section. Updated Ordering information by adding tape and reel information and updating notes. Updated labels on Figures 5 and 9. Added Revision History Updated POD M8.15 to latest revision changes are as follows: -Updated Note 1 changed 1982 to 1994. Updated Disclaimer. FN6659 Rev.3.01 Page 30 of 32 Oct 24, 2019

ISL12022 Package Outline Drawing For the most recent package outline drawing, see M8.15. M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 17. Dimensioning and tolerancing per ANSI Y14.5M-1994. 18. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 19. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 20. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 21. Terminal numbers are shown for reference only. 22. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 23. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 24. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6659 Rev.3.01 Page 31 of 32 Oct 24, 2019

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