DATASHEET ISL12020M FN6667 Low Power RTC with Battery Backed SRAM, Integrated ±5ppm Temperature Rev 6.00 Compensation and Auto Daylight Saving January 9, 2015 The ISL12020M device is a low power Real Time Clock (RTC) Features with an embedded temperature sensor and crystal. Device functions include oscillator compensation, clock/calendar, • Embedded 32.768kHz quartz crystal in the package power fail and low battery monitors, brownout indicator, • 20 Ld DFN package (for SOIC version, refer to the one-time, periodic or polled alarms, intelligent battery backup ISL12022M) switching, Battery Reseal™ function and 128 bytes of • Calendar battery-backed user SRAM. The device is offered in a 20LdDFN module that contains the RTC and an embedded • On-chip oscillator temperature compensation 32.768kHz quartz crystal. The calibrated oscillator provides • 10-bit digital temperature sensor output less than ±5ppm drift across the 0°C to +85°C temperature • 15 selectable frequency outputs range. • Interrupt for alarm or 15 selectable frequency outputs The RTC tracks time with separate registers for hours, minutes and seconds. The calendar registers track date, month, year • Automatic backup to battery or supercapacitor and day of the week and are accurate through 2099, with • VDD and battery status monitors automatic leap year correction. • Battery Reseal™ function to extend battery shelf life Daylight Savings time adjustment is done automatically, using • Power status brownout monitor parameters entered by the user. Power fail and battery monitors offer user-selectable trip levels. The time stamp • Time stamp for battery switchover function records the time and date of switchover from VDD to • 128 Bytes battery-backed user SRAM VBAT power and also from VBAT to VDD power. • I2C-Bus™ Related Literature • RoHS compliant •AN1549, “Addressing Power Issues in Real Time Clock Applications Applications” • Utility meters •AN1389, “Using Intersil’s High Accuracy Real Time Clock Module” • POS equipment • Printers and copiers • Digital cameras 1 X2 X1 20 2 X2 X1 19 3 X2 X1 18 4 X2 X1 17 3.3V 5 X2 X1 16 SCHOTTKY DIODE 6 NC NC 15 0.C1µ1F R1 R2 R3 BAT54 7 VBAT VDD 14 10k 10k 10k BATTERY C2 8 GND IRQ/FOUT 13 3.0V 0.1µF VDD 9 NC SCL 12 SCL MCU 10 NC SDA 11 INTERFACE SDA ISL12020M GND IRQ/FOUT FIGURE 1. TYPICAL APPLICATION CIRCUIT FN6667 Rev 6.00 Page 1 of 34 January 9, 2015

ISL12020M Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC Operating Characteristics - RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power-Down Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 I2C Interface Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SDA vs SCL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Symbol Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Control Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Normal Mode (VDD) to Battery-Backup Mode (VBAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Battery-Backup Mode (VBAT) to Normal Mode (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Brownout Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Battery Level Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Real Time Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Single Event and Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Frequency Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Purpose User SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Real Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Addresses [00h to 06h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Control and Status Registers (CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Addresses [07h to 0Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt Control Register (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial AT and DT setting Register (ITRO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ALPHA Register (ALPHA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BETA Register (BETA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Final Analog Trimming Register (FATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Final Digital Trimming Register (FDTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ALARM Registers (10h to 15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Time Stamp VDD to Battery Registers (TSV2B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Time Stamp Battery to VDD Registers (TSB2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DST Control Registers (DSTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TEMP Registers (TEMP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 NPPM Registers (NPPM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 XT0 Registers (XT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ALPHA Hot Register (ALPHAH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 User Registers (Accessed by Using Slave Address 1010111x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Addresses [00h to 7Fh]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Device Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Application Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power Supply Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FN6667 Rev 6.00 Page 2 of 34 January 9, 2015

ISL12020M Battery-Backup Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Measuring Oscillator Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Temperature Compensation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Daylight Savings Time (DST) Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FN6667 Rev 6.00 Page 3 of 34 January 9, 2015

ISL12020M Block Diagram SDA BUSFDFAER I2C SECONDS SCL SCL INTERFACE COLNOTGRICOL MINUTES BUFFER REGISTERS HOURS X1 DAY OF WEEK CRYSTAL RTC DATE OSCILLATOR DIVIDER X2 MONTH VDD POR FREQUENCY YEAR OUT ALARM CONTROL VTRIP REGISTERS +- SWITCH USER SRAM VBAT INSTUEPRPNLAYL IRQ/FOUT GND TEMPERATURE FREQUENCY SENSOR CONTROL Ordering Information PART NUMBER PART VDD RANGE TEMP RANGE PACKAGE (Notes1, 2, 3) MARKING (V) (°C) (RoHS Compliant) PKG DWG # ISL12020MIRZ ISL 12020MIRZ 2.7 to 5.5 -40 to +85 20 Ld DFN L20.5.5x4.0 ISL12020MIRZ-EVALZ Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL12020M. For more information on MSL please see techbrief TB363. FN6667 Rev 6.00 Page 4 of 34 January 9, 2015

ISL12020M Pin Configuration ISL12020M (20 LD DFN) TOP VIEW X2 1 20 X1 X2 2 19 X1 X2 3 18 X1 X2 4 17 X1 X2 5 16 X1 NC 6 15 NC VBAT 7 14 VDD GND 8 THERMAL 13 IRQ/FOUT PAD NC 9 12 SCL NC 10 11 SDA Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 2, 3, 4, 5, 16, X2 Crystal Connection. The X1 and X2 pins are the input and output, respectively, of an inverting amplifier and are also 17, 18, 19, 20 X1 connected to the internal 32.768kHz quartz crystal, which is the timebase for the real time clock. Compensation circuitry with an internal temperature sensor provides frequency correction to ±5ppm across the temperature range from 0°C to +85°C. The X1 and X2 pins are not to be connected to any other circuitry or power voltages and are best left floating. Do not connect in an application circuit, floating electrical connection. 6, 9, 10, 15 NC No connection. Do not connect to a signal or supply voltage. 7 VBAT Backup Supply. This input provides a backup supply voltage to the device. The VBAT supplies power to the device in the event that the VDD supply fails. This pin can be connected to a battery, a Super Capacitor or tied to ground if not used. See the Battery Monitor parameter in the “Electrical Specifications” table “DC Operating Characteristics - RTC” on page6. 11 SDA Serial Data. The SDA is a bidirectional pin used to transfer data into and out of the device. It has an open-drain output and may be ORed with other open-drain or open collector outputs. The input buffer is always active (not gated) in normal mode. An open-drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz I2C interface speeds. It is disabled when the backup power supply on the VBAT pin is activated. The SDA is a bidirectional pin used to transfer serial data into and out of the device. It has an open-drain output and may be wire OR’ed with other open-drain or open collector outputs. 12 SCL Serial Clock. The SCL input is used to clock all serial data into and out of the device. The input buffer on this pin is always active (not gated). It is disabled when the backup power supply on the VBAT pin is activated to minimize power consumption. 13 IRQ/FOUT Interrupt Output/Frequency Output (Default 32.768kHz frequency output). This dual function pin can be used as an interrupt or frequency output pin. The IRQ/FOUT mode is selected via the frequency out control bits of the control/status register. Multi-functional pin that can be used as interrupt or frequency output pin. The function is set via the configuration register. The output is open drain and requires a pull-up resistor. Interrupt Mode. The pin provides an interrupt signal output. This signal notifies a host processor that an alarm has occurred and requests action. It is an open-drain active low output. Frequency Output Mode. The pin outputs a clock signal, which is related to the crystal frequency. The frequency output is user selectable and enabled via the I2C bus. It is an open-drain output. 14 VDD Power supply. Chip power supply and ground pins. The device will operate with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF capacitor is recommended on the VDD pin to ground. 8 GND Ground Pin Thermal Pad NC No Connection. Do not connect to a signal or supply voltage. FN6667 Rev 6.00 Page 5 of 34 January 9, 2015

ISL12020M Absolute Maximum Ratings Thermal Information Voltage on VDD, VBAT and IRQ/FOUT pins Thermal Resistance (Typical) JA (°C/W) JC (°C/W) (Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V 20 Lead DFN (Notes4, 5) . . . . . . . . . . . . . . 40 3.5 Voltage on SCL and SDA pins Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+85°C (Respect to Ground). . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Voltage on X1 and X2 pins Pb-Free Reflow Profile (Note7). . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 (Respect to Ground, Note6) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.5V ESD Rating Human Body Model (Tested per MIL-STD-883 Method 3014) . . . . >3kV Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V Latch-up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA or 1.5 * VMAX Input Shock Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . .5000g, 0.3ms, 1/2 sine Vibration (Ultrasound cleaning not advised). . . . . . . . . . .20g/10-2000Hz, CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 6. The X1 and X2 pins are connected internally to a crystal and should be a floating electrical connection. 7. The ISL12020M Oscillator Initial Accuracy can change after solder reflow attachment. The amount of change will depend on the reflow temperature and length of exposure. A general rule is to use only one reflow cycle and keep the temperature and time as short as possible. Changes on the order of ±1ppm to ±3ppm can be expected with typical reflow profiles. DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply across the operating temperature range, -40°Cto +85°C. MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note8) (Note9) (Note8) UNITS NOTES VDD Main Power Supply (Note10) 2.7 5.5 V VBAT Battery Supply Voltage (Note10) 1.8 5.5 V 11 IDD1 Supply Current. (I2Cnotactive, VDD = 5V 4.1 15 µA 12, 13 temperature conversion not active, FOUT not active) VDD = 3V 3.5 14 µA 12, 13 IDD2 Supply Current. (I2C Active, Temperature VDD = 5V 200 500 µA 12, 13 Conversion not Active, FOUT not Active) IDD3 Supply Current. (I2CnotActive, VDD = 5V 120 400 µA 12, 13 Temperature Conversion Active, FOUT not Active) IBAT Battery Supply Current VDD = 0V, VBAT = 3V, TA= +25°C 1.0 1.6 µA 12 VDD = 0V, VBAT = 3V 1.0 5.0 µA 12 IBATLKG Battery Input Leakage VDD = 5.5V, VBAT = 1.8V 100 nA ILI Input Leakage Current on SCL VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA ILO I/O Leakage Current on SDA VIL = 0V, VIH = VDD -1.0 ±0.1 1.0 µA VBATM Battery Level Monitor Threshold -100 +100 mV VPBM Brownout Level Monitor Threshold -100 +100 mV VTRIP VBAT Mode Threshold (Note10) 2.0 2.2 2.4 V VTRIPHYS VTRIP Hysteresis 30 mV 15 VBATHYS VBAT Hysteresis 50 mV 15 Fout25°C Oscillator Initial Accuracy VDD = 3.3V, TA = +25°C ±2 ppm 7, 15 FN6667 Rev 6.00 Page 6 of 34 January 9, 2015

ISL12020M DC Operating Characteristics - RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface limits apply across the operating temperature range, -40°Cto +85°C. (Continued) MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note8) (Note9) (Note8) UNITS NOTES FoutT Oscillator Stability vs Temperature VDD = 3.3V, 0°Cto +85°C -5 +5 ppm 7, 15 VDD = 3.3V, -30°Cto +85°C -10 +10 ppm 7, 15 VDD = 3.3V, -40°Cto +85°C -15 +15 ppm 7, 15 FoutV Oscillator Stability vs Voltage 2.7V  VDD  5.5V -3 +3 ppm 15 Temperature Sensor Accuracy VDD = VBAT = 3.3V ±2 °C 15 IRQ/FOUT (OPEN-DRAIN OUTPUT) VOL Output Low Voltage VDD = 5V, IOL = 3mA 0.4 V VDD = 2.7V, IOL = 1mA 0.4 V Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN TYP MAX SYMBOL PARAMETER CONDITIONS (Note8) (Note9) (Note8) UNITS NOTES VDDSR- VDD Negative Slew Rate 10 V/ms 14 VDDSR+ VDD Positive Slew Rate, Minimum .05 V/ms 17 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°Cto+85°C. MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note8) (Note9) (Note8) UNITS NOTES VIL SDA and SCL Input Buffer LOW -0.3 0.3 x VDD V Voltage VIH SDA and SCL Input Buffer HIGH 0.7 x VDD VDD + 0.3 V Voltage Hysteresis SDA and SCL Input Buffer 0.05 x VDD V 15, 16 Hysteresis VOL SDA Output Buffer LOW Voltage, VDD = 5V, IOL = 3mA 0 0.02 0.4 V Sinking 3mA CPIN SDA and SCL Pin Capacitance TA = +25°C, f = 1MHz, 10 pF 15, 16 VDD = 5V, VIN=0V, VOUT = 0V fSCL SCL Frequency 400 kHz tIN Pulse Width Suppression Time at Any pulse narrower than the 50 ns SDA and SCL Inputs max spec is suppressed. tAA SCL Falling Edge to SDA Output SCL falling edge crossing 900 ns Data Valid 30% of VDD, until SDA exits the 30% to 70% of VDD window. tBUF Time the Bus Must be Free Before SDA crossing 70% of VDD 1300 ns the Start of a New Transmission during a STOP condition, to SDA crossing 70% of VDD during the following START condition. tLOW Clock LOW Time Measured at the 30% of VDD 1300 ns crossing. FN6667 Rev 6.00 Page 7 of 34 January 9, 2015

ISL12020M 2 I C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. Boldface limits apply across the operating temperature range, -40°Cto+85°C. (Continued) MIN TYP MAX SYMBOL PARAMETER TEST CONDITIONS (Note8) (Note9) (Note8) UNITS NOTES tHIGH Clock HIGH Time Measured at the 70% of VDD 600 ns crossing. tSU:STA START Condition Setup Time SCL rising edge to SDA 600 ns falling edge. Both crossing 70% of VDD. tHD:STA START Condition Hold Time From SDA falling edge 600 ns crossing 30% of VDD to SCL falling edge crossing 70% of VDD. tSU:DAT Input Data Setup Time From SDA exiting the 30% to 100 ns 70% of VDD window, to SCL rising edge crossing 30% of VDD. tHD:DAT Input Data Hold Time From SCL falling edge 20 900 ns crossing 30% of VDD to SDA entering the 30% to 70% of VDD window. tSU:STO STOP Condition Setup Time From SCL rising edge 600 ns crossing 70% of VDD, to SDA rising edge crossing 30% of VDD. tHD:STO STOP Condition Hold Time From SDA rising edge to SCL 600 ns falling edge. Both crossing 70% of VDD. tDH Output Data Hold Time From SCL falling edge 0 ns crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window. tR SDA and SCL Rise Time From 30% to 70% of VDD. 20 +0.1 x 300 ns 16 Cb tF SDA and SCL Fall Time From 70% to 30% of VDD. 20 +0.1 x 300 ns 16 Cb Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 16 RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by 1 kΩ 16 Off-chip tR and tF. For Cb = 400pF, max is about 2kΩ~2.5kΩ. For Cb = 40pF, max is about 15kΩ~20kΩ NOTES: 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Specified at +25°C. 10. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested. 11. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V. 12. IRQ/FOUT Inactive. 13. VDD > VBAT +VBATHYS 14. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 15. Limits should be considered typical and are not production tested. 16. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification. 17. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only. FN6667 Rev 6.00 Page 8 of 34 January 9, 2015

ISL12020M SDA vs SCL Timing tF tHIGH tLOW tR SCL tSU:DAT tSU:STA tHD:DAT tSU:STO tHD:STA SDA (INPUT TIMING) tAA tDH tBUF SDA (OUTPUT TIMING) Symbol Table EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V WAVEFORM INPUTS OUTPUTS 5.0V FOR VOL= 0.4V Must be steady Will be steady 1533Ω SDA AND IOL = 3mA AND IRQ/FOUT May change Will change 100pF from LOW from LOW to HIGH to HIGH May change Will change FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE from HIGH from HIGH to LOW to LOW WITH VDD = 5.0V Don’t Care: Changing: Changes Allowed State Not Known N/A Center Line is High Impedance Typical Performance Curves Temperature is +25°C unless otherwise specified. 1050 1600 1000 1400 A) n ENT ( 950 A) 1200 VBAT = 5.5V R n UR 900 (AT 1000 C B AT I VBAT = 3.0V B V 850 800 VBAT = 1.8V 800 600 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 -40 -20 0 20 40 60 80 VBAT VOLTAGE (V) TEMPERATURE (°C) FIGURE 3. IBAT vs VBAT FIGURE 4. IBAT vs TEMPERATURE FN6667 Rev 6.00 Page 9 of 34 January 9, 2015

ISL12020M Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 6 4.4 4.2 5 VBAT = 5.5V 4.0 µA) A) 3.8 (D1 4 (µ1 3.6 D D I D I 3 VDD = 2.7V 3.4 VDD = 3.3V 3.2 2 3.0 -40 -20 0 20 40 60 80 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE (°C) VDD (V) FIGURE 5. IDD1 vs TEMPERATURE FIGURE 6. IDD1 vs VDD 5 6 m) 4 p p 3 R ( 5 VDD = 5.5V O 2 R R 1 NCY E -10 VDD = 5.5V VDD = 2.7V (µA)DD 4 EQUE -2 I 3 VDD = 2.7V VDD = 3.3V R -3 FT -4 VDD = 3.3V U O -5 2 F -40 -20 0 20 40 60 80 0.01 0.1 1 10 100 1k 10k 1M TEMPERATURE (°C) FREQUENCY OUTPUT (Hz) FIGURE 7. OSCILLATOR ERROR vs TEMPERATURE FIGURE 8. FOUT vs IDD 5.5 110 100 5.0 T (µA) 4.5 FOUT = 32kHz 8900 VBAT = 5.5V URREN 4.0 (µA)AT 6700 C B Y 3.5 FOUT = 1Hz AND 64Hz I 50 VBAT = 3.0V L P UP 3.0 40 VBAT = 1.8V S 30 2.5 20 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 9. IDD vs TEMPERATURE, 3 DIFFERENT FOUT FIGURE 10. IBAT WITH TSE = 1, BTSE = 1 vs TEMPERATURE FN6667 Rev 6.00 Page 10 of 34 January 9, 2015

ISL12020M Typical Performance Curves Temperature is +25°C unless otherwise specified. (Continued) 110 80 62.5ppm 100 m) 60 p p 90 VDD = 5.5V E ( 40 32ppm VDD = 3.3V NG 20 (µA)D 7800 Y CHA 0 0ppm ID NC -20 -31ppm 60 E VBAT = 2.7V QU -40 50 RE -60 -61.5ppm F 40 -80 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 11. IDD with TSE = 1 vs TEMPERATURE FIGURE 12. OSCILLATOR CHANGE vs TEMPERATURE AT DIFFERENT AGING SETTINGS (IATR) (BETA SET FOR 1ppm STEPS) General Description Functional Description The ISL12020M device is a low power Real Time Clock (RTC) with Power Control Operation embedded temperature sensor and crystal. It contains crystal frequency compensation circuitry over the temperature range of The power control circuit accepts a VDD and a VBAT input. Many 0°C to 85°C good to ±5ppm accuracy. It also contains a types of batteries can be used with Intersil RTC products. For clock/calendar with Daylight Savings Time (DST) adjustment, example, 3.0V or 3.6V Lithium batteries are appropriate and power fail and low battery monitors, brownout indicator, 1 periodic battery sizes are available that can power the ISL12020M for up or polled alarm, intelligent battery-backup switching and 128 to 10 years. Another option is to use a Super Capacitor for Bytes of battery-backed user SRAM. applications where VDD is interrupted for up to a month. See the “Application Section” on page28 for more information. The oscillator uses an internal 32.768kHz crystal. The real time clock tracks time with separate registers for hours, minutes and Normal Mode (VDD) to Battery-Backup Mode seconds. The device has calendar registers for date, month, year (V ) BAT and day of the week. The calendar is accurate through 2099, with automatic leap year correction. In addition, both the To transition from the VDD to VBAT mode, both of the following conditions must be met: ISL12020M could be programmed for automatic Daylight Savings Time (DST) adjustment by entering local DST Condition 1: information. VDD < VBAT - VBATHYS The ISL12020M’s alarm can be set to any clock/calendar value where VBATHYS  50mV for a match. For example, every minute, every Tuesday or at Condition 2: 5:23AM on March 21. The alarm status is available by checking the Status Register, or the device can be configured to provide a VDD < VTRIP hardware interrupt via the IRQ/FOUT pin. There is a repeat mode where VTRIP  2.2V for the alarm allowing a periodic interrupt every minute, every Battery-Backup Mode (V ) to Normal Mode hour, every day, etc. BAT (V ) The device also offers a backup power input pin. This VBAT pin DD allows the device to be backed up by battery or Super Capacitor The ISL12020M device will switch from the VBAT to VDD mode with automatic switchover from VDD to VBAT. The ISL12020M when one of the following conditions occurs: device is specified for VDD = 2.7V to 5.5V and the clock/calendar Condition 1: portion of the device remains fully operational in battery-backup mode down to 1.8V (Standby Mode). The VBAT level is monitored VDD > VBAT + VBATHYS and reported against preselected levels. The first report is where VBATHYS 50mV registered when the VBAT level falls below 85% of nominal level, Condition 2: the second level is set for 75%. Battery levels are stored in PWR_VBAT registers. VDD > VTRIP + VTRIPHYS where VTRIPHYS  30mV The ISL12020M offers a “Brownout” alarm once the VDD falls below a preselected trip level. This allows system Micro to save These power control situations are illustrated in Figures13 and vital information to memory before complete power loss. There 14. are six VDD levels that could be selected for initiation of the Brownout alarm. FN6667 Rev 6.00 Page 11 of 34 January 9, 2015

ISL12020M 85% and 75%, the LBAT85 bit is set in the status register. When the level drops below 75%, both LBAT85 and LBAT75 bits are set BATTERY-BACKUP in the status register. MODE VDD The battery level monitor is not functional in battery backup mode. VTRIP 2.2V In order to read the monitor bits after powering up VDD, instigate a VBAT 1.8V battery level measurement, which is set by setting the TSE bit to "1" (BETA register) and then read the bits. VBAT - VBATHYS VBAT + VBATHYS There is a Battery Time Stamp Function available. Once the VDD is low enough to enable switchover to the battery, the RTC time/date are written into the TSV2B register. This information can be read FIGURE 13. BATTERY SWITCHOVER WHEN VBAT<VTRIP from the TSV2B registers to discover the point in time of the VDD power-down. If there are multiple power-down cycles before reading these registers, the first values stored in these registers BATTERY-BACKUP will be retained. These registers will hold the original power-down MODE value until they are cleared by setting CLRTS = 1 to clear the VDD registers. VBAT 3.0V The normal power switching of the ISL12020M is designed to VTRIP 2.2V switch into battery-backup mode only if the VDD power is lost. This will ensure that the device can accept a wide range of VTRIP VTRIP + VTRIPHYS backup voltages from many types of sources while reliably switching into backup mode. Note that the ISL12020M is not guaranteed to operate with FIGURE 14. BATTERY SWITCHOVER WHEN VBAT>VTRIP VBAT< 1.8V. If the battery voltage is expected to drop lower than this minimum, correct operation of the device, especially after a The I2C bus is deactivated in battery-backup mode to reduce VDD power-down cycle, is not guaranteed. power consumption. Aside from this, all RTC functions are operational during battery-backup mode. Except for SCL and SDA, The minimum VBAT to insure SRAM is stable is 1.0V. Below that, all the inputs and outputs of the ISL12020M are active during the SRAM may be corrupted when VDD power resumes. battery-backup mode unless disabled via the control register. Real Time Clock Operation The device Time Stamps the switchover from VDD to VBAT and VBAT to VDD and the time is stored in tSV2B and tSB2V registers The Real Time Clock (RTC) uses an integrated 32.768kHz quartz respectively. If multiple VDD power-down sequences occur before crystal to maintain an accurate internal representation of status is read, the earliest VDD to VBAT power-down time is stored second, minute, hour, day of week, date, month and year. The and the most recent VBAT to VDD time is stored. RTC also has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls Temperature conversion and compensation can be enabled in 24-hour or AM/PM format. When the ISL12020M powers up battery-backup mode. Bit BTSE in the BETA register controls this operation, as described in “BETA Register (BETA)” on page20. after the loss of both VDD and VBAT, the clock will not begin incrementing until at least one byte is written to the clock Power Failure Detection register. The ISL12020M provides a Real Time Clock Failure Bit (RTCF) to Single Event and Interrupt detect total power failure. It allows users to determine if the The alarm mode is enabled via the MSB bit. Choosing single device has powered up after having lost all power to the device event or interrupt alarm mode is selected via the IM bit. Note that (both VDD and VBAT). when the frequency output function is enabled, the alarm Brownout Detection function is disabled. The ISL12020M monitors the VDD level continuously and The standard alarm allows for alarms of time, date, day of the provides warning if the VDD level drops below prescribed levels. week, month and year. When a time alarm occurs in single There are six (6) levels that can be selected for the trip level. event mode, the IRQ/FOUT pin will be pulled low and the alarm These values are 85% below popular VDD levels. The LVDD bit in status bit (ALM) will be set to “1”. the Status Register will be set to “1” when brownout is detected. The pulsed Interrupt mode allows for repetitive or recurring alarm Note that the I2C serial bus remains active unless the Battery functionality. Hence, once the alarm is set, the device will VTRIP levels are reached. continue to alarm for each occurring match of the alarm and present time. Thus, it will alarm as often as every minute (if only Battery Level Monitor the nth second is set) or as infrequently as once a year (if at least The ISL12020M has a built in warning feature once the Back Up the nth month is set). During pulsed Interrupt mode, the battery level drops first to 85% and then to 75% of the battery’s IRQ/FOUT pin will be pulled low for 250ms and the alarm status nominal VBAT level. When the battery voltage drops to between bit (ALM) will be set to “1”. FN6667 Rev 6.00 Page 12 of 34 January 9, 2015

ISL12020M The ALM bit can be reset by the user or cleared automatically Register Descriptions using the auto reset mode (see ARST bit). The alarm function can be enabled/disabled during battery-backup mode using the The battery-backed registers are accessible following a slave FOBATB bit. For more information on the alarm, please see byte of “1101111x” and reads or writes to addresses [00h:2Fh]. “ALARM Registers (10h to 15h)” on page22. The defined addresses and default values are described in Table1. The battery backed general purpose SRAM has a Frequency Output Mode different slave address (1010111x), so it is not possible to The ISL12020M has the option to provide a clock output signal read/write that section of memory while accessing the registers. using the IRQ/FOUT open-drain output pin. The frequency output REGISTER ACCESS mode is set by using the FO bits to select 15 possible output frequency values from 1/32Hz to 32kHz. The frequency output The contents of the registers can be modified by performing a byte can be enabled/disabled during battery-backup mode using the or a page write operation directly to any register address. FOBATB bit. The registers are divided into 8 sections. They are: General Purpose User SRAM 1. Real Time Clock (7 bytes): Address 00h to 06h. The ISL12020M provides 128 bytes of user SRAM. The SRAM will 2. Control and Status (9 bytes): Address 07h to 0Fh. continue to operate in battery-backup mode. However, it should 3. Alarm (6 bytes): Address 10h to 15h. be noted that the I2C bus is disabled in battery-backup mode. 4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah. 2 I C Serial Interface 5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh. The ISL12020M has an I2C serial bus interface that provides 6. Daylight Savings Time (8 bytes): 20h to 27h. access to the control and status registers and the user SRAM. 7. TEMP (2 bytes): 28h to 29h The I2C serial interface is compatible with other industry I2C 8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh serial bus protocols using a bidirectional data signal (SDA) and a 9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch clock signal (SCL). 10.Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh Oscillator Compensation 11.Scratch Pad (2 bytes): Address 2Eh and 2Fh The ISL12020M provides both initial timing correction and Write capability is allowable into the RTC registers (00h to 06h) temperature correction due to variation of the crystal oscillator. only when the WRTC bit (bit 6 of address 08h) is set to “1”. A Analog and digital trimming control is provided for initial multi-byte read or write operation should be limited to one adjustment and a temperature compensation function is provided section per operation for best RTC timekeeping performance. to automatically correct for temperature drift of the crystal. Initial A register can be read by performing a random read at any values for the initial AT and DT settings (ITR0), temperature address at any time. This returns the contents of that register coefficient (ALPHA), crystal capacitance (BETA), as well as the location. Additional registers are read by performing a sequential crystal turn-over temperature (XTO), are preset internally and read. For the RTC and Alarm registers, the read instruction recalled to RAM registers on power-up. These values can be latches all clock registers into a buffer, so an update of the clock overwritten by the user although this is not suggested as the does not change the time being read. At the end of a read, the resulting temperature compensation performance will be master supplies a stop condition to end the operation and free compromised. The compensation function can be the bus. After a read, the address remains at the previous enabled/disabled at any time and can be used in battery mode as address +1 so the user can execute a current address read and well. continue reading the next register. When the previous address is 2Fh, the next address will wrap around to 00h. It is not necessary to set the WRTC bit prior to writing into the control and status, alarm and user SRAM registers. FN6667 Rev 6.00 Page 13 of 34 January 9, 2015

ISL12020M TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE CHANGED BY THE USER) BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 00h RTC SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0 to 59 00h 01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0 to 59 00h 02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0 to 23 00h 03h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1 to 31 01h 04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1 to 12 01h 05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0 to 99 00h 06h DW 0 0 0 0 0 DW2 DW1 DW0 0 to 6 00h 07h CSR SR BUSY OSCF DSTADJ ALM LVDD LBAT85 LBAT75 RTCF N/A 01h 08h INT ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 N/A 01h 09h PWR_VDD CLRTS D D D D VDDTrip2 VDDTrip1 VDDTrip0 N/A 00h 0Ah PWR_VBAT RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A 00h 0Bh ITRO IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 N/A XXh 0Ch ALPHA D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A XXh 0Dh BETA TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 N/A XXh 0Eh FATR 0 0 FFATR5 FATR4 FATR3 FATR2 FATR1 FATR0 N/A 00h 0Fh FDTR 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 N/A 00h 10h ALARM SCA0 ESCA0 SCA022 SCA021 SCA020 SCA013 SCA012 SCA011 SCA010 00 to 59 00h 11h MNA0 EMNA0 MNA022 MNA021 MNA020 MNA013 MNA012 MNA011 MNA010 00 to 59 00h 12h HRA0 EHRA0 D HRA021 HRA020 HRA013 HRA012 HRA011 HRA010 0 to 23 00h 13h DTA0 EDTA0 D DTA021 DTA020 DTA013 DTA012 DTA011 DTA010 01 to 31 00h 14h MOA0 EMOA00 D D MOA020 MOA013 MOA012 MOA011 MOA010 01 to 12 00h 15h DWA0 EDWA0 D D D D DWA02 DWA01 DWA00 0 to 6 00h 16h TSV2B VSC 0 VSC22 VSC21 VSC20 VSC13 VSC12 VSC11 VSC10 0 to 59 00h 17h VMN 0 VMN22 VMN21 VMN20 VMN13 VMN12 VMN11 VMN10 0 to 59 00h 18h VHR VMIL 0 VHR21 VHR20 VHR13 VHR12 VHR11 VHR10 0 to 23 00h 19h VDT 0 0 VDT21 VDT20 VDT13 VDT12 VDT11 VDT10 1 to 31 00h 1Ah VMO 0 0 0 VMO20 VMO13 VMO12 VMO11 VMO10 1 to 12 00h 1Bh TSB2V BSC 0 BSC22 BSC21 BSC20 BSC13 BSC12 BSC11 BSC10 0 to 59 00h 1Ch BMN 0 BMN22 BMN21 BMN20 BMN13 BMN12 BMN11 BMN10 0 to 59 00h 1Dh BHR BMIL 0 BHR21 BHR20 BHR13 BHR12 BHR11 BHR10 0 to 23 00h 1Eh BDT 0 0 BDT21 BDT20 BDT13 BDT12 BDT11 BDT10 1 to 31 00h 1Fh BMO 0 0 0 BMO20 BMO13 BMO12 BMO11 BMO10 1 to 12 00h FN6667 Rev 6.00 Page 14 of 34 January 9, 2015

ISL12020M TABLE 1. REGISTER MEMORY MAP (X INDICATES DEFAULT VARIES WITH EACH DEVICE. YELLOW SHADING INDICATES THOSE BITS SHOULD NOT BE CHANGED BY THE USER) (Continued) BIT REG ADDR. SECTION NAME 7 6 5 4 3 2 1 0 RANGE DEFAULT 20h DSTCR DstMoFd DSTE D D DstMoFd DstMoFd DstMoFd DstMoFd DstMoFd 1 to 12 00h 20 13 12 11 10 21h DstDwFd D DstDwFd DstWkFd DstWkFd DstWkFd DstDwFd DstDwFd DstDwFd 0 to 6 00h E 12 11 10 12 11 10 22h DstDtFd D D DstDtFd2 DstDtFd2 DstDtFd1 DstDtFd1 DstDtFd1 DstDtFd1 1 to 31 00h 1 0 3 2 1 0 23h DstHrFd D D DstHrFd2 DstHrFd2 DstHrFd1 DstHrFd1 DstHrFd1 DstHrFd1 0 to 23 00h 1 0 3 2 1 0 24h DstMoRv D D D XDstMoR DstMoRv DstMoR1 DstMoRv DstMoRv 01 to 12 00h v20 13 2v 11 10 25h DstDwRv D DstDwRv DstWkrv1 DstWkRv DstWkRv DstDwRv DstDwRv DstDwRv 0 to 6 00h E 2 11 10 12 11 10 26h DstDtRv D D DstDtRv2 DstDtRv2 DstDtRv1 DstDtRv1 DstDtRv1 DstDtRv1 01 to 31 00h 1 0 3 2 1 0 27h DstHrRv D D DstHrRv2 DstHrRv2 DstHrRv1 DstHrRv1 DstHrRv1 DstHrRv1 0 to 23 00h 1 0 3 2 1 0 28h TEMP TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 00 to FF 00h 29h TK0M 0 0 0 0 0 0 TK09 TK08 00 to 03 00h 2Ah NPPM NPPML NPPM7 NPPM6 NPPM5 NPPM4 NPPM3 NPPM2 NPPM1 NPPM0 00 to FF 00h 2Bh NPPMH 0 0 0 0 0 NPPM10 NPPM9 NPPM8 00 to 07 00h 2Ch XT0 XT0 D D D XT4 XT3 XT2 XT1 XT0 00 to FF XXh 2Dh ALPHAH ALPHAH D ALP_H6 ALP_H5 ALP_H4 ALP_H3 ALP_H2 ALP_H1 ALP_H0 00 to 7F XXh 2Eh GPM GPM1 GPM17 GPM16 GPM15 GPM14 GPM13 GPM12 GPM11 GPM10 00 to FF 00h 2Fh GPM2 GPM27 GPM26 GPM25 GPM24 GPM23 GPM22 GPM21 GPM20 00 to FF 00h Real Time Clock Registers LEAP YEARS Leap years add the day February 29 and are defined as those years Addresses [00h to 06h] that are divisible by 4. Years divisible by 100 are not leap years, unless they are also divisible by 400. This means that the year 2000 RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) is a leap year and the year 2100 is not. The ISL12020M does not These registers depict BCD representations of the time. As such, correct for the leap year in the year 2100. SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) Control and Status Registers can either be a 12-hour or 24-hour mode, DT (Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99 and DW (Day of the (CSR) Week) is 0 to 6. Addresses [07h to 0Fh] The DW register provides a Day of the Week status and uses three bits DW2 to DW0 to represent the seven days of the week. The The Control and Status Registers consist of the Status Register, counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… Interrupt and Alarm Register, Analog Trimming and Digital Theassignment of a numerical value to a specific day of the Trimming Registers. week is arbitrary and may be decided by the system software designer. The default value is defined as “0”. Status Register (SR) 24-HOUR TIME The Status Register is located in the memory map at address 07h. This is a volatile register that provides either control or If the MIL bit of the HR register is “1”, the RTC uses a 24-hour status of RTC failure (RTCF), Battery Level Monitor (LBAT85, format. If the MIL bit is “0”, the RTC uses a 12-hour format and LBAT75), alarm trigger, Daylight Saving Time, crystal oscillator HR21 bit functions as an AM/PM indicator with a “1” enable and temperature conversion in progress bit. representing PM. The clock defaults to 12-hour format time with HR21 = “0”. FN6667 Rev 6.00 Page 15 of 34 January 9, 2015

ISL12020M TABLE 2. STATUS REGISTER (SR) clear when the VBAT is above the pre-selected trip level at the next detection cycle either by manual or automatic trigger. ADDR 7 6 5 4 3 2 1 0 In Battery Mode (VBAT), this bit indicates the device has entered 07h BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register BUSY BIT (BUSY) reaches x9h or x0h minutes. Busy Bit indicates temperature sensing is in progress. In this mode, Alpha, Beta and ITRO registers are disabled and cannot be Example - When the LBAT85 is Set To “1” In Battery Mode: accessed. The minute the register changes to 19h when the device is in battery mode, the LBAT85 is set to “1” the next time the device OSCILLATOR FAIL BIT (OSCF) switches back to Normal Mode. Oscillator Fail Bit indicates that the oscillator has failed. The Example - When the LBAT85 Remains at “0” In Battery oscillator frequency is either zero or very far from the desired Mode: 32.768kHz due to failure, PC board contamination or mechanical issues. If the device enters into battery mode after the minute register reaches 20h and switches back to Normal Mode before the DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ) minute register reaches 29h, then the LBAT85 bit will remain at DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the “0” the next time the device switches back to Normal Mode. daylight saving time forward adjustment has happened. If a DST LOW BATTERY INDICATOR 75% BIT (LBAT75) Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit will stay high when DSTFD event happens and will be reset to “0” In Normal Mode (VDD), this bit indicates when the battery level when the DST Reverse event happens. It is read-only and cannot has dropped below the preselected trip levels. The trip points are be written. Setting time during a DST forward period will not set selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the this bit to “1”. PWR_VBAT registers. The LBAT75 detection happens automatically once every minute when seconds register reaches The DSTE bit must be enabled when the RTC time is more than 59. The detection can also be manually triggered by setting the one hour before the DST Forward or DST Reverse event time TSE bit in BETA register to “1”. The LBAT75 bit is set when the setting, or the DST event correction will not happen. VBAT has dropped below the preselected trip level and will self DSTADJ is reset to “0” upon power-up. It will reset to “0” when the clear when the VBAT is above the preselected trip level at the next DSTE bit in Register 15h is set to “0” (DST disabled), but no time detection cycle either by manual or automatic trigger. adjustment will happen. In Battery Mode (VBAT), this bit indicates the device has entered ALARM BIT (ALM) into battery mode by polling once every 10 minutes. The LBAT85 detection happens automatically once when the minute register This bit announces if the alarm matches the real time clock. If reaches x9h or x0h minutes. there is a match, the respective bit is set to “1”. This bit can be manually reset to “0” by the user or automatically reset by Example - When the LBAT75 is Set to “1” in Battery Mode: enabling the auto-reset bit (see ARST bit). A write to this bit in the The minute register changes to 30h when the device is in battery SR can only set it to “0”, not “1”. An alarm bit that is set by an mode, the LBAT75 is set to “1” the next time the device switches alarm occurring during an SR read operation will remain set after back to Normal Mode. the read operation is complete. Example - When the LBAT75 Remains at “0” in Battery Mode: LOW V INDICATOR BIT (LVDD) DD If the device enters into battery mode after the minute register This bit indicates when VDD has dropped below the pre-selected reaches 49h and switches back to Normal Mode before minute trip level (Brownout Mode). The trip points for the brownout levels register reaches 50h, then the LBAT75 bit will remain at “0” the are selected by three bits: VDDTrip2, VDDTrip1 and VDDTrip0 in next time the device switches back to Normal Mode. PWR_VDD registers. The LVDD detection is only enabled in VDD mode and the detection happens in real time. The LVDD bit is set REAL TIME CLOCK FAIL BIT (RTCF) whenever the VDD has dropped below the preselected trip level This bit is set to a “1” after a total power failure. This is a read and self clears whenever the VDD is above the preselected trip only bit that is set by hardware (ISL12020M internally) when the level. device powers up after having lost all power (defined as VDD = 0V LOW BATTERY INDICATOR 85% BIT (LBAT85) and VBAT = 0V). The bit is set regardless of whether VDD or VBAT is applied first. The loss of only one of the supplies does not set In Normal Mode (VDD), this bit indicates when the battery level the RTCF bit to “1”. The first valid write to the RTC section after a has dropped below the preselected trip levels. The trip points are complete power failure resets the RTCF bit to “0” (writing one selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the byte is sufficient). PWR_VBAT registers. The LBAT85 detection happens automatically once every minute when seconds register reaches 59. The detection can also be manually triggered by setting the TSE bit in BETA register to “1”. The LBAT85 bit is set when the VBAT has dropped below the preselected trip level and will self FN6667 Rev 6.00 Page 16 of 34 January 9, 2015

ISL12020M Interrupt Control Register (INT) TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN TABLE 3. INTERRUPT CONTROL REGISTER (INT) FREQUENCY, FOUT UNITS FO3 FO2 FO1 FO0 ADDR 7 6 5 4 3 2 1 0 0 Hz 0 0 0 0 08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0 32768 Hz 0 0 0 1 AUTOMATIC RESET BIT (ARST) 4096 Hz 0 0 1 0 This bit enables/disables the automatic reset of the ALM, LVDD, 1024 Hz 0 0 1 1 LBAT85 and LBAT75 status bits only. When ARST bit is set to “1”, 64 Hz 0 1 0 0 these status bits are reset to “0” after a valid read of the respective status register (with a valid STOP condition). When the 32 Hz 0 1 0 1 ARST is cleared to “0”, the user must manually reset the ALM, 16 Hz 0 1 1 0 LVDD, LBAT85 and LBAT75 bits. 8 Hz 0 1 1 1 WRITE RTC ENABLE BIT (WRTC) 4 Hz 1 0 0 0 The WRTC bit enables or disables write capability into the RTC 2 Hz 1 0 0 1 Timing Registers. The factory default setting of this bit is “0”. Upon initialization or power-up, the WRTC must be set to “1” to 1 Hz 1 0 1 0 enable the RTC. Upon the completion of a valid write (STOP), the 1/2 Hz 1 0 1 1 RTC starts counting. The RTC internal 1Hz signal is synchronized to the STOP condition during a valid write cycle. 1/4 Hz 1 1 0 0 INTERRUPT/ALARM MODE BIT (IM) 1/8 Hz 1 1 0 1 This bit enables/disables the interrupt mode of the alarm 1/16 Hz 1 1 1 0 function. When the IM bit is set to “1”, the alarm will operate in 1/32 Hz 1 1 1 1 the interrupt mode, where an active low pulse width of 250ms will appear at the IRQ/FOUT pin when the RTC is triggered by the POWER SUPPLY CONTROL REGISTER (PWR_VDD) alarm, as defined by the alarm registers (0Ch to 11h). When the IM bit is cleared to “0”, the alarm will operate in standard mode, Clear Time Stamp Bit (CLRTS) where the IRQ/FOUT pin will be set low until the ALM status bit is TABLE 6. cleared to “0”. ADDR 7 6 5 4 3 2 1 0 TABLE 4. 09h CLRTS 0 0 0 0 VDDTrip2 VDDTrip1 VDDTrip0 IM BIT INTERRUPT/ALARM FREQUENCY 0 Single Time Event Set By Alarm This bit clears Time Stamp VDD to Battery (TSV2B) and Time 1 Repetitive/Recurring Time Event Set By Alarm Stamp Battery to VDD Registers (TSB2V). The default setting is 0 (CLRTS=0) and the Enabled setting is 1 (CLRTS= 1). FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB) VDD Brownout Trip Voltage BITS (VDDTrip<2:0>) This bit enables/disables the IRQ/FOUT pin during These bits set the trip level for the VDD alarm, indicating that VDD battery-backup mode (i.e. VBAT power source active). When the has dropped below a preset level. In this event, the LVDD bit in FOBATB is set to “1”, the IRQ/FOUT pin is disabled during the Status Register is set to “1”. See Table7. battery-backup mode. This means that both the frequency output and alarm output functions are disabled. When the FOBATB is TABLE 7. VDD TRIP LEVELS cleared to “0”, the IRQ/FOUT pin is enabled during battery- TRIP VOLTAGE backup mode. Note that the open-drain IRQ/FOUT pin will need a VDDTrip2 VDDTrip1 VDDTrip0 (V) pull-up to the battery voltage to operate in battery-backup mode. 0 0 0 2.295 FREQUENCY OUT CONTROL BITS (FO<3:0>) 0 0 1 2.550 These bits enable/disable the frequency output function and 0 1 0 2.805 select the output frequency at the IRQ/FOUT pin. See Table5 for frequency selection. Default for the ISL12020M is FO<3:0> = 1h, 0 1 1 3.060 or 32.768kHz output (FOUT is ON). When the frequency mode is 1 0 0 4.250 enabled, it will override the alarm mode at the IRQ/FOUT pin. 1 0 1 4.675 FN6667 Rev 6.00 Page 17 of 34 January 9, 2015

ISL12020M BATTERY VOLTAGE TRIP VOLTAGE REGISTER TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) (PWR_VBAT) BATTERY ALARM TRIP This register controls the trip points for the two VBAT alarms, with LEVEL levels set to approximately 85% and 75% of the nominal battery VB75Tp2 VB75Tp1 VB75Tp0 (V) level. 0 0 0 1.875 TABLE 8. 0 0 1 2.025 ADDR 7 6 5 4 3 2 1 0 0 1 0 2.250 0Ah D RESEALB VB85T VB85T VB85T VB75T VB75T VB75T 0 1 1 2.475 p2 p1 p0 p2 p1 p0 1 0 0 2.700 RESEAL BIT (RESEALB) 1 0 1 3.750 This is the Reseal bit for actively disconnecting VBAT pin from the 1 1 0 4.125 internal circuitry. Setting this bit allows the device to disconnect the battery and eliminate standby current drain while the device is Initial AT and DT setting Register (ITRO) unused. Once VDD is powered up, this bit is reset and the VBAT pin is These bits are used to trim the initial error (at room temperature) then connected to the internal circuitry. of the crystal. Both Digital Trimming (DT) and Analog Trimming The application for this bit involves placing the chip on a board (AT) methods are available. The digital trimming uses clock pulse with a battery and testing the board. Once the board is tested skipping and insertion for frequency adjustment. Analog and ready to ship, it is desirable to disconnect the battery to keep trimming uses load capacitance adjustment to pull the oscillator it fresh until the board or unit is placed into final use. Setting frequency. A range of +62.5ppm to -61.5ppm is possible with RESEALB = “1” initiates the battery disconnect and after VDD combined digital and analog trimming. power is cycled down and up again, the RESEAL bit is cleared to Initial values for the ITR0 register are preset internally and “0”. recalled to RAM registers on power-up. These values can be BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>) overwritten by the user although this is not suggested as the resulting temperature compensation performance will be Three bits select the first alarm (85% of Nominal VBAT) level for the compromised. Aging adjustment is normally a few ppm and can battery voltage monitor. There are total of 7levels that could be be handled by writing to the IATR section. selected for the first alarm. Any of the of levels could be selected as the first alarm with no reference as to nominal battery voltage level. AGING AND INITIAL TRIM DIGITAL TRIMMING BITS See Table9. (IDTR0<1:0>) TABLE 9. VB85T ALARM LEVEL These bits allow ±30.5ppm initial trimming range for the crystal frequency. This is meant to be a coarse adjustment if the range BATTERY ALARM TRIP needed is outside that of the IATR control. See Table11. The LEVEL IDTR0 register should only be changed while the TSE (Temp VB85Tp2 VB85Tp1 VB85Tp0 (V) Sense Enable) bit is “0”. 0 0 0 2.125 The ISL12020M has a preset Initial Digital Trimming value 0 0 1 2.295 corresponding to the crystal in the module. This value is recalled 0 1 0 2.550 on initial power-up and should never be changed for best temperature compensation performance, although the user may 0 1 1 2.805 change this preset value to adjust for aging or board mounting 1 0 0 3.060 changes if so desired. 1 0 1 4.250 TABLE 11. IDTR0 TRIMMING RANGE 1 1 0 4.675 IDTR01 IDTR00 TRIMMING RANGE 0 0 Default/Disabled BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>) 0 1 +30.5ppm Three bits select the second alarm (75% of Nominal VBAT) level for the battery voltage monitor. There are total of 7 levels that could be 1 0 0ppm selected for the second alarm. Any of the of levels could be selected 1 1 -30.5ppm as the second alarm with no reference as to nominal Battery voltage level. See Table10. FN6667 Rev 6.00 Page 18 of 34 January 9, 2015

ISL12020M AGING AND INITIAL ANALOG TRIMMING BITS The IATR0 register should only be changed while the TSE (Temp (IATR0<5:0>) Sense Enable) bit is “0”. The Initial Analog Trimming Register allows +32ppm to -31ppm TABLE 12. INITIAL AT AND DT SETTING REGISTER adjustment in 1ppm/bit increments. This enables fine frequency ADDR 7 6 5 4 3 2 1 0 adjustment for trimming initial crystal accuracy error or to correct for aging drift. 0Bh IDTR0 IDTR0 IATR0 IATR0 IATR0 IATR0 IATR0 IATR0 1 0 5 4 3 2 1 0 The ISL12020M has a preset Initial Analog Trimming value corresponding to the crystal in the module. This value is recalled on initial power-up and should never be changed for best Note that setting the IATR to the lowest settings (-31ppm) with the temperature compensation performance, although the user may default 32kHz output can cause the oscillator frequency to change this preset value to adjust for aging or board mounting become unstable on power-up. The lowest settings for IATR should changes if so desired. be avoided to insure oscillator frequency integrity. TABLE 13. IATRO TRIMMING RANGE IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 TRIMMING RANGE 0 0 0 0 0 0 +32 0 0 0 0 0 1 +31 0 0 0 0 1 0 +30 0 0 0 0 1 1 +29 0 0 0 1 0 0 +28 0 0 0 1 0 1 +27 0 0 0 1 1 0 +26 0 0 0 1 1 1 +25 0 0 1 0 0 0 +24 0 0 1 0 0 1 +23 0 0 1 0 1 0 +22 0 0 1 0 1 1 +21 0 0 1 1 0 0 +20 0 0 1 1 0 1 +19 0 0 1 1 1 0 +18 0 0 1 1 1 1 +17 0 1 0 0 0 0 +16 0 1 0 0 0 1 +15 0 1 0 0 1 0 +14 0 1 0 0 1 1 +13 0 1 0 1 0 0 +12 0 1 0 1 0 1 +11 0 1 0 1 1 0 +10 0 1 0 1 1 1 +9 0 1 1 0 0 0 +8 0 1 1 0 0 1 +7 0 1 1 0 1 0 +6 0 1 1 0 1 1 +5 0 1 1 1 0 0 +4 0 1 1 1 0 1 +3 0 1 1 1 1 0 +2 0 1 1 1 1 1 +1 1 0 0 0 0 0 0 1 0 0 0 0 1 -1 1 0 0 0 1 0 -2 1 0 0 0 1 1 -3 1 0 0 1 0 0 -4 1 0 0 1 0 1 -5 1 0 0 1 1 0 -6 1 0 0 1 1 1 -7 FN6667 Rev 6.00 Page 19 of 34 January 9, 2015

ISL12020M TABLE 13. IATRO TRIMMING RANGE (Continued) IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 TRIMMING RANGE 1 0 1 0 0 0 -8 1 0 1 0 0 1 -9 1 0 1 0 1 0 -10 1 0 1 0 1 1 -11 1 0 1 1 0 0 -12 1 0 1 1 0 1 -13 1 0 1 1 1 0 -14 1 0 1 1 1 1 -15 1 1 0 0 0 0 -16 1 1 0 0 0 1 -17 1 1 0 0 1 0 -18 1 1 0 0 1 1 -19 1 1 0 1 0 0 -20 1 1 0 1 0 1 -21 1 1 0 1 1 0 -22 1 1 0 1 1 1 -23 1 1 1 0 0 0 -24 1 1 1 0 0 1 -25 1 1 1 0 1 0 -26 1 1 1 0 1 1 -27 1 1 1 1 0 0 -28 1 1 1 1 0 1 -29 1 1 1 1 1 0 -30 1 1 1 1 1 1 -31 ALPHA Register (ALPHA) BETA Register (BETA) TABLE 14. ALPHA REGISTER TABLE 15. ADDR 7 6 5 4 3 2 1 0 ADDR 7 6 5 4 3 2 1 0 0Ch D ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA ALPHA 0Dh TSE BTSE BTSR BETA4 BETA3 BETA2 BETA1 BETA0 6 5 4 3 2 1 0 TEMPERATURE SENSOR ENABLED BIT (TSE) The ALPHA variable is 8 bits and is defined as the temperature This bit enables the Temperature Sensing operation, including the coefficient of crystal from -40°C to T0, or the ALPHA Cold (there temperature sensor, A/D converter and FATR/FDTR register is an Alpha Hot register that must be programmed as well). It is adjustment. The default mode after power-up is disabled (TSE = 0). normally given in units of ppm/°C2, with a typical value of To enable the operation, TSE should be set to 1 (TSE = 1). When -0.034. The ISL12020M device uses a scaled version of the temp sense is disabled, the initial values for IATR and IDTR registers absolute value of this coefficient in order to get an integer value. are used for frequency control. Therefore, ALPHA<7:0> is defined as the (|Actual ALPHA Value| x 2048) and converted to binary. For example, a crystal with Alpha All changes to the IDTR, IATR, ALPHA and BETA registers must be of -0.034ppm/°C2 is first scaled (|2048*(-0.034)|=70d) and made with TSE = 0. After loading the new values, TSE can be then converted to a binary number of 01000110b. enabled and the new values are used. When TSE is set to 1, the temperature conversion cycle begins and will end when two The practical range of Actual ALPHA values is from -0.020 to temperature conversions are completed. The average of the two -0.060. conversions is in the TEMP registers. The ISL12020M has a preset ALPHA value corresponding to the crystal in the module. This value is recalled on initial power-up TEMP SENSOR CONVERSION IN BATTERY MODE BIT and should remain unchanged for best compensation (BTSE) performance, although the user can override this preset value if This bit enables the Temperature Sensing and Correction in battery so desired. mode. BTSE = 0 (default) no conversion, Temp Sensing or The ALPHA register should only be changed while the TSE (Temp Compensation in battery mode. BTSE = 1 indicates Temp Sensing Sense Enable) bit is “0”. Note that both the ALPHA and the and Compensation enabled in battery mode. The BTSE is disabled ALPHA Hot registers need to be programmed with values for full when the battery voltage is lower than 2.7V. No temperature range temperature compensation. compensation will take place with VBAT<2.7V. FN6667 Rev 6.00 Page 20 of 34 January 9, 2015

ISL12020M FREQUENCY OF TEMPERATURE SENSING AND The BETA VALUES result is indexed in the right hand column and CORRECTION BIT (BTSR) the resulting Beta factor (for the register) is in the same row in the left column. This bit controls the frequency of Temp Sensing and Correction. BTSR = 0 default mode is every 10 minutes, BTSR = 1 is every The ISL12020M has a preset BETA value corresponding to the 1.0 minute. Note that BTSE has to be enabled in both cases. See crystal in the module. This value is recalled on initial power-up Table16. and should never be changed for best temperature compensation performance, although the user may override this The temperature measurement conversion time is the same for preset value if so desired. battery mode as for VDD mode, approximately 22ms. The battery mode current will increase during this conversion time to The value for BETA should only be changed while the TSE (Temp typically 68µA. The average increase in battery current is much Sense Enable) bit is “0”. The procedure for writing the BETA lower than this due to the small duty cycle of the ON-time versus register involves two steps. First, write the new value of BETA with OFF-time for the conversion. TSE = 0. Then write the same value of BETA with TSE = 1. This will insure the next temp sense cycle will use the new BETA value. To figure the average increase in battery current, we take the change in current times the duty cycle. For the 1minute TABLE 17. BETA VALUES temperature period the average current is as shown in BETA<4:0> AT STEP ADJUSTMENT Equation1: 01000 0.5000 0.022s I =------------------68A= 250nA (EQ. 1) BAT 60s 00111 0.5625 00110 0.6250 For the 10 minute temperature period the average current is as shown in Equation2: 00101 0.6875 I =0----.-0----2---2----s--68A= 25nA (EQ. 2) 00100 0.7500 BAT 600s 00011 0.8125 If the application has a stable temperature environment that 00010 0.8750 doesn’t change quickly, the 10 minute option will work well and the backup battery lifetime impact is minimized. If quick 00001 0.9375 temperature variations are expected (multiple cycles of more 00000 1.0000 than 10° within an hour), then the 1 minute option should be 10000 1.0625 considered and the slightly higher battery current figured into overall battery life. 10001 1.1250 TABLE 16. FREQUENCY OF TEMPERATURE SENSING AND 10010 1.1875 CORRECTION BIT 10011 1.2500 TC PERIOD IN 10100 1.3125 BTSE BTSR BATTERY MODE 0 0 OFF 10101 1.3750 0 1 OFF 10110 1.4375 1 0 10 Minutes 10111 1.5000 1 1 1 Minute 11000 1.5625 11001 1.6250 GAIN FACTOR OF AT BIT (BETA<4:0>) Beta is specified to take care of the Cm variations of the crystal. 11010 1.6875 Most crystals specify Cm around 2.2fF. For example, if Cm > 2.2fF, 11011 1.7500 the actual AT steps may reduce from 1ppm/step to approximately 11100 1.8125 0.80ppm/step. Beta is then used to adjust for this variation and restore the step size to 1ppm/step. 11101 1.8750 BETA values are limited in the range from 01000 to 11111 as 11110 1.9375 shown in Table17. To use Table17, the device is tested at two AT 11111 2.0000 settings in Equation3: BETA VALUES = ATmax–ATmin/63 (EQ. 3) Where: AT(max) = FOUT in ppm (at AT = 00H) and AT(min) = FOUT in ppm (at AT = 3FH). FN6667 Rev 6.00 Page 21 of 34 January 9, 2015

ISL12020M Final Analog Trimming Register (FATR) ALARM Registers (10h to 15h) This register shows the final setting of AT after temperature The alarm register bytes are set up identical to the RTC register correction. It is read-only; the user cannot overwrite a value to this bytes, except that the MSB of each byte functions as an enable register. This value is accessible as a means of monitoring the bit (enable = “1”). These enable bits specify which alarm temperature compensation function. See Tables18 and 19 (for registers (seconds, minutes, etc.) are used to make the values). comparison. Note that there is no alarm byte for year. TABLE 18. FINAL ANALOG TRIMMING REGISTER The alarm function works as a comparison between the alarm registers and the RTC registers. As the RTC advances, the alarm ADDR 7 6 5 4 3 2 1 0 will be triggered once a match occurs between the alarm 0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0 registers and the RTC registers. Any one alarm register, multiple registers, or all registers can be enabled for a match. Final Digital Trimming Register (FDTR) There are two alarm operation modes: Single Event and periodic This register shows the final setting of DT after temperature Interrupt Mode: correction. It is read-only; the user cannot overwrite a value to •Single Event Mode is enabled by setting the bit 7 on any of the this register. The value is accessible as a means of monitoring Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “0” and the temperature compensation function. The corresponding disabling the frequency output. This mode permits a one-time clock adjustment values are shown in Table20. The FDTR setting match between the Alarm registers and the RTC registers. has both positive and negative settings to adjust for any offset in Once this match occurs, the ALM bit is set to “1” and the the crystal.. IRQ/FOUT output will be pulled low and will remain low until the ALM bit is reset. This can be done manually or by using the TABLE 19. FINAL DIGITAL TRIMMING REGISTER auto-reset feature. ADDR 7 6 5 4 3 2 1 0 •Interrupt Mode is enabled by setting the bit 7 on any of the 0Fh 0 0 0 FDTR4 FDTR3 FDTR2 FDTR1 FDTR0 Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to “1” and disabling the frequency output. The IRQ/FOUT output will now TABLE 20. CLOCK ADJUSTMENT VALUES FOR FINAL DIGITAL be pulsed each time an alarm occurs. This means that once TRIMMING REGISTER the interrupt mode alarm is set, it will continue to alarm for FDTR<4:0> DECIMAL ppm ADJUSTMENT each occurring match of the alarm and present time. This mode is convenient for hourly or daily hardware interrupts in 00000 0 0 microcontroller applications such as security cameras or utility 00001 1 30.5 meter reading. 00010 2 61 To clear a single event alarm, the ALM bit in the status register 00011 3 91.5 must be set to “0” with a write. Note that if the ARST bit is set to 00100 4 122 1 (address 08h, bit 7), the ALM bit will automatically be cleared when the status register is read. 00101 5 152.5 00110 6 183 Following are examples of both Single Event and periodic Interrupt Mode alarms. 00111 7 213.5 01000 8 244 Example 1 01001 9 274.5 • Alarm set with single interrupt (IM = “0”) 01010 10 305 • A single alarm will occur on January 1 at 11:30 a.m. 10000 0 0 • Set Alarm registers as follows: 10001 -1 -30.5 10010 -2 -61 10011 -3 -91.5 10100 -4 -122 10101 -5 -152.5 10110 -6 -183 10111 -7 -213.5 11000 -8 -244 11001 -9 -274.5 11010 -10 -305 FN6667 Rev 6.00 Page 22 of 34 January 9, 2015

ISL12020M TABLE 21. captures the FIRST VDD to Battery Voltage transition time and will not update upon subsequent events, until cleared (only the first BIT ALARM event is captured before clearing). Set CLRTS = 1 to clear this REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION register (Add 09h, PWR_VDD register). SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled Note that the time stamp registers are cleared to all “0”, MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30, including the month and day, which is different from the RTC and enabled alarm registers (those registers default to 01h). This is the HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11, indicator that no time stamping has occurred since the last clear enabled or initial power-up. Once a time stamp occurs, there will be a DTA0 1 0 0 0 0 0 0 1 81h Date set to 1, non-zero time stamp. enabled Time Stamp Battery to V Registers (TSB2V) DD MOA0 1 0 0 0 0 0 0 1 81h Month set to 1, enabled The Time Stamp Battery to VDD Register bytes are identical to the RTC register bytes, except they do not extend beyond Month. DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled The Time Stamp captures the LAST transition of VBAT to VDD (only the last event of a series of power-up/down events is After these registers are set, an alarm will be generated when the retained). Set CLRTS= 1 to clear this register (Add 09h, RTC advances to exactly 11:30 a.m. on January 1 (after seconds PWR_VDD register). changes from 59 to 00) by setting the ALM bit in the status register DST Control Registers (DSTCR) to “1” and also bringing the IRQ/FOUT output low. Example 2 8 bytes of control registers have been assigned for the Daylight Savings Time (DST) functions. DST beginning (set Forward) time • Pulsed interrupt once per minute (IM = “1”) is controlled by the registers DstMoFd, DstDwFd, DstDtFd and • Interrupts at one minute intervals when the seconds register is DstHrFd. DST ending time (set Backward or Reverse) is controlled at 30s. by DstMoRv, DstDwRv, DstDtRv and DstHrRv. • Set Alarm registers as follows: Tables23 and 24 describe the structure and functions of the DSTCR. TABLE 22. DST FORWARD REGISTERS (20H TO 23H) BIT DST forward is controlled by the following DST Registers: ALARM REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION DST Enable SCA0 1 0 1 1 0 0 0 0 B0h Seconds set to 30, DSTE is the DST Enabling Bit located in Bit 7 of register 20h enabled (DstMoFdxx). Set DSTE = 1 will enable the DSTE function. Upon powering up for the first time (including battery), the DSTE bit MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled defaults to “0”. When DSTE is set to “1” the RTC time must be at HRA0 0 0 0 0 0 0 0 0 00h Hours disabled least one hour before the scheduled DST time change for the correction to take place. When DSTE is set to “0”, the DSTADJ bit DTA0 0 0 0 0 0 0 0 0 00h Date disabled in the Status Register automatically resets to “0”. MOA0 0 0 0 0 0 0 0 0 00h Month disabled DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled DST Month Forward DstMoFd sets the Month that DST starts. The format is the same Once the registers are set, the following waveform will be seen at as for the RTC register month, from 1 to 12. The default value for IRQ/FOUT: the DST begin month is 00h. RTC AND ALARM REGISTERS ARE BOTH “30s” DST Day/Week Forward DstDwFd contains both the Day of the Week and the Week of the Month data for DST Forward control. DST can be controlled either by actual date or by setting both the Week of the month and the Day of the Week. DstDwFdE sets the priority of the Day/Week over the Date. For DstDwFdE = 1, Day/Week is the priority. You 60s must have the correct Day of Week entered in the RTC registers FIGURE 15. IRQ/FOUT WAVEFORM for the Day/Week correction to work properly. Note that the status register ALM bit will be set each time the alarm is triggered, but does not need to be read or cleared. Time Stamp V to Battery Registers (TSV2B) DD The TSV2B Register bytes are identical to the RTC register bytes, except they do not extend beyond the Month. The Time Stamp FN6667 Rev 6.00 Page 23 of 34 January 9, 2015

ISL12020M TABLE 23. DST FORWARD REGISTERS ADDRESS FUNCTION 7 6 5 4 3 2 1 0 20h Month Forward DSTE 0 0 MoFd20 MoFd13 MoFd12 MoFd11 MoFd10 21h Day Forward 0 DwFdE WkFd12 WkFd11 WkFd10 DwFd12 DwFd11 DwFd10 22h Date Forward 0 0 DtFd21 DtFd20 DtFd13 DtFd12 DtFd11 DtFd10 23h Hour Forward 0 HrFd21 HrFd20 HrFd13 HrFd12 HrFd11 HrFd10 TABLE 24. DST REVERSE REGISTERS ADDRESS NAME 7 6 5 4 3 2 1 0 24h Month Reverse 0 0 0 MoRv20 MoRv13 MoRv12 MoRv11 MoRv10 25h Day Reverse 0 DwRvE WkRv12 WkRv11 WkRv10 DwRv12 DwRv11 DwRv10 26h Date Reverse 0 0 DtRv21 DtRv20 DtRv13 DtRv12 DtRv11 DtRv10 27h Hour Reverse 0 HrRv21 HrRv20 HrRv13 HrRv12 HrRv11 HrRv10 • Bits 0, 1, 2 contain the Day of the week information, which must have the correct Day of Week entered in the RTC registers sets the Day of the Week that DST starts. Note that Day of the for the Day/Week correction to work properly. week counts from 0 to 6, like the RTC registers. The default for • Bits 0, 1, 2 contain the Day of the week information, which the DST Forward Day of the Week is 00h (normally Sunday). sets the Day of the Week that DST ends. Note that Day of the • Bits 3, 4, 5 contain the Week of the Month information that week counts from 0 to 6, like the RTC registers. The default for sets the week that DST starts. The range is from 1 to 5 and the DST Reverse Day of the Week is 00h (normally Sunday). Week 7 is used to indicate the last week of the month. The • Bits 3, 4, 5 contain the Week of the Month information that sets default for the DST Forward Week of the Month is 00h. the week that DST ends. The range is from 1 to 5 and Week 7 is DST Date Forward used to indicate the last week of the month. The default for the DST Reverse Week of the Month is 00h. DstDtfd controls which Date DST begins. The format for the Date is the same as for the RTC register, from 1 to 31. The default DST Date Reverse value for DST forward date is 00h. DstDtFd is only effective if DstDtRv controls which Date DST ends. The format for the Date is DstDwFdE = 0. the same as for the RTC register, from 1 to 31. The default value DST Hour Forward for DST Date Reverse is 00h. The DstDtRv is only effective if the DwRvE = 0. DstHrFd controls the hour that DST begins. The RTC hour and DstHrFd registers have the same formats except there is no DST Hour Reverse Military bit for DST hour. The user sets the DST hour with the DstHrRv controls the hour that DST ends. The RTC hour and same format as used for the RTC hour (AM/PM or MIL) but DstHrFd registers have the same formats except there is no without the MIL bit and the DST will still advance as if the MIL bit Military bit for DST hour. The user sets the DST hour with the were there. The default value for DST hour Forward is 00h. same format as used for the RTC hour (AM/PM or MIL) but DST REVERSE REGISTERS (24H TO 27H) without the MIL bit and the DST will still advance as if the MIL bit were there. The default value for DST hour Reverse is 00h. DST end (reverse) is controlled by the following DST Registers: TEMP Registers (TEMP) DST Month Reverse DstMoRv sets the Month that DST ends. The format is the same The temperature sensor produces an analog voltage output, as for the RTC register month, from 1 to 12. The default value for which is input to an A/D converter and produces a 10-bit the DST end month is October (10h). temperature value in degrees Kelvin. TK07:00 are the LSBs of the code and TK09:08 are the MSBs of the code. The temperature DST Day/Week Reverse result is actually the average of two successive temperature DstDwRv contains both the Day of the Week and the Week of the measurements to produce greater resolution for the temperature Month data for DST Reverse control. DST can be controlled either control. The output code can be converted to degrees Centigrade by actual date or by setting both the Week of the month and the by first converting from binary to decimal, dividing by 2 and then Day of the Week. DstDwRvE sets the priority of the Day/Week subtracting 273d. over the Date. For DstDwRvE = 1, Day/Week is the priority. You Temperature in °C = [(TK <9:0>)/2] - 273 (EQ. 4) FN6667 Rev 6.00 Page 24 of 34 January 9, 2015

ISL12020M The practical range for the temp sensor register output is from 446d TABLE 26. TURNOVER TEMPERATURE to 726d, or -50°C to +90°C. The temperature compensation ADDR 7 6 5 4 3 2 1 0 function is only guaranteed over -40°C to +85°C. The TSE bit must be set to “1” to enable temperature sensing. 2Ch 0 0 0 XT4 XT3 XT2 XT1 XT0 TABLE 25. The ISL12020M has a preset turnover temperature TEMP 7 6 5 4 3 2 1 0 corresponding to the crystal in the module. This value is recalled on initial power-up and should never be changed for best TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00 temperature compensation performance, although the user may TK0M 0 0 0 0 0 0 TK09 TK08 override this preset value if so desired. Table27 shows the values available, with a range from +17.5°C NPPM Registers (NPPM) to +32.5°C in +0.5°C increments. The default value is 00000b The NPPM value is exactly 2x the net correction required to bring or +25°C. the oscillator to 0ppm error. The value is the combination of TABLE 27. XT0 VALUES oscillator Initial Correction (IPPM) and crystal temperature dependent correction (CPPM). XT<4:0> TURNOVER TEMPERATURE IPPM is used to compensate the oscillator offset at room 01111 32.5 temperature and is controlled by the ITR0 and BETA registers, 01110 32.0 which are fixed during factor test. 01101 31.5 The CPPM compensates the oscillator frequency fluctuation over 01100 31 temperature. It is determined by the temperature (T), crystal curvature parameter (ALPHA) and crystal turn-over temperature 01011 30.5 (XT0). T is the result of the temp sensor/ADC conversion, whose 01010 30 decimal result is 2x the actual temperature in Kelvin. ALPHA is from either the ALPHA (cold) or ALPHAH (hot) register depending 01001 29.5 on T and XT0 is from the XT0 register. 01000 29.0 NPPM is governed by Equation5: 00111 28.5 NPPM = IPPM(ITR0,BETA) + ALPHA x (T-T0)2 00110 28.0 NPPM = IPPM+CPPM 00101 27.5 00100 27.0 2 NPPM = IPPM+A-----L----P----H-----A--4---0----9---6T-----–-----T----0-------- (EQ. 5) 00011 26.5 Where 00010 26.0 ALPHA = 2048 00001 25.5 T is the reading of the ADC, result is 2 x temperature in degrees 00000 25.0 Kelvin. 10000 25.0 T = 2298+XT0 (EQ. 6) 10001 24.5 or 10010 24.0 T = 596+XT0 10011 23.5 Note that NPPM can also be predicted from the FATR and FDTR 10100 23.0 register by the relationship (all values in decimal): 10101 22.5 NPPM = 2*(BETA*FATR - (FDTR-16)) 10110 22.0 XT0 Registers (XT0) 10111 21.5 TURNOVER TEMPERATURE (XT<3:0>) 11000 21.0 The apex of the Alpha curve occurs at a point called the turnover 11001 20.5 temperature, or XT0. Crystals normally have a turnover 11010 20.0 temperature between +20°C and +30°C, with most occurring near +25°C. 11011 19.5 11100 19.0 11101 18.5 FN6667 Rev 6.00 Page 25 of 34 January 9, 2015

ISL12020M TABLE 27. XT0 VALUES (Continued) The ALPHAH register should only be changed while the TSE (Temp Sense Enable) bit is “0”. XT<4:0> TURNOVER TEMPERATURE 11110 18.0 User Registers (Accessed by 11111 17.5 Using Slave Address 1010111x) ALPHA Hot Register (ALPHAH) Addresses [00h to 7Fh] These registers are 128 bytes of battery-backed user SRAM. The TABLE 28. ALPHA HOT REGISTER separate I2C slave address must be used to read and write to ADDR 7 6 5 4 3 2 1 0 these registers. 2Dh D ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H ALP_H 2 I C Serial Interface 6 5 4 3 2 1 0 The ISL12020M supports a bidirectional bus oriented protocol. The ALPHA Hot variable is 7 bits and is defined as the temperature The protocol defines any device that sends data onto the bus as a coefficient of Crystal from the XT0 value to +85°C (both Alpha Hot transmitter and the receiving device as the receiver. The device and Alpha Cold must be programmed to provide full temperature controlling the transfer is the master and the device being compensation). It is normally given in units of ppm/°C2, with a controlled is the slave. The master always initiates data transfers typical value of -0.034. Like the ALPHA cold version, a scaled and provides the clock for both transmit and receive operations. version of the absolute value of this coefficient is used in order to Therefore, the ISL12020M operates as a slave device in all get an integer value. Therefore, ALP_H<7:0> is defined as the applications. (|Actual Alpha Hot Value| x 2048) and converted to binary. For example, a crystal with Alpha Hot of -0.034ppm/°C2 is first scaled All communication over the I2C interface is conducted by sending (|2048*(-0.034)| = 70d) and then converted to a binary number the MSB of each byte of data first. of 01000110b. Protocol Conventions The practical range of Actual ALPHAH values is from -0.020to Data states on the SDA line can change only during SCL LOW -0.060. periods. SDA state changes during SCL HIGH are reserved for The ISL12020M has a preset ALPHAH value corresponding to the indicating START and STOP conditions (see Figure16). On crystal in the module. This value is recalled on initial power-up power-up of the ISL12020M, the SDA pin is in the input mode. and should never be changed for best temperature . compensation performance, although the user may override this preset value if so desired. SCL SDA DATA DATA DATA START STOP STABLE CHANGE STABLE FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM HIGH IMPEDANCE TRANSMITTER SDA OUTPUT FROM HIGH IMPEDANCE RECEIVER START ACK FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER FN6667 Rev 6.00 Page 26 of 34 January 9, 2015

ISL12020M WRITE SIGNALS FROM S THE MASTER T S A IDENTIFICATION ADDRESS DATA T R BYTE BYTE BYTE O T P SIGNAL AT SDA 1 1 0 1 1 1 1 0 0 0 0 0 SIGNALS FROM A A A THE ISL12020M C C C K K K FIGURE 18. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN) All I2C interface operations must begin with a START condition, In a random read operation, the slave byte in the “dummy write” which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The portion must match the slave byte in the “read” section. For a ISL12020M continuously monitors the SDA and SCL lines for the random read of the Control/Status Registers, the slave byte must be START condition and does not respond to any command until this “1101111x” in both places. condition is met (see Figure16). A START condition is ignored during the power-up sequence. 1 1 0 1 1 1 1 R/ SLAVE ADDRESS BYTE All I2C interface operations must be terminated by a STOP condition, which is a LOW-to-HIGH transition of SDA while SCL is A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS HIGH (see Figure16). A STOP condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE An acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master FIGURE 19. SLAVE ADDRESS, WORD ADDRESS AND DATA BYTES or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW Write Operation to acknowledge the reception of the eight bits of data (see Figure17). A Write operation requires a START condition, followed by a valid The ISL12020M responds with an ACK after recognition of a Identification Byte, a valid Address Byte, a Data Byte and a STOP START condition followed by a valid Identification Byte and once condition. After each of the three bytes, the ISL12020M again, after successful receipt of an Address Byte. The responds with an ACK. At this time, the I2C interface enters a ISL12020M also responds with an ACK after receiving a Data standby state. Byte of a write operation. The master must respond with an ACK Read Operation after receiving a Data Byte of a read operation. Device Addressing A Read operation consists of a three byte instruction, followed by one or more Data Bytes (see Figure20). The master initiates the Following a start condition, the master must output a Slave Address operation issuing the following sequence: a START, the Byte. The 7 MSBs are the device identifiers. These bits are Identification byte with the R/W bit set to “0”, an Address Byte, a “1101111” for the RTC registers and “1010111” for the User SRAM. second START and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the ISL12020M responds The last bit of the Slave Address Byte defines a read or write with an ACK. Then the ISL12020M transmits Data Bytes as long as operation to be performed. When this R/W bit is a “1”, a read the master responds with an ACK during the SCL cycle following operation is selected. A “0” selects a write operation (refer to the eighth bit of each byte. The master terminates the read Figure19). operation (issuing a STOP condition) following the last bit of the After loading the entire Slave Address Byte from the SDA bus, the last Data Byte (see Figure20). ISL12020M compares the device identifier and device select bits The Data Bytes are from the memory location indicated by an with “1101111” or “1010111”. Upon a correct compare, the device internal pointer. This pointer’s initial value is determined by the outputs an acknowledge on the SDA line. Address Byte in the Read operation instruction and increments Following the Slave Byte is a one byte word address. The word by one during transmission of each Data Byte. After reaching the address is either supplied by the master device or obtained from an memory location 2Fh, the pointer “rolls over” to 00h and the internal counter. On power-up, the internal address counter is set to device continues to output data for each ACK received. address 00h, so a current address read starts at address 00h. When required, as part of a random read, the master must supply the 1 Word Address Bytes, as shown in Figure20. FN6667 Rev 6.00 Page 27 of 34 January 9, 2015

ISL12020M SIGNALS S S FROM THE T IDENTIFICATION T IDENTIFICATION S MASTER A BYTE WITH ADDRESS A BYTE WITH A A T R R/W = 0 BYTE R R/W = 1 C C O T T K K P SIGNAL AT 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 SDA A A A SIGNALS FROM C C C FIRST READ LAST READ THE SLAVE K K K DATA BYTE DATA BYTE FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN) Application Section . VDD = 2.7V ISL12020M JBAT DBAT TO 5.5V BAT43W Power Supply Considerations VDD VBAT +VBAT = 1.8V The ISL12022M contains programmed EEPROM registers which 0.1CµINF C0.B1AµTF TO 3.2V are recalled to volatile RAM registers during initial power-up. These registers contain DC voltage, frequency and temperature GND calibration settings. Initial power-up can be either application of VBAT or VDD power, whichever is first. It is important that the FIGURE 21. SUGGESTED BATTERY-BACKUP CIRCUIT initial power-up meet the power supply slew rate specification to avoid faulty EEPROM power-up recall. Also, any glitches or low The VDD negative slew rate should be limited to below the data voltage DC pauses should be avoided, as these may activate sheet spec (10V/ms) otherwise battery switchover can be recall at a low voltage and load erroneous data into the delayed, resulting in SRAM contents corruption and oscillator calibration registers. Note that a very slow VDD ramp rate operation interruption. (outside data sheet limits) will almost always trigger erroneous Some applications will require separate supplies for the RTC VDD recall and should be avoided entirely. and the I2C pullups. This is not advised, as it may compromise the operation of the I2C bus. For applications that do require Battery-Backup Details serial bus communication with the RTC VDD powered down, the The ISL12020M has automatic switchover to battery-backup SDA pin must be pulled low during the time the RTC VDD ramps when the VDD drops below the VBAT mode threshold. A wide down to 0V. Otherwise, the device may lose serial bus variety of backup sources can be used, including standard and communications once VDD is powered up and will return to rechargeable lithium, Super Capacitors, or regulated secondary normal operation ONLY once VDD and VBAT are both powered sources. The serial interface is disabled in battery-backup, while down together. the oscillator and RTC registers are operational. The SRAM register contents are powered to preserve their contents as well. Layout Considerations The input voltage range for VBAT is 1.8V to 5.5V, but keep in The ISL12020M contains a quarts crystal and requires special mind the temperature compensation only operates for handling during PC board assembly. Excessive shock and vibrations VBAT>2.7V. Note that the device is not guaranteed to operate should be avoided. Ultrasound cleaning is not advisable. See Note7 with a VBAT < 1.8V, so the battery should be changed before on page6 in the electrical specifications table pertaining to solder discharging to that level. It is strongly advised to monitor the low reflow effects on oscillator accuracy. battery indicators in the status registers and take action to The crystal pins X1 and X2 have a very high impedance and replace discharged batteries. oscillator circuits operating at low frequencies (such as If a Super Capacitor is used, it is possible that it may discharge to 32.768kHz) are known to pick up noise very easily if layout below 1.8V during prolonged power-down. Once powered up, the precautions are not followed. Most instances of erratic clocking device may lose serial bus communications until both VDD and or large accuracy errors can be traced to the susceptibility of the VBAT are powered down together. To avoid that situation, oscillator circuit to interference from adjacent high speed clock including situations where a battery may discharge deeply, the or data lines. Careful layout of the RTC circuit will avoid noise circuit in Figure21 can be used. pickup and insure accurate clocking. The diode, DBAT, will add a small drop to the battery voltage but will protect the circuit should battery voltage drop below 1.8V. The jumper is added as a safeguard should the battery ever need to be disconnect from the circuit. FN6667 Rev 6.00 Page 28 of 34 January 9, 2015

ISL12020M Figure22 shows a suggested layout for the ISL12020M device. parasitic elements in the scope probe. Use the FOUT output and a Three main precautions should be followed: frequency counter for the most accurate results. 1. Do not run the serial bus lines or any high speed logic lines in Temperature Compensation Operation the vicinity of the X1 and X2 pins. These logic level lines can The ISL12020M temperature compensation feature needs to be induce noise in the oscillator circuit, causing misclocking. enabled by the user. This must be done in a specific order as 2. Add a ground trace around the device with one end follows: terminated at the chip ground. This guard ring will provide termination for emitted noise in the vicinity of the RTC device. 1. Read register 0Dh, the BETA register. This register contains 3. Do not run a ground or power plane immediately under the the 5-bit BETA trimmed value, which is automatically loaded RTC. This will add capacitance to the X1/X2 pins and change on initial power-up. Mask off the 5LSB’s of the value just read. the trimmed frequency of the oscillator. Instead, try to leave a 2. Bit 7 of the BETA register is the master enable control for gap in any planes under the RTC device. temperature sense operation. Set this to “1” to allow continuous temperature frequency correction. Frequency . GROUND correction will then happen every 60s with VDD applied. RING 3. Bits 5 and 6 of the BETA register control temperature compensation in battery-backup mode (see Table16 on page21). Set the values for the operation desired. 4. Write back to register 0Dh making sure not to change the 5 LSB values and include the desired compensation control bits. FOUT Note that every time the BETA register is written with the TSE SCL bit= 1, a temperature compensation cycle is instigated and a new correction value will be loaded into the FATR/FDTR registers SDA (if the temperature changed since the last conversion). Also note that registers 0Bh and 0Ch, the ITR0 and ALPHA registers, should not be changed. If they must be written be sure FIGURE 22. SUGGESTED LAYOUT FOR ISL12020M to write the same values that are recalled from initial power-up. The ITR0 register may be written if the user wishes to recalibrate The best way to run clock lines around the RTC is to stay outside the oscillator frequency at room temperature for aging or board of the ground ring by at least a few millimeters. Also, use the mounting. The original recalled value can be rewritten if desired VBAT and VDD as guard ring lines as well, they can isolate clock after testing. lines from the X1 and X2 pins. In addition, if the IRQ/FOUT pin is used as a clock, it should be routed away from the RTC device as Daylight Savings Time (DST) Example well. DST involves setting the forward and back times and allowing the Measuring Oscillator Accuracy RTC device to automatically advance the time or set the time back. This can be done for current year and future years. Many The best way to analyze the ISL12020M frequency accuracy is to regions have DST rules that use standard months, weeks and set the IRQ/FOUT pin for a specific frequency and look at the time of the day, which permit a preprogrammed, permanent output of that pin on a high accuracy frequency counter (at least setting. 7 digits accuracy). Note that the IRQ/FOUT is an drain output and will require a pull-up resistor. An example setup for the ISL12020M is in Table29. Using the 1.0Hz output frequency is the most convenient as the TABLE 29. DST EXAMPLE ppm error is just as shown in Equation7: VARIABLE VALUE REGISTER VALUE ppm error = F –11e6 (EQ. 7) OUT Month Forward and DST April 15h 84h Enable Other frequencies may be used for measurement but the error calculation becomes more complex. Week and Day Forward 1st Week and 16h 48h and select Day/Week, not Sunday When the proper layout guidelines above are observed, the Date oscillator should start-up in most circuits in less than one second. Date Forward not used 17h 00h When testing RTC circuits, a common impulse is to apply a scope probe to the circuit at the X2 pin (oscillator output) and observe Hour Forward 2am 18h 02h the waveform. DO NOT DO THIS! Although in some cases you may Month Reverse October 19h 10h see a usable waveform, due to the parasitics (usually 10pF to ground) applied with the scope probe, there will be no useful Week and Day Reverse Last Week and 1Ah 78h information in that waveform other than the fact that the circuit and select Day/Week, not Sunday Date is oscillating. The X2 output is sensitive to capacitive impedance so the voltage levels and the frequency will be affected by the Date Reverse not used 1Bh 00h FN6667 Rev 6.00 Page 29 of 34 January 9, 2015

ISL12020M TABLE 29. DST EXAMPLE (Continued) VARIABLE VALUE REGISTER VALUE Hour Reverse 2am 1Ch 02h The Enable bit (DSTE) is in the Month forward register, so the BCD value for that register is altered with the additional bit. The Week and Day values along with Week/Day vs Date select bit is in the Week/Day register, so that value is also not straight BCD. Hour and Month are normal BCD, but the Hour doesn’t use the MIL bit since Military time PM values are already discretely different from AM/PM time PM values. The DST reverse setting utilizes the option to select the last week of the month for October, which could have 4 or 5 weeks but needs to have the time change on the last Sunday. Note that the DSTADJ bit in the status register monitors whether the DST forward adjustment has happened. When it is “1”, DST forward has taken place. When it is “0”, then either DST reverse has happened, or it has been reset either by initial power-up or if the DSTE bit has been set to “0”. FN6667 Rev 6.00 Page 30 of 34 January 9, 2015

ISL12020M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE January 9, 2015 FN6667.6 Updated datasheet applying Intersil’s new standards. On page1, added bullet (AN1389) to the Related Literature section. Updated the temperature range from “-40°C to +85°C” to “0°C to +85°C” on page1 in paragraph 1, on page5 in the Pin Descriptions table for X2 and X1 pins and on page11 in paragraph 1. On page7, updated FoutT by the following: added “0°C to +85°C” to the test conditions added “-30°C to +85C” and “-40°C to +85°C” rows Updated Products verbiage to About Intersil verbiage. October 28, 2011 FN6667.5 On page1, corrected Figure 1, Typical Application Circuit to show that pin 6/15 are not connected to ground. On page4, Ordering Information, added ISL12020MIRZ-EVALZ evaluation board. On page5, Pin Descriptions, added Ground pin row, separated VDD pin. Bolded No Connection for the Thermal Pad. On page6, Absolute Maximum Ratings, added shock, vibration. On page6, for IDD1 at 3V/5V limits, changed MAX from 7/6µA to 15/14µA. On page7, added VDDSR+ as typical, with Note 17. On page8, added Note 17 for VDDSR+ On page16, under Oscillator Fail Bit, changed text to: “Oscillator Fail Bit indicates that the oscillator has failed. The oscillator frequency is either zero or very far from the desired 32.768kHz due to failure, PC board contamination or mechanical issues.” On page16, under Daylight Savings Time Change Bit, removed “DSTADJ can be set to “1” for instances where the RTC device is initialized during the DST Forward period.” Added “It is read-only and cannot be written. Setting time during a DST forward period will not set this bit to “1”.” On page22, Table 19, changed FDTR column head from <2:0> to <4:0>. On page22, Tables 20 and 21, corrected addresses. On page28, added Power Supply Considerations section. April 23, 2010 Added “Latch-up (Tested per JESD-78B; Class 2, Level A) 100mA or 1.5 * VMAX Input” on page6 Added “Maximum Junction Temperature +85°C” on page6 Added “” on page1 Added “Thermal Pad” description to “Pin Descriptions” on page5. Added “Thermal Pad” label to “Pin Configuration” on page5. Added cross references to page numbers in “Revision History”. Updated Package Outline Drawing on page34 to most recent revision. Changes were as follows: Revised note 8 from: "Soldering required to PCB for X1 and X2 pads each on a separate floating metal (GRN)." to: "Soldering required to PCB for X1 and X2 pads to separate and non-connected metal pads." Changed Note 2 from: "These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric elements).." to: "These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melting temp solder and in piezoelectronic devices) and exemption 5 (lead in glass of electronic components).." FN6667 Rev 6.00 Page 31 of 34 January 9, 2015

ISL12020M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE February 11, 2010 FN6667.4 Updated Note 2 in Ordering Information table from “These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.” to “These Intersil plastic packaged products employ special material sets, molding compounds and 100% matte tin plate plus anneal (e3) termination finish. These products do contain Pb but they are RoHS compliant by exemption 7 (lead in high melt temp solder for internal connections) and exemption 5 (lead in piezoelectric elements). These Intersil RoHS compliant products are compatible with both SnPb and Pb-free soldering operations. These Intersil RoHS compliant products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.” Changed "Pb-Free" in page1 “Features” and page4 “Ordering Information” to "RoHS Compliant" October 22, 2009 Converted to New Intersil Template - Matched front page to match ISL12022M with the exception of pinout change from SOIC to DFN. Updated ordering information by numbering all notes, setting up links, added MSL (Moisture Sensitivity Level) note. Updated word "Pinout" to "Pin Configuration". Pin Descriptions updated by adding descriptive text taken from page 9. Deleted Text Pin Descriptions that were on page 9. Changed Thermal information from "Tja 85, Tjc 3" To "Tja 40, Tjc 3.5" to match ASYD in Intrepid. Pb-free reflow link now shown in blue. Updated Notes in Electrical Spec Tables to follow flow of numbers when referenced. Added "boldface limits..." text in Electrical Spec Conditions to indicate Min and Max over-temp. Bolded all over-temp Min and Max values. Added Revision History and Products information with links. Updated POD from Rev0 to Rev1 to match Intrepid. Added Table of Contents. July 24, 2009 FN6667.3 Page 1: in the Features section, corrected typo in the second bullet from: 20 Ld DFN Package (for SOIC package see ISL12020M) To:20 Ld DFN Package (for SOIC package see ISL12022M) No rev, no date change, no formal review necessary June 22, 2009 Changes in Word document attached in Intrepid. http://intranet.intrepid.intersil.com/Windchill/servlet/WindchillAuthGW/wt.content.ContentHttp/viewContent /12020M.doc?u8&HttpOperationItem=wt.content.ApplicationData%3A120896672&ContentHolder=ext.isil.p art.mcol.MCOL%3A120896665 January 15, 2009 FN6667.2 Added text and equations for Ibat for temp sense ON and for relative accuracy for 1m vs 10m interval Added text clarifying that no compensation at Vbat<2.7V Revised entire “DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)” on page16 Added Application Example for DST - “Daylight Savings Time (DST) Example” on page29 Added requirement for Vbat>1.8V in Vbat note. Added apps circuit to survive Vbat<1.8V Corrected all occurrences of Alpha tables Bolded and shaded the COMPENSATION registers in Table 1 to indicate they are not to be overwritten. Also bolded an advisory in the register sections. Fixed blank bits in register tables and in text. Register Table 1: Change default values for compensation to xx's, they are different with each device. Added Datasheet curves Added statement to Apps section on crystal handling (in “Layout Considerations” on page28.) Applied Intersil standards as follows: Updated lead finish note in “Ordering Information”, added Theta JC note for thermal resistance, updated over-temp note in Electrical Specification tables, numbered equations that were not initially, updated POD to latest version, which includes following edits: Note 6 revised from “Soldering required to PCB for X1 and X2 pads each on a separate floating metal (GRN).”to “The X1 and X2 pads need to be soldered down to the PCB on separate and electrically isolated land pads.” Minor dimensions included based on customer input and laid out in new format. On page6: IDD1 - Changed Max from 6.5 to 7 for VDD = 5V and 5.5 to 6 for VDD = 3V. On page 3: Remove DeltaATLSB spec On page7: Hysteresis spec - Remove Min and set Typ to 0.05 x VDD on page8: tHD:DAT - Change Min from 0 to 20 On page14: For Table 1, yellow shaded and bolded XTO and ALPHAH registers On page21: Eq. 3 - Changed "BETAVALUES" to "BETA VALUES" On page29: Eq. 7 - Change "ppmerror" to "ppm error" On page26: Changed title for Table 28 from “ALPHA REGISTER” to "ALPHA HOT REGISTER" On Page 16: Under “Initial AT and DT setting Register (ITRO)” on page18, changed range value from 62.6ppm to 62.5ppm. FN6667 Rev 6.00 Page 32 of 34 January 9, 2015

ISL12020M Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE March 28, 2008 FN6667.1 Removed Min and Max limits for “Oscillator Initial Accuracy” on page6. Added Typ of ±2, Replaced Note 11 (Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.) with Note 9 (Limits should be considered typical and are not production tested). February 27, 2008 FN6667.0 Initial Release to web About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2008-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6667 Rev 6.00 Page 33 of 34 January 9, 2015

ISL12020M Package Outline Drawing L20.5.5x4.0 20 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 9/09 0.10 10X 0.50 2.10 0.66 5.5 A 0.300 0.30 R0.0750 B 11 20 10 X 0.50 R0.0750 2X1.30 0 4. 2.20 PIN #1 INDEX AREA 6 0.10 2X 10 1 PIN 1 18X 0.50 0.20 10X 0.25 INDEX AREA TOP VIEW 2.25 4 0.10M CAB10 x 0.25 0.35 2.45 (4.95) (2X 0.20) BOTTOM VIEW (4.50 ) 10X 0.50 10X 0.50 10X 0.45 10 X 0.25 10X 0.70 SEE DETAIL "X" 0.10C BPOAUCNKDAAGREY (2.20) (3.0)(4.40) 1.30 SEATING PLANEC 0.08C 2X 1.50 SIDE VIEW 0.68 0.16 0.30 (0.10) 10X 0.25 2.10 2X 2.45 5 (4.85) C 0.2 REF (4.95) 0-0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 Angular ±2° 4. Dimension applies to the metallized terminal and is measured between 0.015mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 7. No other electrical connection allowed under backside of X1 or X2 areas. 8. Soldering required to PCB for X1 and X2 pads to separate and non-connected metal pads. FN6667 Rev 6.00 Page 34 of 34 January 9, 2015