IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2015 FEATURES DESCRIPTION • High-speed access time: 35, 45, 55 ns The ISSI IS62WV25616DALL and IS62/65WV25616DBLL are high-speed, low power, 4M bit SRAMs organized as • CMOS low power operation 256K words by 16 bits. It is fabricated using ISSI's high- 30 mW (typical) operating performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields 6 µW (typical) CMOS standby high-performance and low power consumption devices. • TTL compatible interface levels When CS1 is HIGH (deselected) or when CS2 is LOW • Single power supply (deselcted) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode 1.65V--2.2V Vdd (IS62WV25616DALL) at which the power dissipation can be reduced down with 2.3V--3.6V Vdd (IS62/65WV25616DBLL) CMOS input levels. • Fully static operation: no clock or refresh Easy memory expansion is provided by using Chip Enable required and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte • Three state outputs allows Upper Byte (UB) and Lower Byte (LB) access. • Data control for upper and lower bytes The IS62WV25616DALL and IS62/65WV25616DBLL are • Industrial and Automotive temperature support packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm). • Lead-free available • 2 CS option available FUNCTIONAL BLOCK DIAGRAM 256K x 16 A0-A17 DECODER MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O DATA COLUMN I/O I/O8-I/O15 CIRCUIT Upper Byte CS2 CS1 OE CONTROL CIRCUIT WE UB LB Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL PIN CONFIGURATIONS 44-Pin mini TSOP (Type II) 48- ball mini BGA (6mm x 8mm) (Package Code T) (Package Code B) A4 1 44 A5 1 2 3 4 5 6 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE A0 5 40 UB CS1 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 A LB OE A0 A1 A2 NC I/O2 9 36 I/O13 I/O3 10 35 I/O12 B I/O8 UB A3 A4 CSI I/O0 VDD 11 34 GND GND 12 33 VDD C I/O9 I/O10 A5 A6 I/O1 I/O2 I/O4 13 32 I/O11 D GND I/O11 A17 A7 I/O3 VDD I/O5 14 31 I/O10 I/O6 15 30 I/O9 E VDD I/O12 NC A16 I/O4 GND I/O7 16 29 I/O8 WE 17 28 NC F I/O14 I/O13 A14 A15 I/O5 I/O6 A16 18 27 A8 A15 19 26 A9 G I/O15 NC A12 A13 WE I/O7 A14 20 25 A10 A13 21 24 A11 H NC A8 A9 A10 A11 NC A12 22 23 A17 48-Pin mini BGA (6mm x 8mm)* 2 CS Option (Package Code B2) 1 2 3 4 5 6 PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs A LB OE A0 A1 A2 CS2 CS1, CS2 Chip Enable Input B I/O8 UB A3 A4 CS1 I/O0 OE Output Enable Input C I/O9 I/O10 A5 A6 I/O1 I/O2 WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) D GND I/O11 A17 A7 I/O3 VDD UB Upper-byte Control (I/O8-I/O15) E VDD I/O12 NC A16 I/O4 GND NC No Connection F I/O14 I/O13 A14 A15 I/O5 I/O6 Vdd Power G I/O15 NC A12 A13 WE I/O7 GND Ground H NC A8 A9 A10 A11 NC *Available upon request 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL TRUTH TABLE I/O PIN Mode WE CS1 CS2 OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X X High-Z High-Z isb1, isb2 X X L X X X High-Z High-Z isb1, isb2 X X X X H H High-Z High-Z isb1, isb2 Output Disabled H L H H L X High-Z High-Z iCC H L H H X L High-Z High-Z iCC Read H L H L L H dOut High-Z iCC H L H L H L High-Z dOut H L H L L L dOut dOut Write L L H X L H din High-Z iCC L L H X H L High-Z din L L H X L L din din ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND –0.5 to Vdd + 0.5 V Vdd Vdd Relates to GND –0.3 to 4.0 V tstg Storage Temperature –65 to +150 °C Pt Power Dissipation 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit Cin Input Capacitance Vin = 0V 6 pF C Input/Output Capacitance VOut = 0V 8 pF i/O Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC TEST CONDITIONS Parameter Unit Unit Unit (2.3V-3.6V) (3.3V + 5%) (1.65V-2.2V) Input Pulse Level 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V 0.4V to Vdd - 0.3V Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns Input and Output Timing VDD /2 VDD + 0.05 0.9V and Reference Level (VRef) 2 Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 R1 ( Ω ) 1005 1213 13500 R2 ( Ω ) 820 1378 10800 Vtm (V) 3.0V 3.3V 1.8V AC TEST LOADS R1 R1 VTM VTM OUTPUT OUTPUT R2 R2 5 pF 30 pF Including Including jig and jig and scope scope Figure 1. Figure 2. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage Vdd = Min., iOH = –1 mA 2.4 — V VOL Output LOW Voltage Vdd = Min., iOL = 2.1 mA — 0.4 V ViH Input HIGH Voltage 2 Vdd + 0.3 V ViL Input LOW Voltage(1) –0.3 0.8 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.3V-3.6V Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage Vdd = Min., iOH = –1.0 mA 1.8 — V VOL Output LOW Voltage Vdd = Min., iOL = 2.1 mA — 0.4 V ViH Input HIGH Voltage 2.0 Vdd + 0.3 V ViL Input LOW Voltage(1) –0.3 0.8 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage iOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage iOL = 0.1 mA 1.65-2.2V — 0.2 V ViH Input HIGH Voltage 1.65-2.2V 1.4 Vdd + 0.2 V ViL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V iLi Input Leakage GND ≤ Vin ≤ Vdd –1 1 µA iLO Output Leakage GND ≤ VOut ≤ Vdd, Outputs Disabled –1 1 µA Note: 1. ViL (min.) = –0.3V DC; ViL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. ViH (max.) = Vdd + 0.3V dC; ViH (max.) = Vdd + 2.0V aC (pulse width < 10 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL OPERATING RANGE (VDD) Range Ambient Temperature VDD Speed Commercial 0°C to +70°C 1.65V-2.2V 45ns Industrial –40°C to +85°C 1.65V-2.2V 55ns Automotive –40°C to +125°C 1.65V-2.2V 55ns OPERATING RANGE (VDD) Range Ambient Temperature VDD (45 nS) VDD (35 nS) Commercial 0°C to +70°C 2.3V-3.6V 3.3V+5% Industrial –40°C to +85°C 2.3V-3.6V 3.3V+5% Automotive (A1) –40°C to +85°C 2.3V-3.6V 3.3V+5% OPERATING RANGE (VDD) Range Ambient Temperature VDD (45 nS) Automotive (A3) –40°C to +125°C 2.3V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -35 -45 -55 Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit iCC Vdd Dynamic Operating Vdd = Max., Com. — 20 — 15 — 15 mA Supply Current iOut = 0 mA, f = fmaX Ind./Auto A1 — 25 — 18 — 15 CE = ViL Auto. A3 — 30 — 25 — 25 Vin ≥ Vdd – 0.3V, or typ.(2) 10 Vin ≤ 0.4V iCC1 Operating Vdd = Max., Com. — 3 — 3 — 3 mA Supply Current iOut = 0 mA, f = 0 Ind./Auto A1 — 3 — 3 — 3 CE = ViL Auto. A3 — 3 — 3 — 3 Vin ≥ Vdd – 0.3V, or Vin ≤ 0.4V isb2 CMOS Standby Vdd = Max., Com. — 5 — 5 — 5 µA Current (CMOS Inputs) CS1 ≥ Vdd – 0.2V, Ind./Auto A1 — 10 — 10 — 10 CS2 ≤ 0.2V, Auto. A3 — 30 — 30 — 30 Vin ≥ Vdd – 0.2V, or typ.(2) 2 Vin ≤ 0.2V, f = 0 OR ULB Control Vdd = Max., CS1 = ViL, Cs2=ViH Vin ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Note: 1. At f = fmaX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 35 ns 45 ns 55 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit trC Read Cycle Time 35 — 45 — 55 — ns taa Address Access Time — 35 — 45 — 55 ns tOHa Output Hold Time 10 — 10 — 10 — ns taCs1/taCs2 CS1/CS2 Access Time — 35 — 45 — 55 ns tdOe OE Access Time — 10 — 20 — 25 ns tHzOe(2) OE to High-Z Output 0 10 0 15 0 20 ns tLzOe(2) OE to Low-Z Output 3 — 5 — 5 — ns tHzCs1/tHzCs2(2) CS1/CS2 to High-Z Output 0 10 0 15 0 20 ns tLzCs1/tLzCs2(2) CS1/CS2 to Low-Z Output 5 — 5 — 10 — ns tba LB, UB Access Time — 35 — 45 — 55 ns tHzb LB, UB to High-Z Output 0 15 0 15 0 20 ns tLzb LB, UB to Low-Z Output 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = ViL, CS2 = WE = ViH, UB or LB = ViL) tRC ADDRESS tAA tOHA tOHA DOUT PREVIOUS DATA VALID DATA VALID AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE tHZOE CS1 tLZOE tACE1/tACE2 CS2 tLZCE1/ tLZCE2 tHZCS1/ tHZCS2 LB, UB tBA tHZB tLZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = ViL. Cs2=WE=ViH. 3. Address is valid prior to or coincident with CS1 LOW transition. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 35 ns 45 ns 55 ns Symbol Parameter Min. Max. Min. Max. Min. Max. Unit twC Write Cycle Time 35 — 45 — 55 — ns tsCs1/tsCs2 CS1/CS2 to Write End 25 — 35 — 45 — ns taw Address Setup Time to Write End 25 — 35 — 45 — ns tHa Address Hold from Write End 0 — 0 — 0 — ns tsa Address Setup Time 0 — 0 — 0 — ns tPwb LB, UB Valid to End of Write 25 — 35 — 45 — ns tPwe WE Pulse Width 25 — 35 — 40 — ns tsd Data Setup to Write End 20 — 20 — 25 — ns tHd Data Hold from Write End 0 — 0 — 0 — ns tHzwe(3) WE LOW to High-Z Output — 10 — 20 — 20 ns tLzwe(3) WE HIGH to Low-Z Output 3 — 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to Vdd-0.2V/Vdd-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE WE LB, UB tSA tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC WAVEFORMS WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tSCS1 tHA CS1 tSCS2 CS2 tAW tPWE WE LB, UB tSA tHZWE tLZWE DOUT DATA UNDEFINED HIGH-Z tSD tHD DIN DATA-IN VALID 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL AC WAVEFORMS WRITE CYCLE NO. 4 (UB/LB Controlled) t t WC WC ADDRESS ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t t HA HA t WE SA t t PBW PBW UB, LB WORD 1 WORD 2 t t HZWE LZWE HIGH-Z DOUT DATA UNDEFINED t t HD HD t t SD SD DIN DVAATLAIDIN DVAATLAIDIN UB_CSWR4.eps Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 1.2 3.6 V idr Data Retention Current Vdd = 1.2V, CS1 ≥ Vdd – 0.2V Com. — 3 µA Ind. — 7 Auto. — 20 typ.(1) 1 tsdr Data Retention Setup Time See Data Retention Waveform 0 — ns trdr Recovery Time See Data Retention Waveform trC — ns Note: 1. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CS1 Controlled) tSDR Data Retention Mode tRDR VDD VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode V DD CE2 tSDR tRDR VDR CS2 ≤ 0.2V 0.4V GND 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL ORDERING INFORMATION IS62WV25616DALL (1.65V-2.2V) Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 70 IS62WV25616DALL-55TL TSOP, Lead-free Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 55 IS62WV25616DALL-55TI TSOP IS62WV25616DALL-55TLI TSOP, Lead-free 55 IS62WV25616DALL-55BI mini BGA (6mmx8mm) IS62WV25616DALL-55BLI mini BGA (6mmx8mm), Lead-free IS62WV25616DBLL (2.3V - 3.6V) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IS62WV25616DBLL-45TI TSOP IS62WV25616DBLL-45TLI TSOP, Lead-free 45 IS62WV25616DBLL-45BI mini BGA (6mmx8mm) IS62WV25616DBLL-45BLI mini BGA (6mmx8mm), Lead-free 55 IS62WV25616DBLL-55TLI TSOP, Lead-free IS65WV25616DBLL (2.3V - 3.6V) Automotive (A1) Range: –40°C to +85°C Speed (ns) Order Part No. Package 45 IS65WV25616DBLL-45CTLA1 TSOP, Lead-free, Copper Leadframe Automotive (A3) Range: –40°C to +125°C Speed (ns) Order Part No. Package 55 IS65WV25616DBLL-55CTLA3 TSOP, Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL 8 0 0 2 / 4 0 / 6 N. 0 O SI U R N. NT SIO ON/I RU SI T U O R R T P O OLD R PR M A E MB CLUD E DA ne Θ N : MM NOT IN NCLUD Outli SIO DO OT I e N 1 N g ME D E ES ka DI N O c NG D A b D Pa LI N N L O O TE : ONTRO MENSI MENSI O C DI DI N 1. 2. 3. Θ 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. D1 3/10/2015

IS62WV25616DALL/DBLL, IS65WV25616DBLL 8 0 0 7 2 0 2/ .2 1 M- / O 8 MM 0 N :C OE D I SE NJ E: Mt n DIe m Gu Nc o I Ld L e O : c E TRen ne OT ONefer utli CR O N 1. 2. e g a k c a P Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. D1 3/10/2015