IS62C1024AL IS65C1024AL 128K x 8 LOW POWER CMOS DECEMBER 2017 STATIC RAM FEATURES DESCRIPTION • High-speed access time: 35, 45 ns The ISSI IS62C1024AL/IS65C1024AL is a low power, 131,072-word by 8-bit CMOS static RAM. It is fabricated • Low active power: 100 mW (typical) using high-performance CMOS technology. This highly • Low standby power: 20 µW (typical) CMOS reliable process coupled with innovative circuit design standby techniques, yields higher performance and low power • Output Enable (OE) and two Chip Enable consumption devices. (CE1 and CE2) inputs for ease in applications When CE1 is HIGH or CE2 is LOW (deselected), the device • Fully static operation: no clock or refresh assumes a standby mode at which the power dissipation required can be reduced by using CMOS input levels. • TTL compatible inputs and outputs Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable • Single 5V (±10%) power supply (WE) controls both writing and reading of the memory. • Commercial, Industrial, and Automotive tem- perature ranges available • Standard Pin Configuration: — 32-pin SOP/ 32-pin TSOP (Type 1) • Lead free available FUNCTIONAL BLOCK DIAGRAM 128K x 8 A0-A16 DECODER MEMORY ARRAY VDD GND I/O I/O0-I/O7 DATA COLUMN I/O CIRCUIT CE1 CE2 CONTROL OE CIRCUIT WE Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL PIN CONFIGURATION PIN CONFIGURATION 32-Pin SOP 32-Pin TSOP (Type 1) NC 1 32 VDD A11 1 32 OE A16 2 31 A15 A9 2 31 A10 A14 3 30 CE2 A8 3 30 CE1 A12 4 29 WE A13 4 29 I/O7 A7 5 28 A13 WE 5 28 I/O6 A6 6 27 A8 CE2 6 27 I/O5 A5 7 26 A9 A15 7 26 I/O4 A4 8 25 A11 VDD 8 25 I/O3 A3 9 24 OE NC 9 24 GND A2 10 23 A10 A16 10 23 I/O2 A1 11 22 CE1 A14 11 22 I/O1 A0 12 21 I/O7 A12 12 21 I/O0 I/O0 13 20 I/O6 A7 13 20 A0 I/O1 14 19 I/O5 A6 14 19 A1 I/O2 15 18 I/O4 A5 15 18 A2 GND 16 17 I/O3 A4 16 17 A3 PIN DESCRIPTIONS A0-A16 Address Inputs CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input OPERATING RANGE (IS62C1024AL) OE Output Enable Input WE Write Enable Input Range Ambient Temperature Vdd Commercial 0°C to +70°C 5V ± 10% I/O0-I/O7 Input/Output Industrial -40°C to +85°C 5V ± 10% VDD Power GND Ground OPERATING RANGE (IS65C1024AL) Range Ambient Temperature Vdd Automotive -40°C to +125°C 5V ± 10% TRUTH TABLE Mode WE CE1 CE2 OE I/O Operation Vdd Current Not Selected X H X X High-Z Isb1, Isb2 (Power-down) X X L X High-Z Isb1, Isb2 Output Disabled H L H H High-Z Icc Read H L H L Dout Icc Write L L H X DIn Icc 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND –0.5 to +7.0 V tstg Storage Temperature –65 to +125 °C Pt Power Dissipation 1.0 W Iout DC Output Current (LOW) 20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit cIn Input Capacitance VIn = 0V 6 pF cout Output Capacitance Vout = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°c, f = 1 MHz, VDD = 5.0V. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Options Min. Max. Unit Voh Output HIGH Voltage VDD = Min., Ioh = –1.0 mA 2.4 — V Vol Output LOW Voltage VDD = Min., Iol = 2.1 mA — 0.4 V VIh Input HIGH Voltage 2.2 VDD + 0.5 V VIl Input LOW Voltage(1) -0.5 0.8 V IlI Input Leakage GND ≤ VIn ≤ VDD Com. -1 1 µA Ind. -2 2 Auto. -5 5 Ilo Output Leakage GND ≤ Vout ≤ VDD Com. -1 1 µA CE1 = VIh, or Ind. -2 2 CE2 = VIl, or OE = VIh or Auto. -5 5 WE = VIl Note: 1. VIl (min.) = -0.3V DC; VIl (min.) = -2.0V AC (pulse width -2.0 ns). Not 100% tested. VIh (max.) = VDD + 0.3V DC; VIh (max.) = VDD + 2.0V AC (pulse width -2.0 ns). Not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL IS62C1024AL/IS65C1024AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -35 ns -45 ns Symbol Parameter Test Conditions Min. Max. Min. Max. Unit Icc Average operating CE1 = VIl, ce2 = VIh Com. — 25 mA Current VIn = VIh or VIl, Ind. — 30 I I/o= 0 mA, f=0 Auto. — 35 Icc1 VDD Dynamic Operating VDD = Max., CE1 = VIl Com. — 30 mA Supply Current Iout = 0 mA, f = fmax Ind. — 35 VIn = VIh or VIl Auto. — 40 CE2 = VIh typ.(2) — 20 Isb1 TTL Standby Current VDD = Max., Com. — 1 mA (TTL Inputs) VIn = VIh or VIl, CE1 ≥ VIh, Ind. — 1.5 or CE2 ≤ VIl, f = 0 Auto. — 2 Isb2 CMOS Standby VDD = Max., Com. — 5 µA Current (CMOS Inputs) CE1 ≥ VDD – 0.2V, or Ind. — 10 ce2 ≤ 0.2V, VIn ≥ VDD – 0.2V, Auto. — 45 or VIn ≤ Vss + 0.2V, f = 0 typ.(2) — 4 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical Values are measured at VDD = 5V, Ta = 25oC and not 100% tested. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -35 ns -45 ns Symbol Parameter Min. Max. Min. Max. Unit trc Read Cycle Time 35 — 45 — ns taa Address Access Time — 35 — 45 ns toha Output Hold Time 3 — 3 — ns tace1 CE1 Access Time — 35 — 45 ns tace2 CE2 Access Time — 35 — 45 ns tDoe OE Access Time — 10 — 20 ns tlzoe(2) OE to Low-Z Output 3 — 5 — ns thzoe(2) OE to High-Z Output 0 10 0 15 ns tlzce1(2) CE1 to Low-Z Output 3 — 5 — ns tlzce2(2) CE2 to Low-Z Output 3 — 5 — ns thzce(2) CE1 or CE2 to High-Z Output 0 10 0 15 ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL AC TEST CONDITIONS Parameter Unit Input Pulse Level 0.6V to 2.4V Input Rise and Fall Times 5 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1a and 1b AC TEST LOADS 1838 Ω 1838 Ω 5V 5V OUTPUT OUTPUT 100 pF 993 Ω 5 pF 993 Ω Including Including jig and jig and scope scope Figure 1a. Figure 1b. AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tHZOE CE1 tLZOE tACE1/tACE2 CE2 tLZCE1/ tLZCE2 tHZCE DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIl, CE2 = VIh. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power) -35 ns -45 ns Symbol Parameter Min. Max. Min. Max. Unit twc Write Cycle Time 35 — 45 — ns tsce1 CE1 to Write End 25 — 35 — ns tsce2 CE2 to Write End 25 — 35 — ns taw Address Setup Time to Write End 25 — 35 — ns tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tPwe(4) WE Pulse Width 25 — 35 — ns tsD Data Setup to Write End 20 — 25 — ns thD Data Hold from Write End 0 — 0 — ns thzwe(2) WE LOW to High-Z Output — 10 — 15 ns tlzwe(2) WE HIGH to Low-Z Output 3 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) WE tSA tHZWE tLZWE HIGH-Z DOUT DATA UNDEFINED tSD tHD DIN DATA-IN VALID WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2) tWC ADDRESS tSA tSCE1 tHA CE1 tSCE2 CE2 tAW tPWE(4) WE tHZWE tLZWE DOUT DATA UNDEFINED HIGH-Z tSD tHD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIh. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit VDr VDD for Data Retention See Data Retention Waveform 2.0 5.5 V IDr Data Retention Current VDD = 2.0V, CE1 ≥ VDD – 0.2V Com. — — 5 µA or CE2 ≤ 0.2V Ind. — — 10 VIn ≥ VDD – 0.2V, or VIn ≤ Vss + 0.2V Auto. — — 45 tsDr Data Retention Setup Time See Data Retention Waveform 0 — ns trDr Recovery Time See Data Retention Waveform trc — ns Note: 1. Typical Values are measured at VDD = 5V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE1 Controlled) tSDR Data Retention Mode tRDR VDD 4.5V 2.2V VDR CE1 ≥ VDD - 0.2V CE1 GND DATA RETENTION WAVEFORM (CE2 Controlled) Data Retention Mode VDD 4.5V CE2 tSDR tRDR 2.2V VDR CE2 ≤ 0.2V 0.4V GND 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 35 IS62C1024AL-35QLI Plastic SOP, Lead-free 35 IS62C1024AL-35TLI TSOP, Type 1, Lead-free ORDERING INFORMATION: IS65C1024AL Automotive Range: -40°C to +125°C Speed (ns) Order Part No. Package 45 IS65C1024AL-45QLA3 Plastic SOP, Lead-free 45 IS65C1024AL-45TLA3 TSOP, Type 1, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. H1 12/01/2017

IS62C1024AL IS65C1024AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. H1 12/01/2017

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: I SSI: IS62C1024AL-35QLI IS62C1024AL-35QLI-TR IS62C1024AL-35TLI IS62C1024AL-35TLI-TR IS65C1024AL-45TLA3 IS65C1024AL-45TLA3-TR