ISSI ® IS61LV5128AL 512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES DESCRIPTION • High-speed access times: The ISSI IS61LV5128AL is a very high-speed, low power, 10, 12 ns 524,288-word by 8-bit CMOS static RAM. The (cid:127) High-performance, low-power CMOS process IS61LV5128AL is fabricated using ISSI's high-perform- ance CMOS technology. This highly reliable process (cid:127) Multiple center power and ground pins for coupled with innovative circuit design techniques, yields greater noise immunity higher performance and low power consumption devices. (cid:127) Easy memory expansion with CE and OE When CE is HIGH (deselected), the device assumes a options standby mode at which the power dissipation can be (cid:127) CE power-down reduced down to 250 µW (typical) with CMOS input levels. (cid:127) Fully static operation: no clock or refresh The IS61LV5128AL operates from a single 3.3V power required supply and all inputs are TTL-compatible. (cid:127) TTL compatible inputs and outputs The IS61LV5128AL is available in 36-pin 400-mil SOJ, 36- (cid:127) Single 3.3V power supply pin mini BGA, and 44-pin TSOP (Type II) packages. (cid:127) Packages available: – 36-pin 400-mil SOJ – 36-pin miniBGA – 44-pin TSOP (Type II) (cid:127) Lead-free available FUNCTIONAL BLOCK DIAGRAM 512K X 8 A0-A18 DECODER MEMORY ARRAY VDD GND I/O I/O0-I/O7 DATA COLUMN I/O CIRCUIT CE CONTROL OE CIRCUIT WE Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. C 04/15/05

ISSI ® IS61LV5128AL PIN CONFIGURATION 36 mini BGA 44-Pin TSOP (Type II) 1 2 3 4 5 6 NC 1 44 NC NC 2 43 NC A0 3 42 NC A1 4 41 A18 A2 5 40 A17 A3 6 39 A16 A A0 A1 NC A3 A6 A8 A4 7 38 A15 B I/O4 A2 WE A4 A7 I/O0 CE 8 37 OE I/O0 9 36 I/O7 C I/O5 NC A5 I/O1 I/O1 10 35 I/O6 D GND VDD VDD 11 34 GND GND 12 33 VDD E VDD GND I/O2 13 32 I/O5 F I/O6 A18 A17 I/O2 I/O3 14 31 I/O4 WE 15 30 A14 G I/O7 OE CE A16 A15 I/O3 A5 16 29 A13 H A9 A10 A11 A12 A13 A14 A6 17 28 A12 A7 18 27 A11 A8 19 26 A10 A9 20 25 NC NC 21 24 NC NC 22 23 NC 36-Pin SOJ PIN DESCRIPTIONS A0-A18 Address Inputs A0 1 36 NC CE Chip Enable Input A1 2 35 A18 OE Output Enable Input A2 3 34 A17 A3 4 33 A16 WE Write Enable Input A4 5 32 A15 I/O0-I/O7 Bidirectional Ports CE 6 31 OE I/O0 7 30 I/O7 VDD Power I/O1 8 29 I/O6 GND Ground VDD 9 28 GND NC No Connection GND 10 27 VDD I/O2 11 26 I/O5 I/O3 12 25 I/O4 WE 13 24 A14 A5 14 23 A13 TRUTH TABLE A6 15 22 A12 Mode WWWWWEEEEE CCCCCEEEEE OOOOOEEEEE I/O Operation VDD Current A7 16 21 A11 A8 17 20 A10 Not Selected X H X High-Z ISB1, ISB2 A9 18 19 NC (Power-down) Output Disabled H L H High-Z ICC Read H L L DOUT ICC Write L L X DIN ICC 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05

ISSI ® IS61LV5128AL ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit VTERM Terminal Voltage with Respect to GND –0.5 to VDD + 0.5 V TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma- nent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE VDD Range Ambient Temperature 10ns 12ns Commercial 0°C to +70°C 3.3V +10%, -5% 3.3V +10% Industrial -40°C to +85°C 3.3V +10%, -5% 3.3V +10% CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 0V 6 pF CI/O Input/Output Capacitance VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. C 04/15/05

ISSI ® IS61LV5128AL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD Com. –2 2 µA Ind. –5 5 ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled Com. –2 2 µA Ind. –5 5 Note: 1. VIL = –3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 -12 Symbol Parameter Test Conditions Min. Max. Min. Max. Unit ICC VDD Dynamic Operating VDD = Max., Com. — 90 — 85 mA Supply Current IOUT = 0 mA, f = fMAX Ind. — 95 — 90 ISB TTL Standby Current VDD = Max., Com. — 40 — 35 mA (TTL Inputs) VIN = VIH or VIL Ind. — 45 — 40 CE ≥ VIH, f = fMAX. ISB1 TTL Standby Current VDD = Max., Com. — 20 — 20 mA (TTL Inputs) VIN = VIH or VIL Ind. — 25 — 25 CE ≥ VIH, f = 0 ISB2 CMOS Standby VDD = Max., Com. — 15 — 15 mA Current (CMOS Inputs) CE ≥ VDD – 0.2V, Ind. — 20 — 20 VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05

ISSI ® IS61LV5128AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -10 -12 Symbol Parameter Min. Max. Min. Max. Unit tRC Read Cycle Time 10 — 12 — ns tAA Address Access Time — 10 — 12 ns tOHA Output Hold Time 2 — 2 — ns tACE CE Access Time — 10 — 12 ns tDOE OE Access Time — 4 — 5 ns tHZOE(2) OE to High-Z Output — 4 — 5 ns tLZOE(2) OE to Low-Z Output 0 — 0 — ns tHZCE(2 CE to High-Z Output 0 4 0 6 ns tLZCE(2) CE to Low-Z Output 3 — 3 — ns tPU Power Up Time 0 — 0 — ns tPD Power Down Time — 10 — 12 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1 and 2 AC TEST LOADS 319 Ω 319 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF 353 Ω 5 pF 353 Ω Including Including jig and jig and scope scope Figure 1 Figure 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. C 04/15/05

ISSI ® IS61LV5128AL AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS t AA t t OHA OHA DOUT PREVIOUS DATA VALID DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA t OHA OE t DOE t HZOE CE t LZOE t ACE t t LZCE HZCE DOUT HIGH-Z DATA VALID CE_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05

ISSI ® IS61LV5128AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -10 -12 Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 10 — 12 — ns tSCE CE to Write End 8 — 8 — ns tAW Address Setup Time 8 — 8 — ns to Write End tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1 WE Pulse Width 8 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 10 — 12 — ns tSD Data Setup to Write End 6 — 6 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 5 — 6 ns tLZWE(2) WE HIGH to Low-Z Output 2 — 2 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 WE t PWE2 t t HZWE LZWE HIGH-Z DOUT DATA UNDEFINED t t SD HD DIN DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. C 04/15/05

ISSI ® IS61LV5128AL WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t t SD HD DIN DATAIN VALID CE_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS t HA OE LOW CE LOW t AW t PWE2 WE t SA t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t t SD HD DIN DATAIN VALID CE_WR3.eps 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. C 04/15/05

ISSI ® IS61LV5128AL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. Package 10 IS61LV5128AL-10K 400-mil Plastic SOJ 10 IS61LV5128AL-10T TSOP (Type II) 12 IS61LV5128AL-12K 400-mil Plastic SOJ 12 IS61LV5128AL-12T TSOP (Type II) Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 10 IS61LV5128AL-10KI 400-mil Plastic SOJ 10 IS61LV5128AL-10KLI 400-mil Plastic SOJ, Lead-free 10 IS61LV5128AL-10TI TSOP (Type II) 10 IS61LV5128AL-10TLI TSOP (Type II), Lead-free 10 IS61LV5128AL-10BI mini BGA (8mmx10mm) 10 IS61LV5128AL-10BLI mini BGA (8mmx10mm), Lead-free 12 IS61LV5128AL-12TI TSOP (Type II) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. C 04/15/05

ISSI ® PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (36-pin) Top View Bottom View φ b (36x) 1 2 3 4 5 6 6 5 4 3 2 1 A A e B B C C D D D D1 E E F F G G H H e E E1 Notes: 1. Controlling dimensions are in millimeters. A2 A SEATING PLANE A1 mBGA - 6mm x 8mm mBGA - 8mm x 10mm MILLIMETERS INCHES MILLIMETER INCHES Sym. Min. Typ. Max. Min. Typ. Max. Sym. Min. Typ. Max. Min. Typ. Max. N0. N0. Leads 36 36 Leads 36 36 A — — 1.20 — — 0.047 A — — 1.20 — — 0.047 A1 0.24 — 0.30 0.009 — 0.012 A1 0.24 — 0.30 0.009 — 0.012 A2 0.60 — — 0.024 — — A2 0.60 — — 0.024 — — D 7.90 8.00 8.10 0.311 0.315 0.319 D 9.90 10.00 10.10 0.390 0.394 0.398 D1 5.25BSC 0.207BSC D1 5.25BSC .207BSC E 5.90 6.00 6.10 0.232 0.236 0.240 E 7.90 8.00 8.10 0.311 0.315 0.319 E1 3.75BSC 0.148BSC E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC e 0.75BSC 0.030BSC b 0.30 0.35 0.40 0.012 0.014 0.016 b 0.30 0.35 0.40 0.012 0.014 0.016 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 01/15/03

ISSI ® PACKAGING INFORMATION 400-mil Plastic SOJ Package Code: K Notes: N N/2+1 1. Controlling dimension: millimeters. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions E1 E and should be measured from the bottom of the package. 4. Reference document: JEDEC MS-027. 1 N/2 SEATING PLANE D A b C A2 e B A1 E2 Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) 28 32 36 A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03

ISSI ® PACKAGING INFORMATION Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max No. Leads (N) 40 42 44 A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 — A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 — B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130 E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 10/29/03

ISSI ® PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II) N N/2+1 Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not E1 E include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1 N/2 D SEATING PLANE A ZD . L α e b A1 C Plastic TSOP (T - Type II) Millimeters Inches Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Min Max Min Max Ref. Std. No. Leads (N) 32 44 50 A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018 C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830 E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471 e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024 ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF α 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5° Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. F 06/18/03

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: I SSI: IS61LV5128AL-10KLI-TR IS61LV5128AL-10TLI-TR IS61LV5128AL-10KLI IS61LV5128AL-10TLI