IRMCK171 High Performance Sensorless Motor Control IC Description IRMCK171 is a high performance One Time Programmable ROM based motion control IC designed and optimized for appliance control which contains two computation engines integrated into one monolithic chip. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCK171 comes in a 48 pin QFP package. Features Product Summary • MCETM (Flexible Motion Control Engine) - Maximum clock input (fcrystal) 60 Dedicated computation engine for high MHz efficiency sinusoidal sensorless motor control Maximum Internal clock (SYSCLK) 128MHz • Built-in hardware peripheral for single or two shunt current feedback reconstruction and Maximum 8051 clock (8051CLK) 32MHz analog circuits MCETM computation data range 16 bit • Supports induction machine and both interior signed and surface permanent magnet motor 8051/MCE Data RAM 2KB sensorless control • Loss minimization Space Vector PWM MCE Program RAM 12KB • Two-channel analog output (PWM) PWM carrier frequency 20 bits/ SYSCLK • Embedded 8-bit high speed microcontroller A/D input channels 7 (8051) for flexible I/O and man-machine control A/D converter resolution 12 bits • JTAG programming port for emulation/debugger A/D converter conversion speed 2 μsec • Serial communication interface (UART) Analog output (PWM) resolution 8 bits • I2C/SPI serial interface UART baud rate (typ) 57.6 Kbps • Internal 32Kbyte OTP ROM Number of digital I/O (max) 10 • 3.3V single supply Package (lead free) QFP48 Maximum 3.3V operating current 60mA Standard Pack Base Part Number Package Type Orderable Part Number Form Quantity Tray 2500 IRMCK171TY IRMCK171 QFP Tape and Reel 2000 IRMCK171TR 1 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 Table of Contents 1 Overview ............................................................................................................................... 5 2 Pinout .................................................................................................................................... 6 3 IRMCK171 Block Diagram and Main Functions .................................................................... 7 4 Application connection and Pin function ............................................................................... 9 4.1 8051 Peripheral Interface Group ................................................................................. 10 4.2 Motion Peripheral Interface Group .............................................................................. 11 4.3 Analog Interface Group ............................................................................................... 11 4.4 Power Interface Group ................................................................................................ 11 4.5 Test Interface Group ................................................................................................... 11 5 DC Characteristics .............................................................................................................. 13 5.1 Absolute Maximum Ratings ......................................................................................... 13 5.2 System Clock Frequency and Power Consumption .................................................... 13 5.3 Digital I/O DC Characteristics ...................................................................................... 14 5.4 Analog I/O (IFB+,IFB-,IFBO, AIN5+,AIN5-,AIN5O) DC Characteristics ...................... 15 5.5 Under Voltage Lockout DC characteristics.................................................................. 16 5.6 Itrip comparator DC characteristics ............................................................................. 16 5.7 CMEXT and AREF Characteristics ............................................................................. 16 6 AC Characteristics .............................................................................................................. 17 6.1 Digital PLL AC Characteristics .................................................................................... 17 6.2 Analog to Digital Converter AC Characteristics ........................................................... 18 6.3 Op amp AC Characteristics ......................................................................................... 19 6.4 SYNC to SVPWM and A/D Conversion AC Timing ..................................................... 20 6.5 GATEKILL to SVPWM AC Timing ............................................................................... 21 6.6 Itrip AC Timing ............................................................................................................. 21 6.7 Interrupt AC Timing ..................................................................................................... 22 6.8 I2C AC Timing .............................................................................................................. 22 6.9 SPI AC Timing ............................................................................................................. 23 6.10 UART AC Timing ......................................................................................................... 25 6.11 CAPTURE Input AC Timing ........................................................................................ 26 6.12 OTP Programming Timing ........................................................................................... 27 6.13 JTAG AC Timing ......................................................................................................... 28 7 I/O Structure ........................................................................................................................ 29 8 Pin List ................................................................................................................................ 32 9 Package Dimensions .......................................................................................................... 34 10 Part Marking Information ..................................................................................................... 35 11 Qualification Information ..................................................................................................... 35 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 List of Tables Table 1 Absolute Maximum Ratings ........................................................................................... 13 Table 2 System Clock Frequency ............................................................................................... 13 Table 3 Digital I/O DC Characteristics ........................................................................................ 14 Table 5 Analog I/O DC Characteristics ....................................................................................... 15 Table 6 UVcc DC Characteristics ............................................................................................... 16 Table 7 Itrip DC Characteristics .................................................................................................. 16 Table 8 CMEXT and AREF DC Characteristics .......................................................................... 16 Table 9 PLL AC Characteristics .................................................................................................. 17 Table 10 A/D Converter AC Characteristics ............................................................................... 18 Table 11 Current Sensing OP Amp AC Characteristics .............................................................. 19 Table 12 SYNC AC Characteristics ............................................................................................ 20 Table 13 GATEKILL to SVPWM AC Timing................................................................................ 21 Table 14 Itrip AC Timing ............................................................................................................. 21 Table 15 Interrupt AC Timing ...................................................................................................... 22 Table 16 I2C AC Timing .............................................................................................................. 22 Table 17 SPI Write AC Timing .................................................................................................... 23 Table 18 SPI Read AC Timing .................................................................................................... 24 Table 19 UART AC Timing ......................................................................................................... 25 Table 20 CAPTURE AC Timing .................................................................................................. 26 Table 21 OTP Programming Timing ........................................................................................... 27 Table 22 JTAG AC Timing .......................................................................................................... 28 Table 23 Pin List ......................................................................................................................... 33 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 List of Figures Figure 1 Typical Application Block Diagram Using IRMCK171 ........................................................................ 5 Figure 2 Pinout of IRMCK171 ........................................................................................................................... 6 Figure 3 Crystal circuit example ...................................................................................................................... 17 Figure 4 Voltage droop and S/H hold time ...................................................................................................... 18 Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. ........................................... 19 Figure 6 SYNC timing ..................................................................................................................................... 20 Figure 7 Gatekill timing ................................................................................................................................... 21 Figure 8 ITRIP timing ...................................................................................................................................... 21 Figure 9 Interrupt timing .................................................................................................................................. 22 Figure 10 I2C Timing ....................................................................................................................................... 22 Figure 11 SPI write timing ............................................................................................................................... 23 Figure 12 SPI read timing ............................................................................................................................... 24 Figure 13 UART timing.................................................................................................................................... 25 Figure 14 CAPTURE timing ............................................................................................................................ 26 Figure 15 OTP programming timing ................................................................................................................ 27 Figure 16 JTAG timing .................................................................................................................................... 28 Figure 17 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output .................................................... 29 Figure 18 All digital I/O except motor PWM output ......................................................................................... 29 Figure 19 RESET, GATEKILL I/O ................................................................................................................... 30 Figure 20 Analog input .................................................................................................................................... 30 Figure 21 Analog operational amplifier output and AREF I/O structure ....................................................... 30 Figure 22 VPP programming pin I/O structure ................................................................................................ 31 Figure 23 VSS and AVSS pin structure .......................................................................................................... 31 Figure 24 VDD1 and VDDCAP pin structure .................................................................................................. 31 Figure 25 XTAL0/XTAL1 pins structure .......................................................................................................... 31 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 1 Overview IRMCK171 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK171 provides a built-in closed loop sensorless control algorithm using the unique flexible Motion Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK171 also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCK171. IRMCK171 contains 32K bytes of OTP program ROM, The IRMCF171 contains 64K bytes of Flash RAM and intended for development purposes only while the IRMCK171 is intended for volume production. Both the development and ROM versions come in a 48-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production. Host Communication (RS232C) Appliance PM motor Drive Galvanic isolation 15V Passive PM motor FEilMlteIr IPM or SPM Or Gate signal IM motor IRS2336D IRMCK171 Power Supply 3.3V EOEpPtRioOnMal 2 8 Digital I/O 6 Analog Input Figure 1 Typical Application Block Diagram Using IRMCK171 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 2 Pinout Pin out shown is based on QFP48 pin package. L P3.3/INT1 P1.2/TXD P1.1/RXD RESET TCK TDI/P5.1 TDO/P5.3 TMS/P5.2 P3.0/CS1 GATEKIL VPP/P1.5 PWMUH 48 47 46 45 44 43 42 41 40 39 38 37 XTAL0 1 36 PWMVH XTAL1 2 35 PWMWH P1.0/T2 3 34 PWMUL SCL/SO-SI 4 33 PWMVL SDA/CS0 5 32 PWMWL IRMCK171 P1.3/SYNC/SCK 6 31 P3.1/AOPWM2 P1.4/CAP 7 30 VSS VDD1 8 (Top View) 29 VDD1 VSS 9 28 VDDCAP VDDCAP 10 27 AVSS P2.0/NMI 11 26 AIN5O P3.2/INT0 12 25 AIN5+ 13 14 15 16 17 18 19 20 21 22 23 24 OPWM1 AIN0 AIN1 AIN2 AIN3 AIN4 IFB- IFB+ IFBO CMEXT AREF AIN5- A 7/ 2. P Figure 2 Pinout of IRMCK171 6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 3 IRMCK171 Block Diagram and Main Functions IRMCK171 block diagram is shown in Figure 3. Mini-Motion 2 D/A 6 Monitoring (PWM) Control To IGBT Speed Low Loss gate drive Capture Engine command SVPWM GATEKILL Timer (MiniMCE) Counnter0,1,2 Single Shunt From Watchdog Motor Current shunt Timer Reconstruction resistor Program SND UART ROM/RAM Host RCV 32kB Motion IFB 3 IntDeIri/gfOaitscael SSDCAL PPPOOOI2RRRCTTT 123 LRCC8oAoPbcrMiUaetl 8bit uP Address/data bus DP2urRMRokabAAgCl yrPMMEatoem rt Control Bus MCoodnutrleosl MSAU//HDX AAAAAIIIIINNNNN10234 ainnapluotg 2kbyte 12kbyte Motion AIN53 8bit (8051) Interrupt Control microcontroller Motion Control Sequencer 4 Emulator JTAG Debugger 2 Ceramic 32MHz Resonator Freq (4MHz) Synthesizer 128MHz Figure 3 IRMCK171 Block Diagram IRMCK171 contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCETM) Sensorless FOC (complete sensorless field oriented control) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o 7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCETM program memory and dual port RAM (max 12K+2k byte) o MCETM control sequencer o • 8051 microcontroller Two 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to 24 discrete I/Os o Six-channel 12 bit A/D o  Buffered (current sensing) one channel (0 – 1.2V input)  Unbuffered seven channels (0 – 1.2V input) JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o I2C/SPI port o 32K byte OTP program ROM o 2K byte data RAM o 8 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 4 Application connection and Pin function SCylsotcekm C4rMysHtazl XXTTAALL01 SFyrnetqhueesnizceyr Scylsotcekm LoVSwep caLtcooesr s PPPWWWMMMVUUHLH Mic(RroSHc2oo3ns2tt rCo)ller PP11..12//RTXXDD RS232C CMoontitoronl PWM PPPWWWGMMMAWWVTLHLEKILL Modules Other Co(mI2Cm)unication SCSLD/SAO/C-SSI0 I2C/SPI DPuoartl 3.3V Memory PP11..30//ST2YNC/SCK (2kB) Single P1.4/CAP PORT1 & Shunt MCE Motion Current Memory Control Sensing (12kB) Sequencer GaHteV DICrive Digital I/O IRS2336D Control P2.0/NMI PORT2 AVREF IFBC+ S/H IFBC- P3.0/CS1 IFBCO PP33..23//IINNTT01 PORT3 Timers AIN5+ AVREF S/H AIN5- AIN5O Watchdog Timer 12bit A/D & Motor Analog Output P2.7/AOPWM1 PWM1 LRoAcMal MUX 4 AIN0,AIN1,AIN2, AIN3 (2kByte) Other analog input (0-1.2V) AREF CMEXT OptioRneafel rEexntceern (a0l. 6VVo)ltage TCLK JTAG Control P5.1/TDI JTAG Program AVSS (OTP programming P5.2/TMS Interface RAM & Emulation) TDO (32kByte) AVDD RESET RESET ProgOraTmPming P1.5/VPP SRyessteemt 8051 Voltage CPU (6.5V) VDD1 3.3V VSS IRMCK171 3.3V Vo1l.t8aVge VDDCAP 1.8V Regulator Figure 4 IRMCK171 Connection Diagram 9 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD Output, Transmit data from IRMCK171 P1.1/RXD Input, Receive data to IRMCK171 Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.1/RXD Input/output port 1.1, can be configured as RXD input P1.2/TXD Input/output port 1.2, can be configured as TXD output P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input P1.5/VPP Input/output port 1.5, or OTP programming voltage P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt input P3.2/INT0 Input/output port 3.2, can be configured as INT0 input P2.7/AOPWM1 Input/output port 2.7, can be configured as AOPWM1 output P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 P3.1/AOPWM2 Input/output port 3.1, can be configured as AOPWM2 output P3.3/INT1 Input/output port 3.3, can be configured as INT1 input P5.1/TDI Input port 5.1, configured as JTAG port by default P5.2/TMS Input port 5.2, configured as JTAG port by default Analog Output Interface P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency Crystal Interface XTAL0 Input, connected to crystal XTAL1 Output, connected to crystal Reset Interface RESET Input and Output, system reset, doesn’t require external RC time constant I2C Interface SCL/SO-SI Output, I2C clock output, or SPI data SDA/CS0 Input/output, I2C Data line or SPI chip select 0 I2C/SPI Interface SCL/SO-SI Output, I2C clock output, or SPI data SDA/CS0 Input/output, I2C data line or SPI chip select 0 P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 10 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 4.2 Motion Peripheral Interface Group PWM PWMUH Output, PWM phase U high side gate signal, internally pulled down by 58kΩ PWMUL Output, PWM phase U low side gate signal, internally pulled down by 58kΩ PWMVH Output, PWM phase V high side gate signal, internally pulled down by 58kΩ PWMVL Output, PWM phase V low side gate signal, internally pulled down by 58kΩ PWMWH Output, PWM phase W high side gate signal, internally pulled down by 58kΩ PWMWL Output, PWM phase W low side gate signal, internally pulled down by 58kΩ Fault GATEKILL Input, upon assertion, this negates all six PWM signals, active low, internally pulled up by 70kΩ 4.3 Analog Interface Group AVSS Analog power return, (analog internal 1.8V power is shared with VDDCAP) AREF 0.6V buffered output CMEXT Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected. IFB+ Input, Operational amplifier positive input for shunt resistor current sensing IFB- Input, Operational amplifier negative input for shunt resistor current sensing IFBO Output, Operational amplifier output for shunt resistor current sensing AIN0 Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input AIN1 Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused AIN2 Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused AIN3 Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused AIN4 Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused AIN5+ Input, Operational amplifier positive input for shunt resistor current sensing AIN5- Input, Operational amplifier negative input for shunt resistor current sensing AIN5O Output, Operational amplifier output for AIN5 output, there is a single sample/hold circuit on the output 4.4 Power Interface Group VDD1 Digital power (3.3V) VDDCAP Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. VSS Digital common 4.5 Test Interface Group P5.2/TMS JTAG test mode input or input/output digital port TDO JTAG data output P5.1/TDI JTAG data input, or input/output digital port 11 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 TCK JTAG test clock 12 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol Parameter Min Typ Max Condition V Supply Voltage -0.3 V - 3.6 V Respect to VSS DD1 V Analog Input Voltage -0.3 V - 1.98 V Respect to AVSS IA V Digital Input Voltage -0.3 V - 6.0 V Respect to VSS ID V OTP Programming -0.3V - 7.0V Respect to VSS PP voltage T Ambient Temperature -40 ˚C - 85 ˚C A T Storage Temperature -65 ˚C - 150 ˚C S Table 1 Absolute Maximum Ratings Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption C = 1nF, C = 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. AREF MEXT Symbol Parameter Min Typ Max Unit SYSCLK System Clock 32 - 128 MHz P Power consumption 1601) 200 mW D Table 2 System Clock Frequency Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with a actual motor running by a typical MCE application program and 8051 code. 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 5.3 Digital I/O DC Characteristics Symbol Parameter Min Typ Max Condition V Supply Voltage 3.0 V 3.3 V 3.6 V Recommended DD1 V OTP Programming 6.70V 6.75V 6.80V Recommended PP voltage V Input Low Voltage -0.3 V - 0.8 V Recommended IL V Input High Voltage 2.0 V 3.6 V Recommended IH C Input capacitance - 3.6 pF - (1) IN I Input leakage current ±10 nA ±1 μA V = 3.3 V or 0 V L O I (2) Low level output current 8.9 mA 13.2 mA 15.2 mA V = 0.4 V OL1 OL (1) I (2) High level output 12.4 mA 24.8 mA 38 mA V = 2.4 V OH1 OH current (1) I (3) Low level output current 17.9 mA 26.3 mA 33.4 mA V = 0.4 V OL2 OL (1) I (3) High level output 24.6 mA 49.5 mA 81 mA V = 2.4 V OH2 OH current (1) Table 3 Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins. 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 5.4 Analog I/O (IFB+,IFB-,IFBO, AIN5+,AIN5-,AIN5O) DC Characteristics C = 1nF, C = 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. AREF MEXT Symbol Parameter Min Typ Max Condition V Input Offset Voltage - - 26 mV OFFSET V Input Voltage Range 0 V 1.2 V Recommended I V OP amp output 50 mV - 1.2 V OUTSW operating range (1) C Input capacitance - 3.6 pF - (1) IN R OP amp feedback 5 kΩ - 20 kΩ Requested FDBK resistor between IFBO and IFB- OP Operating Close loop 80 db - - (1) GAINCL Gain CMRR Common Mode - 80 db - (1) Rejection Ratio I Op amp output source - 1 mA - V = 0.6 V SRC OUT current (1) I Op amp output sink - 100 μA - V = 0.6 V SNK OUT current (1) Table 4 Analog I/O DC Characteristics Note: (1) Data guaranteed by design. 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Condition UV UVcc positive going 2.78 V 3.04 V 3.23 V (1) CC+ Threshold UV UVcc negative going 2.78 V 2.97 V 3.23 V CC- Threshold UV H UVcc Hysteresys - 73 mV - (1) CC Table 5 UVcc DC Characteristics Note: (1) Data guaranteed by design. 5.6 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Typ Max Condition Itrip Itrip positive going - 1.22V - + Threshold Itrip Itrip negative going - 1.10V - - Threshold ItripH Itrip Hysteresys - 120mV - Table 6 Itrip DC Characteristics 5.7 CMEXT and AREF Characteristics C = 1nF, C = 100nF. Unless specified, Ta = 25˚C. AREF MEXT Symbol Parameter Min Typ Max Condition V CMEXT voltage 495 mV 600 mV 700 mV VDD1 = 3.3 V(1) CM V Buffer Output Voltage 495 mV 600 mV 700 mV VDD1 = 3.3 V AREF ∆V Load regulation (V -0.6) - 1 mV - (1) o DC PSRR Power Supply Rejection - 75 db - (1) Ratio Table 7 CMEXT and AREF DC Characteristics Note: (1) Data guaranteed by design. 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol Parameter Min Typ Max Condition F Crystal input 3.2 MHz 4 MHz 60 MHz (1) CLKIN frequency (see figure below) F Internal clock 32 MHz 50 MHz 128 MHz (1) PLL frequency F Sleep mode output F ÷ 256 - - (1) LWPW CLKIN frequency J Short time jitter - 200 psec - (1) S D Duty cycle - 50 % - (1) T PLL lock time - - 500 μsec (1) LOCK Table 8 PLL AC Characteristics Note: (1) Data guaranteed by design. R1=1M R2=1K Xtal C1=30PF C2=30PF Figure 3 Crystal circuit example 17 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Condition T Conversion time - - 2.05 μsec (1) CONV T Sample/Hold maximum - - 10 μsec Voltage droop ≤ 15 HOLD hold time LSB (see figure below) Table 9 A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 4 Voltage droop and S/H hold time 18 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Condition OP OP amp slew rate - 10 V/μsec - VDD1 = 3.3 V, CL SR = 33 pF (1) OP OP input impedance - 108 Ω - (1) (2) IMP T Settling time - 400 ns - VDD1 = 3.3 V, CL SET = 33 pF (1) Table 10 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 5. Here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. IRMCK171 IC External AVREF components IFBC+ IFBC- IFBCO 47pF Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. 19 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.4 SYNC to SVPWM and A/D Conversion AC Timing t wSYNC SYNC t dSYNC1 IU,IV,IW t dSYNC2 AINx t dSYNC3 PWMUx,PWMVx,PWMWx Figure 6 SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit t SYNC pulse width - 32 - SYSCLK wSYNC t SYNC to current - - 100 SYSCLK dSYNC1 feedback conversion time t SYNC to AIN0-5 analog - - 200 SYSCLK dSYNC2 input conversion time (1) t SYNC to PWM output - - 2 SYSCLK dSYNC3 delay time Table 11 SYNC AC Characteristics Note: (1) AIN1 through AIN5 channels are converted once every 6 SYNC events 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.5 GATEKILL to SVPWM AC Timing t wGK GATEKILL t dGK PWMUx,PWMVx,PWMWx Figure 7 Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit t GATEKILL pulse width 32 - - SYSCLK wGK t GATEKILL to PWM - - 100 SYSCLK dGK output delay Table 12 GATEKILL to SVPWM AC Timing 6.6 Itrip AC Timing Itrip t Itrip PWMUH,PWMUL, PWMVH,PWMVH, PWMWH,PWMWL Figure 8 ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit t Itrip propagation - - 100(sysclk)+1.0usec SYSCLK+usec ITRIP delay Table 13 Itrip AC Timing 21 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.7 Interrupt AC Timing twINT P3.2/INT0 P3.3/INT1 tdINT Internal Program Internal Vector Fetch Counter Figure 9 Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit t INT0, INT1 Interrupt 4 - - SYSCLK wINT Assertion Time t INT0, INT1 latency - - 4 SYSCLK dINT Table 14 Interrupt AC Timing 2 6.8 I C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2WHOLD tI2RSETUP tI2EN1 tI2ST2 tI2RHOLD tI2EN2 SDA Figure 10 I2C Timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T I2C clock period 10 - 8192 SYSCLK I2CLK t I2C SDA start time 0.25 - - T I2ST1 I2CLK t I2C SCL start time 0.25 - - T I2ST2 I2CLK t I2C write setup time 0.25 - - T I2WSETUP I2CLK t I2C write hold time 0.25 - - T I2WHOLD I2CLK t I2C read setup time I2C filter time(1) - - SYSCLK I2RSETUP t I2C read hold time 1 - - SYSCLK I2RHOLD Table 15 I2C AC Timing Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication. 22 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.9 SPI AC Timing SPI Write AC timing TSPICLK P1.3/SYNC/SCK tWRDELAY tSPICLKHT tSPICLKLT SCL/SO-SI Bit7(MSB) Bit0(LSB) tCSDELAY tCSHOLD tCSHIGH SDA/CS0 P3.0/INT2/CS1 Figure 11 SPI write timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T SPI clock period 4 - - SYSCLK SPICLK t SPI clock high time - 1/2 - T SPICLKHT SPICLK t SPI clock low time - 1/2 - T SPICLKLT SPICLK t CS to data delay time - - 10 nsec CSDELAY t CLK falling edge to data - - 10 nsec WRDELAY delay time t CS high time between two 1 - - T CSHIGH SPICLK consecutive byte transfer t CS hold time - 1 - T CSHOLD SPICLK Table 16 SPI Write AC Timing 23 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 SPI Read AC Timing TSPICLK P1.3/SYNC/SCK tRDHOLD tSPICLKHT tSPICLKLT tRDSU SCL/SO-SI Bit7(MSB) Bit0(LSB) tCSRD tCSHOLD tCSHIGH SDA/CS0 P3.0/INT2/CS1 Figure 12 SPI read timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T SPI clock period 4 - - SYSCLK SPICLK t SPI clock high time - 1/2 - T SPICLKHT SPICLK t SPI clock low time - 1/2 - T SPICLKLT SPICLK t CS to data delay time - - 10 nsec CSRD t SPI read data setup time 10 - - nsec RDSU t SPI read data hold time 10 - - nsec RDHOLD t CS high time between two 1 - - T CSHIGH SPICLK consecutive byte transfer t CS hold time - 1 - T CSHOLD SPICLK Table 17 SPI Read AC Timing 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.10 UART AC Timing TBAUD TXD Start Bit Data and Parity Bit Stop Bit RXD TUARTFIL Figure 13 UART timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T Baud Rate Period - 57600 - bit/sec BAUD T UART sampling filter - 1/16 - T UARTFIL BAUD period (1) Table 18 UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 T . If three sampled values do not agree, then UART noise error is generated. BAUD 25 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.11 CAPTURE Input AC Timing TCAPCLK P1.4/CAP tCAPHIGH tCAPLOW tCRDELAY CREV(H,L) Internal register tCLDELAY CLAST(H,L) Internal register tINTDELAY Interrupt Vector Fetch Interrupt Figure 14 CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T CAPTURE input period 8 - - SYSCLK CAPCLK t CAPTURE input high 4 - - SYSCLK CAPHIGH time t CAPTURE input low time 4 - - SYSCLK CAPLOW t CAPTURE falling edge to - - 4 SYSCLK CRDELAY capture register latch time t CAPTURE rising edge to - - 4 SYSCLK CLDELAY capture register latch time t CAPTURE input interrupt - - 4 SYSCLK INTDELAY latency time Table 19 CAPTURE AC Timing 26 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.12 OTP Programming Timing 6.75V VDD/VSS/Floating VDD/VSS/Floating VPP TVPS TVPH TCK TDI/TMS Figure 15 OTP programming timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T VPP Setup Time 10 - - nsec VPS T VPP Hold Time 15 - - nsec VPH Table 20 OTP Programming Timing 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 6.13 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 16 JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max Unit T TCK Period - - 50 MHz JCLK t TCK High Period 10 - - nsec JHIGH t TCK Low Period 10 - - nsec JLOW t TCK to TDO propagation delay 0 - 5 nsec CO time t TDI/TMS setup time 4 - - nsec JSETUP t TDI/TMS hold time 0 - - nsec JHOLD Table 21 JTAG AC Timing 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 7 I/O Structure The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270Ω 6.0V 58kΩ VSS Figure 17 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output The following figure shows the digital I/O structure except the motor PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70kΩ 6.0V PIN 270Ω 6.0V VSS Figure 18 All digital I/O except motor PWM output 29 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 The following figure shows RESET and GATEKILL I/O structure. VDD1 (3.3V) RESET GATEKILL 70kΩ circuit 6.0V PIN 270Ω 6.0V VSS Figure 19 RESET, GATEKILL I/O The following figure shows the analog input structure. VDDCAP(1.8V) Analog input 6.0V PIN 1 Ω Analog Circuit 6.0V AVSS Figure 20 Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. VDDCAP(1.8V) Analog output 6.0V PIN Analog Circuit 6.0V AVSS Figure 21 Analog operational amplifier output and AREF I/O structure 30 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 The following figure shows the VPP pin structure PIN 270Ω 8.0V VSS Figure 22 VPP programming pin I/O structure The following figure shows the VSS and AVSS pins structure VDD1 AVDD PIN 6.0V Figure 23 VSS and AVSS pin structure The following figure shows the VDD1 and VDDCAP pin structure PIN 6.0V VSS Figure 24 VDD1 and VDDCAP pin structure The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 Ω 6.0V VSS Figure 25 XTAL0/XTAL1 pins structure 31 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 8 Pin List Pin Internal Pin Number Pin Name Pull-up Type Description /Pull-down 1 XTAL0 I Crystal input 2 XTAL1 O Crystal output 3 P1.0/T2 I/O Discrete programmable I/O or Timer/Counter 2 input 4 SCL/SO-SI I/O I2C clock output (open drain, need pull up) or SPI data 5 SDA/CS0 I/O I2C data (open drain, need pull up) or SPI Chip Select 0 6 P1.3/SYNC/SCK I/O Discrete programmable I/O or SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM 7 P1.4/CAP I/O Discrete programmable I/O or Capture timer input 8 VDD1 P 3.3V digital power 9 VSS P Digital common 10 VDDCAP P Internal 1.8V output, Capacitor(s) to be connected 11 P2.0/NMI I/O Discrete programmable I/O or Non-maskable Interrupt input 12 P3.2/INT0 I/O Discrete programmable I/O or Interrupt 0 input 13 P2.7/AOPWM1 I/O Discrete programmable I/O or PWM 1 digital output 14 AIN0 I Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused 15 AIN1 I Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused 16 AIN2 I Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused 17 AIN3 I Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused 18 AIN4 I Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused 19 IFB- I Single shunt current sensing OP amp input (-) 20 IFB+ I Single shunt current sensing OP amp input (+) 21 IFBO O Single shunt current sensing OP amp output 22 CMEXT O Unbuffered 0.6V output. Capacitor needs to be connected. 23 AREF O Analog reference voltage output (0.6V) 24 AIN5- I Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused 25 AIN5+ I Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused 26 AIN5O O Analog output 5, 0-1.2V range, 27 AVSS P Analog common 28 VDDCAP P Internal 1.8V output, Capacitor(s) to be connected 29 VDD1 P 3.3V digital power 30 VSS P Digital common 31 P3.1/AOPWM2 I/O Discrete programmable I/O or PWM 2 digital output 32 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 Pin Internal Pin Number Pin Name Pull-up Type Description /Pull-down 32 PWMWL 58 kΩ Pull O PWM gate drive for phase W low side, configurable down either high or low true. 33 PWMVL 58 kΩ Pull O PWM gate drive for phase V low side, configurable down either high or low true 34 PWMUL 58 kΩ Pull O PWM gate drive for phase U low side, configurable down either high or low true 35 PWMWH 58 kΩ Pull O PWM gate drive for phase W high side, configurable down either high or low true 36 PWMVH 58 kΩ Pull O PWM gate drive for phase V high side, configurable down either high or low true 37 PWMUH 58 kΩ Pull O PWM gate drive for phase U high side, configurable down either high or low true 38 P1.5/VPP I/O OTP programming power (6.5V) or Discrete P programmable I/O. 39 GATEKILL 70 kΩ Pull up I PWM shutdown input, 2-μsec digital filter, configurable either high or low true. 40 P3.0/INT2/CS1 70 kΩ Pull up I/O Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 41 P5.2/TMS I/O JTAG test mode select or Discrete I/O 42 TDO O JTAG test data output 43 P5.1/TDI I/O JTAG test data input or Discrete I/O 44 TCK I JTAG test clock 45 RESET I/O Reset, low true, Schmitt trigger input 46 P1.1/RXD I/O UART receiver input or Discrete programmable I/O 47 P1.1/RXD I/O UART transmitter output or Discrete programmable I/O 48 P3.3/INT1 I/O Interrupt 1 input or Discrete I/O Table 22 Pin List 33 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 9 Package Dimensions 34 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 10 Part Marking Information Part Number IRMCK171 IR Logo YWWP Date Code XXXXXX Production Lot Pin 1 Indentifier 11 Qualification Information †† Industrial Qualification Level (per JEDEC JESD 47E) MSL3††† Moisture Sensitivity Level (per IPC/JEDEC J-STD-020C) Class B Machine Model (per JEDEC standard JESD22-A114D) ESD Class 2 Human Body Model (per EIA/JEDEC standard EIA/JESD22-A115-A) RoHS Compliant Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 35 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

IRMCK171 Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 36 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014

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