IRFR110, SiHFR110 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY • Dynamic dV/dt Rating VDS (V) 100 • Repetitive Avalanche Rated RDS(on) () VGS = 10 V 0.54 • Surface Mount (IRFR110, SiHFR110) Q (Max.) (nC) 8.3 • Available in Tape and Reel g Q (nC) 2.3 • Fast Switching gs • Ease of Paralleling Q (nC) 3.8 gd • Material categorization: For definitions of Configuration Single compliance please see www.vishay.com/doc?99912 D DESCRIPTION DPAK Third generation power MOSFETs from Vishay provide the (TO-252) designer with the best combination of fast switching, ruggedized device design, low on-resistance and D G cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. Power S G S dissipation levels up to 1.5 W are possible in typical surface mount applications. N-Channel MOSFET ORDERING INFORMATION Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) Lead (Pb)-free and Halogen-free SiHFR110-GE3 SiHFR110TRL-GE3 SiHFR110TR-GE3 SiHFR110TRR-GE3 IRFR110PbF IRFR110TRLPbFa IRFR110TRPbFa IRFR110TRRPbFa Lead (Pb)-free SiHFR110-E3 SiHFR110TL-E3a SiHFR110T-E3a SiHFR110TR-E3a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) C PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 100 DS V Gate-Source Voltage V ± 20 GS T = 25 °C 4.3 Continuous Drain Current V at 10 V C I GS T = 100 °C D 2.7 A C Pulsed Drain Currenta I 17 DM Linear Derating Factor 0.20 W/°C Linear Derating Factor (PCB Mount)e 0.020 Single Pulse Avalanche Energyb E 75 mJ AS Repetitive Avalanche Currenta I 4.3 A AR Repetitive Avalanche Energya E 2.5 mJ AR Maximum Power Dissipation T = 25 °C 25 C P W Maximum Power Dissipation (PCB Mount)e T = 25 °C D 2.5 A Peak Diode Recovery dV/dtc dV/dt 5.5 V/ns Operating Junction and Storage Temperature Range T , T - 55 to + 150 J stg °C Soldering Recommendations (Peak Temperature)d for 10 s 260 Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 8.1 mH, Rg = 25 , IAS = 4.3 A (see fig. 12). c. ISD  5.6 A, dI/dt  75 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S13-0171-Rev. F, 04-Feb-13 1 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum Junction-to-Ambient R - 110 thJA Maximum Junction-to-Ambient R - 50 °C/W (PCB Mount)a thJA Maximum Junction-to-Case (Drain) R - 5.0 thJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (T = 25 °C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V V = 0 V, I = 250 μA 100 - - V DS GS D VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.13 - V/°C Gate-Source Threshold Voltage V V = V , I = 250 μA 2.0 - 4.0 V GS(th) DS GS D Gate-Source Leakage I V = ± 20 V - - ± 100 nA GSS GS V = 100 V, V = 0 V - - 25 DS GS Zero Gate Voltage Drain Current I μA DSS V = 80 V, V = 0 V, T = 125 °C - - 250 DS GS J Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 2.6 Ab - - 0.54  Forward Transconductance g V = 50 V, I = 2.6 A 1.6 - - S fs DS D Dynamic Input Capacitance C - 180 - iss V = 0 V, GS Output Capacitance C V = 25 V, - 80 - pF oss DS f = 1.0 MHz, see fig. 5 Reverse Transfer Capacitance C - 15 - rss Total Gate Charge Qg - - 8.3 I = 5.6 A, V = 80 V, Gate-Source Charge Qgs VGS = 10 V Dsee fig. 6 aDnSd 13b - - 2.3 nC Gate-Drain Charge Qgd - - 3.8 Turn-On Delay Time t - 6.9 - d(on) Rise Time tr VDD = 50 V, ID = 5.6 A, - 16 - ns Turn-Off Delay Time td(off) Rg = 24 , RD = 8.4 , see fig. 10b - 15 - Fall Time t - 9.4 - f Between lead, Internal Drain Inductance L D - 4.5 - D 6 mm (0.25") from package and center of nH G Internal Source Inductance L die contact - 7.5 - S S Drain-Source Body Diode Characteristics MOSFET symbol Continuous Source-Drain Diode Current IS showing the D - - 4.3 integral reverse A G Pulsed Diode Forward Currenta I p - n junction diode - - 17 SM S Body Diode Voltage V T = 25 °C, I = 4.3 A, V = 0 Vb - - 2.5 V SD J S GS Body Diode Reverse Recovery Time t - 100 200 ns rr T = 25 °C, I = 5.6 A, dI/dt = 100 A/μsb J F Body Diode Reverse Recovery Charge Q - 0.44 0.88 μC rr Forward Turn-On Time t Intrinsic turn-on time is negligible (turn-on is dominated by L and L ) on S D Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. S13-0171-Rev. F, 04-Feb-13 2 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, T = 25 °C Fig. 3 - Typical Transfer Characteristics C Fig. 2 -Typical Output Characteristics, T = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature C S13-0171-Rev. F, 04-Feb-13 3 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S13-0171-Rev. F, 04-Feb-13 4 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix R D V DS V GS D.U.T. R G + -VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit V DS 90 % 10 % V Fig. 9 - Maximum Drain Current vs. Case Temperature GS t t t t d(on) r d(off) f Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L VDS V Vary tp to obtain DS tp required IAS VDD RG D.U.T. + V I - DD A VDS AS 10 V tp 0.01 Ω I AS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms S13-0171-Rev. F, 04-Feb-13 5 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q 50 kΩ G 10 V 12 V 0.2 µF 0.3 µF QGS QGD + V D.U.T. - DS V G V GS 3 mA Charge I I G D Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit S13-0171-Rev. F, 04-Feb-13 6 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRFR110, SiHFR110 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. (cid:129) Low stray inductance (cid:129) Ground plane (cid:129) Low leakage inductance current transformer - + - + - Rg (cid:129) dV/dt controlled by Rg + (cid:129) Driver same type as D.U.T. V - DD (cid:129) ISD controlled by duty factor “D” (cid:129) D.U.T. - device under test Driver gate drive P.W. Period D = P.W. Period V = 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt V DD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. V = 5 V for logic level devices GS Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91265. S13-0171-Rev. F, 04-Feb-13 7 Document Number: 91265 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information www.vishay.com Vishay Siliconix TO-252AA Case Outline E A MILLIMETERS INCHES C2 b3 DIM. MIN. MAX. MIN. MAX. 3 A 2.18 2.38 0.086 0.094 L A1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 D b3 4.95 5.46 0.195 0.215 H C 0.46 0.61 0.018 0.024 C2 0.46 0.89 0.018 0.035 L4 5 D 5.97 6.22 0.235 0.245 L L m) D1 4.10 - 0.161 - m 5 E 6.35 6.73 0.250 0.265 0. b b2 ght ( C E1 4.32 - 0.170 - e ei H 9.40 10.41 0.370 0.410 h A1 e1 ne e 2.28 BSC 0.090 BSC a pl e1 4.56 BSC 0.180 BSC e g a L 1.40 1.78 0.055 0.070 g L3 0.89 1.27 0.035 0.050 1 D L4 - 1.02 - 0.040 L5 1.01 1.52 0.040 0.060 ECN: T16-0236-Rev. P, 16-May-16 DWG: 5347 E1 Notes • Dimension L3 is for reference only. Revision: 16-May-16 1 Document Number: 71197 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix TO-251AA (HIGH VOLTAGE) 4 3 A E1 Thermal PAD E A 4 b4 0.0100.25 M C A B c2 L2 4 A θ2 θ1 D1 4 B D 3 C Seating 5 plane L1 L3 C C (Datum A) L B B A A1 3 x b2 c 3 x b View A - A 2 x e 0.0100.25 M C A B Base 5 metal Plating b1, b3 Lead tip (c) c1 5 (b, b2) Section B - B and C - C MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 2.18 2.39 0.086 0.094 D1 5.21 - 0.205 - A1 0.89 1.14 0.035 0.045 E 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 E1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 BSC 2.29 BSC b2 0.76 1.14 0.030 0.045 L 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 L1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 L2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 L3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 θ1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 θ2 25' 35' 25' 35' D 5.97 6.22 0.235 0.245 ECN: S-82111-Rev. A, 15-Sep-08 DWG: 5968 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension are shown in inches and millimeters. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions b4, L2, E1 and D1. 5. Lead dimension uncontrolled in L3. 6. Dimension b1, b3 and c1 apply to base metal only. 7. Outline conforms to JEDEC outline TO-251AA. Document Number: 91362 www.vishay.com Revision: 15-Sep-08 1

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 (5.690) 3 0) 4 8 2 1 0. 6. ( 0.420 10.668) ( 7 2) 8 0 0 2 0. 2. ( 0 6) 9 8 0 2 0. 2. ( 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72594 www.vishay.com Revision: 21-Jan-08 3

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: V ishay: IRFR110TRPBF IRFR110TRLPBF IRFR110TRRPBF IRFR110 IRFR110TR IRFR110TRL IRFU110 IRFU110PBF IRFR110PBF