PD - 95531A IRF540ZPbF IRF540ZSPbF IRF540ZLPbF Features HEXFET® Power MOSFET (cid:0) Advanced Process Technology (cid:0) Ultra Low On-Resistance D V = 100V (cid:0) 175°C Operating Temperature DSS (cid:0) Fast Switching (cid:0) Repetitive Avalanche Allowed up to Tjmax R = 26.5mΩ DS(on) (cid:0) Lead-Free G I = 36A Description D S This HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating.These features combine to make this design an extremely efficient and reliable device for use in a wide variety of TO-220AB D2Pak TO-262 applications. IRF540ZPbF IRF540ZSPbF IRF540ZLPbF Absolute Maximum Ratings Parameter Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 36 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 25 A IDM Pulsed Drain Current (cid:0) 140 PD @TC = 25°C Power Dissipation 92 W Linear Derating Factor 0.61 W/°C VGS Gate-to-Source Voltage ± 20 V EAS (Thermally limited) Single Pulse Avalanche Energy(cid:1) 83 mJ EAS (Tested ) Single Pulse Avalanche Energy Tested Value (cid:2) 120 IAR Avalanche Current(cid:3)(cid:0) See Fig.12a, 12b, 15, 16 A EAR Repetitive Avalanche Energy (cid:4) mJ TJ Operating Junction and -55 to + 175 TSTG Storage Temperature Range °C Soldering Temperature, for 10 seconds 300 (1.6mm from case ) Mounting Torque, 6-32 or M3 screw (cid:5) 10 lbf(cid:7)in (1.1N(cid:7)m) Thermal Resistance Parameter Typ. Max. Units RθJC Junction-to-Case ––– 1.64 °C/W RθCS Case-to-Sink, Flat Greased Surface (cid:5) 0.50 ––– RθJA Junction-to-Ambient (cid:5) ––– 62 RθJA Junction-to-Ambient (PCB Mount) (cid:6) ––– 40 www.irf.com 1 (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:3)(cid:6)(cid:1)

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) Electrical Characteristics @ T = 25°C (unless otherwise specified) J Parameter Min. Typ. Max. Units Conditions V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.093 ––– V/°C Reference to 25°C, ID = 1mA RDS(on) Static Drain-to-Source On-Resistance ––– 21 26.5 mΩ VGS = 10V, ID = 22A (cid:3) VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA gfs Forward Transconductance 36 ––– ––– V V = 25V, I = 22A DS D IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V ––– ––– 250 V = 100V, V = 0V, T = 125°C DS GS J IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA VGS = 20V Gate-to-Source Reverse Leakage ––– ––– -200 V = -20V GS Qg Total Gate Charge ––– 42 63 ID = 22A Qgs Gate-to-Source Charge ––– 9.7 ––– nC VDS = 80V Qgd Gate-to-Drain ("Miller") Charge ––– 15 ––– VGS = 10V (cid:3) td(on) Turn-On Delay Time ––– 15 ––– VDD = 50V tr Rise Time ––– 51 ––– ID = 22A td(off) Turn-Off Delay Time ––– 43 ––– ns RG = 12 Ω tf Fall Time ––– 39 ––– VGS = 10V (cid:3) LD Internal Drain Inductance ––– 4.5 ––– Between lead, D nH 6mm (0.25in.) LS Internal Source Inductance ––– 7.5 ––– from package G and center of die contact S Ciss Input Capacitance ––– 1770 ––– VGS = 0V Coss Output Capacitance ––– 180 ––– VDS = 25V Crss Reverse Transfer Capacitance ––– 100 ––– pF ƒ = 1.0MHz Coss Output Capacitance ––– 730 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz Coss Output Capacitance ––– 110 ––– VGS = 0V, VDS = 80V, ƒ = 1.0MHz Coss eff. Effective Output Capacitance ––– 170 ––– VGS = 0V, VDS = 0V to 80V (cid:2) Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions IS Continuous Source Current ––– ––– 36 MOSFET symbol (Body Diode) A showing the ISM Pulsed Source Current ––– ––– 140 integral reverse (Body Diode)(cid:0)(cid:1) p-n junction diode. VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 22A, VGS = 0V (cid:3) trr Reverse Recovery Time ––– 33 50 ns TJ = 25°C, IF = 22A, VDD = 50V Qrr Reverse Recovery Charge ––– 41 62 nC di/dt = 100A/µs (cid:3) ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) 1000 1000 VGS VGS TOP 15V TOP 15V 10V 10V A) 8.0V A) 8.0V n(t 76..00VV n(t 76..00VV uerr 100 55..50VV uerr 100 55..50VV C BOTTOM 4.5V C BOTTOM 4.5V e e c c ur ur o o S S o- o- 4.5V n-t 10 n-t 10 ai ai Dr Dr ,D 4.5V ,D I I 60µs PULSE WIDTH 60µs PULSE WIDTH Tj = 25°C Tj = 175°C 1 1 0.1 1 10 100 00.1 11 1100 110000 V , Drain-to-Source Voltage (V) V , Drain-to-Source Voltage (V) DS DS Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 80 Α() Se() TJ = 175°C nt nc 60 e a Curr 100 TJ = 175°C duct e on Sanoouc--rti 10 wTadanscr r 40 TJ = 25°C Dr TJ = 25°C or 20 I,D VDS = 25V GFsf, VDS = 10V 60µs PULSE WIDTH 380µs PULSE WIDTH 1 0 4.0 5.0 6.0 7.0 0 10 20 30 40 50 V , Gate-to-Source Voltage (V) GS ID, Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance Vs. Drain Current www.irf.com 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) 3000 20 VGS = 0V, f = 1 MHZ I = 22A D Ciss = Cgs + Cgd, Cds SHORTED 2500 CCrss == CCgd + C Ve() 16 VVDDSS== 5800VV Fep() 2000 Cissoss ds gd Vageot l 12 VDS= 20V c c ancti 1500 Sour pa o- 8 Ca e-t C , 1000 Gat , S 4 G 500 Coss V FOR TEST CIRCUIT Crss SEE FIGURE 13 0 0 0 10 20 30 40 50 60 1 10 100 Q Total Gate Charge (nC) VDS, Drain-to-Source Voltage (V) G Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs. Drain-to-Source Voltage Gate-to-Source Voltage 1000.0 1000 OPERATION IN THIS AREA LIMITED BY R (on) DS A) A) nt ( 100.0 n(t 100 e e urr urr C T = 175°C C n J e Dari 10.0 oucr 10 100µsec e S vesr no--t ReI, DS 1.0 TJ = 25°C DarI, iD 1 Tc = 25°C 1msec VGS = 0V Tj = 175°C 10msec Single Pulse 0.1 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 1000 VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Voltage 4 www.irf.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) 40 3.0 ec ID = 22A n ast VGS = 10V si 2.5 e 30 R A) n CDnuenarr(r t , I iD 1200 ODSanoouecr--rt, iRDSon() mNoaedz)(r li 112...050 0 0.5 25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (°C) TJ , Junction Temperature (°C) Fig 9. Maximum Drain Current Vs. Fig 10. Normalized On-Resistance Case Temperature Vs. Temperature 10 )CJ 1 D = 0.50 h t Z 0.20 e( 0.10 s n o 0.1 0.05 p s e 0.02 R a l 0.01 m er 0.01 SINGLE PULSE h T ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) 180 15V mJ) ID 160 y( TOP 8.3A VDS L DRIVER Enegr 140 BOTTOM1240AA e 120 h RG D.U.T + nc IAS - VDDA aavl 100 2V0GVS tp 0.01Ω Aes 80 ul P 60 Fig 12a. Unclamped Inductive Test Circuit e gl V(BR)DSS Sni 40 tp , S 20 A E 0 25 50 75 100 125 150 175 Starting T , Junction Temperature (°C) J IAS Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Q G (cid:1)(cid:2)(cid:3)(cid:4) Q Q GS GD 4.0 VG Ve() 3.5 g a otl Charge Vod l 3.0 ID = 250µA h Fig 13a. Basic Gate Charge Waveform s e hr e t 2.5 at G h) S(t 2.0 L G V VCC DUT 0 1.5 1K -75 -50 -25 0 25 50 75 100 125 150 175 TJ , Temperature ( °C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature 6 www.irf.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) 1000 Duty Cycle = Single Pulse 100 Allowed avalanche Current vs A) en(t 0.01 aavsasulamncinhge ∆pTuj l=se 2w5id°Cth , dueta vto urr avalanche losses C 10 e hc 0.05 n aal 0.10 v A 1 0.1 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current Vs.Pulsewidth 100 Notes on Repetitive Avalanche Curves , Figures 15, 16: TOP Single Pulse (For further info, see AN-1005 at www.irf.com) 90 BOTTOM 10% Duty Cycle 1. Avalanche failures assumption: J) 80 ID = 20A Purely a thermal phenomenon and failure occurs at a m temperature far in excess of T . This is validated for jmax y( 70 every part type. g er 2. Safe operation in Avalanche is allowed as long asTjmax is En 60 not exceeded. e 3. Equation below based on circuit and waveforms shown in h 50 c Figures 12a, 12b. n aal 40 4. PD (ave) = Average power dissipation per single v avalanche pulse. A , R 30 5 . BvoVlt a=g Rea intecdre barseea kdduoriwnng vaovlatalagnec h(1e.)3. factor accounts for A E 20 6. I = Allowable avalanche current. av 10 7. ∆T = Allowable rise in junction temperature, not to exceed T (assumed as 25°C in Figure 15, 16). jmax 0 t Average time in avalanche. av = 25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f Z (D, t ) = Transient thermal resistance, see figure 11) Starting TJ , Junction Temperature (°C) thJC av P = 1/2 ( 1.3·BV·I ) =(cid:1)(cid:1)T/ Z D (ave) av thJC Fig 16. Maximum Avalanche Energy I =2(cid:1)T/ [1.3·BV·Z ] av th Vs. Temperature E = P ·t AS (AR) D (ave) av www.irf.com 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) Driver Gate Drive (cid:2)(cid:3)(cid:4)(cid:3)(cid:5) P.W. Period D = + P.W. Period (cid:24) (cid:1) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:5)(cid:6)(cid:7)(cid:1)(cid:11)(cid:12)(cid:13)(cid:2)(cid:14)(cid:15)(cid:3)(cid:9)(cid:6)(cid:2)(cid:11)(cid:12)(cid:13) VGS=10V • (cid:7)(cid:8)(cid:11)(cid:16)(cid:7)(cid:17)(cid:6)(cid:3)(cid:9)(cid:10)(cid:7)(cid:18)(cid:12)(cid:14)(cid:5)(cid:4)(cid:6)(cid:9)(cid:12)(cid:4)(cid:15) (cid:7)(cid:7) • (cid:19)(cid:3)(cid:11)(cid:5)(cid:12)(cid:14)(cid:7)(cid:20)(cid:21)(cid:9)(cid:12)(cid:15) - (cid:7)(cid:7) • (cid:8)(cid:11)(cid:16)(cid:7)(cid:8)(cid:15)(cid:9)(cid:22)(cid:9)(cid:23)(cid:15)(cid:7)(cid:18)(cid:12)(cid:14)(cid:5)(cid:4)(cid:6)(cid:9)(cid:12)(cid:4)(cid:15) (cid:7)(cid:7)(cid:7)(cid:7)(cid:7)(cid:7)(cid:1)(cid:5)(cid:3)(cid:3)(cid:15)(cid:12)(cid:6)(cid:7)(cid:24)(cid:3)(cid:9)(cid:12)(cid:13)(cid:25)(cid:11)(cid:3)(cid:26)(cid:15)(cid:3) D.U.T. ISDWaveform + (cid:3) Reverse (cid:2) Recovery Body Diode Forward - - + Current Currentdi/dt D.U.T. VDSWaveform Diode Recovery (cid:4) dv/dt VDD (cid:8) (cid:23)(cid:19) • (cid:14)(cid:28)(cid:29)(cid:14)(cid:6)(cid:7)(cid:4)(cid:11)(cid:12)(cid:6)(cid:3)(cid:11)(cid:21)(cid:21)(cid:15)(cid:14)(cid:7)(cid:30)(cid:10)(cid:7)(cid:31)(cid:1) (cid:27)(cid:27) Re-Applied • (cid:27)(cid:3)(cid:2)(cid:28)(cid:15)(cid:3)(cid:7)(cid:13)(cid:9)(cid:26)(cid:15)(cid:7)(cid:6)(cid:10) (cid:15)(cid:7)(cid:9)(cid:13)(cid:7)(cid:27)!"!(cid:24)! + Voltage Body Diode Forward Drop • (cid:18)(cid:2)(cid:3)(cid:7)(cid:4)(cid:11)(cid:12)(cid:6)(cid:3)(cid:11)(cid:21)(cid:21)(cid:15)(cid:14)(cid:7)(cid:30)(cid:10)(cid:7)(cid:27)(cid:5)(cid:6)(cid:10)(cid:7)#(cid:9)(cid:4)(cid:6)(cid:11)(cid:3)(cid:7)$(cid:27)$ - Inductor Curent • (cid:27)!"!(cid:24)!(cid:7)%(cid:7)(cid:27)(cid:15)(cid:28)(cid:2)(cid:4)(cid:15)(cid:7)"(cid:12)(cid:14)(cid:15)(cid:3)(cid:7)(cid:24)(cid:15)(cid:13)(cid:6) Ripple ≤ 5% ISD (cid:24)(cid:7)(cid:8) (cid:7)(cid:9)(cid:7)(cid:10)(cid:8)(cid:7)(cid:11)(cid:12)(cid:13)(cid:7)(cid:14)(cid:12)(cid:15)(cid:16)(cid:17)(cid:7)(cid:14)(cid:18)(cid:19)(cid:18)(cid:20)(cid:7)(cid:21)(cid:18)(cid:19)(cid:16)(cid:17)(cid:18)(cid:22) (cid:19)(cid:17) Fig 17. (cid:5)(cid:6)(cid:7)(cid:8)(cid:3)(cid:9)(cid:10)(cid:11)(cid:12)(cid:6)(cid:3)(cid:13)(cid:6)(cid:14)(cid:11)(cid:15)(cid:6)(cid:16)(cid:17)(cid:3)(cid:12)(cid:15)(cid:18)(cid:12)(cid:19)(cid:3)(cid:20)(cid:6)(cid:21)(cid:19)(cid:3)(cid:22)(cid:10)(cid:16)(cid:14)(cid:23)(cid:10)(cid:19)(cid:3)for N-Channel HEXFET(cid:1)(cid:3)Power MOSFETs (cid:23) (cid:27) (cid:8) (cid:27)(cid:17) (cid:8) (cid:19)(cid:17) (cid:21)(cid:24)(cid:25)(cid:24)(cid:26)(cid:24) (cid:23) (cid:19) +(cid:8) - (cid:27)(cid:27) (cid:6)(cid:1)(cid:8) (cid:20)(cid:5)(cid:21)(cid:13)(cid:15)(cid:7)&(cid:2)(cid:14)(cid:6)’(cid:7)≤ 1 ((cid:13) (cid:27)(cid:5)(cid:6)(cid:10)(cid:7)#(cid:9)(cid:4)(cid:6)(cid:11)(cid:3)(cid:7)≤ 0.1 % Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr td(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:22)(cid:14)(cid:10)(cid:17)(cid:23)(cid:8)(cid:2)(cid:24)(cid:12)(cid:25)(cid:15)(cid:16)(cid:23) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:2)(cid:7)(cid:5)(cid:6)(cid:8)(cid:9)(cid:10)(cid:4)(cid:8)(cid:6)(cid:11)(cid:7)(cid:12)(cid:5)(cid:8)(cid:2)(cid:5)(cid:8)(cid:3)(cid:2)(cid:13)(cid:13)(cid:2)(cid:3)(cid:4)(cid:14)(cid:4)(cid:10)(cid:6)(cid:8)(cid:15)(cid:2)(cid:5)(cid:16)(cid:11)(cid:4)(cid:6)(cid:17) (cid:1)(cid:2)(cid:3)(cid:4)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:8)(cid:13)(cid:10)(cid:11)(cid:14)(cid:15)(cid:16)(cid:17)(cid:8)(cid:18)(cid:16)(cid:19)(cid:20)(cid:11)(cid:21)(cid:10)(cid:12)(cid:15)(cid:20)(cid:16) EXAMPLE: THIS IS AN IRF1010 LOT CODE 1789 INTERNATIONAL PART NUMBER ASSEMBLED ON WW 19, 2000 RECTIFIER IN THE ASSEMBLY LINE "C" LOGO DATE CODE YEAR 0 = 2000 Note: "P" in assembly line position ASSEMBLY indicates "Lead - Free" LOT CODE WEEK 19 LINE C TO-220AB package is not recommended for Surface Mount Application Notes: 1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) (cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:5)(cid:2)(cid:3)(cid:26)(cid:4)(cid:3)(cid:21)(cid:27)(cid:5)(cid:8)(cid:28)(cid:17)(cid:29)(cid:19)(cid:20)(cid:27) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:2)(cid:7)(cid:5)(cid:6)(cid:8)(cid:9)(cid:10)(cid:4)(cid:8)(cid:6)(cid:11)(cid:7)(cid:12)(cid:5)(cid:8)(cid:2)(cid:5)(cid:8)(cid:3)(cid:2)(cid:13)(cid:13)(cid:2)(cid:3)(cid:4)(cid:14)(cid:4)(cid:10)(cid:6)(cid:8)(cid:15)(cid:2)(cid:5)(cid:16)(cid:11)(cid:4)(cid:6)(cid:17) (cid:1)(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:5)(cid:2)(cid:3)(cid:16)(cid:17)(cid:5)(cid:18)(cid:3)(cid:16)(cid:4)(cid:19)(cid:20)(cid:21)(cid:5)(cid:22)(cid:20)(cid:23)(cid:24)(cid:16)(cid:25)(cid:3)(cid:17)(cid:19)(cid:24)(cid:20) TLHOITS CISO ADNE I8R0F25430S WITH INTERNATIONAL PART NUMBER ASSEMBLED ON WW 02, 2000 RECTIFIER F530S IN THE ASSEMBLY LINE "L" LOGO DATE CODE ASSEMBLY YEAR 0 = 2000 LOT CODE WEEK 02 LINE L OR PART NUMBER INTERNATIONAL RECTIFIER F530S LOGO DATE CODE P = DESIGNATES LEAD - FREE PRODUCT (OPTIONAL) ASSEMBLY YEAR 0 = 2000 LOT CODE WEEK 02 A = ASSEMBLY SITE CODE Notes: 1.For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2.For the most current drawing please refer to IR website at http://www.irf.com/package/ 10 www.irf.com

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) TO-262 Package Outline Dimensions are shown in millimeters (inches) EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 PART NUMBER ASSEMBLED ON WW 19, 1997 INTREERCNTAIFTIIEORNAL IN THE ASSEMBLY LINE "C" LOGO Note: "P" in assembly line DATE CODE position indicates "Lead-Free" ASSEMBLY YEAR 7 = 1997 LOT CODE WEEK 19 LINE C OR PART NUMBER INTERNATIONAL RECTIFIER LOGO DATE CODE P = DESIGNATES LEAD-FREE ASSEMBLY PRODUCT (OPTIONAL) LOT CODE YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE Notes: 1.For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2.For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:8)(cid:10)(cid:11)(cid:12)(cid:3) D2Pak Tape & Reel Infomation TRR 1.60 (.063) 1.50 (.059) 43..1900 ((..116513)) 11..6500 ((..006539)) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION 1.85 (.073) 11.60 (.457) 1.65 (.065) 11.40 (.449) 1155..4222 ((..660091)) 2243..3900 ((..995471)) TRL 1.75 (.069) 10.90 (.429) 1.25 (.049) 10.70 (.421) 4.72 (.136) 16.10 (.634) 4.52 (.178) 15.90 (.626) FEED DIRECTION 13.50 (.532) 27.40 (1.079) 12.80 (.504) 23.90 (.941) 4 330.00 60.00 (2.362) (14.173) MIN. MAX. 30.40 (1.197) NOTES : MAX. 1. COMFORMS TO EIA-418. 26.40 (1.039) 4 2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961) 34.. DINIMCLEUNDSEIOSN F LMAENAGSEU RDEISDT @OR HTUIOBN. @ OUTER EDGE. 3 (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11) (cid:4)(cid:7)Repetitive rating; pulse width limited by (cid:5)(cid:1)Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive max. junction temperature. (See fig. 11). avalanche performance. (cid:3) (cid:7)Limited by TJmax, starting TJ = 25°C, L = 0.46mH(cid:6)(cid:1)This value determined from sample failure population. 100% RG = 25Ω, IAS = 20A, VGS =10V. Part not tested to this value in production. recommended for use above this value. (cid:7) This is only applied to TO-220AB pakcage. (cid:1) Pulse width ≤ 1.0ms; duty cycle ≤ 2%. (cid:8) This is applied to D2Pak, when mounted on 1" square PCB (FR- (cid:2) Coss eff. is a fixed capacitance that gives the 4 or G-10 Material). For recommended footprint and soldering same charging time as Coss while VDS is rising techniques refer to application note #AN-994. from 0 to 80% VDSS . TO-220AB package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 07/2010 12 www.irf.com

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