IRF530S, SiHF530S Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21 V (V) 100 Definition DS • Surface Mount RDS(on) () VGS = 10 V 0.16 • Available in Tape and Reel Qg (Max.) (nC) 26 • Dynamic dV/dt Rating Q (nC) 5.5 • Repetitive Avalanche Rated gs Q (nC) 11 • 175 °C Operating Temperature gd • Fast Switching Configuration Single • Ease of Paralleling • Compliant to RoHS Directive 2002/95/EC D DESCRIPTION D2PAK (TO-263) Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. G The D2PAK (TO-263) is a surface mount power package capable of accommodating die size up to HEX-4. It provides G D the highest power capability and the lowest possible on-resistance in any existing surface mount package. The S S D2PAK (TO-263) is suitable for high current applications N-Channel MOSFET because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHF530S-GE3 SiHF530STRL-GE3a SiHF530STRR-GE3a IRF530SPbF IRF530STRLPbFa IRF530STRRPbFa Lead (Pb)-free SiHF530S-E3 SiHF530STL-E3a SiHF530STR-E3a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted C PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 100 DS V Gate-Source Voltage V ± 20 GS T = 25 °C 14 Continuous Drain Current V at 10 V C I GS T = 100 °C D 10 A C Pulsed Drain Currenta I 56 DM Linear Derating Factor 0.59 W/°C Linear Derating Factor (PCB Mount)e 0.025 Single Pulse Avalanche Energyb E 69 mJ AS Avalanche Currenta I 14 A AR Repetitive Avalanche Energya E 8.8 mJ AR Maximum Power Dissipation T = 25 °C 88 C P W Maximum Power Dissipation (PCB Mount)e T = 25 °C D 3.7 A Peak Diode Recovery dV/dtc dV/dt 5.5 V/ns Operating Junction and Storage Temperature Range T , T - 55 to + 175 J stg °C Soldering Recommendations (Peak Temperature) for 10 s 300d Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 528 μH, Rg = 25 , IAS = 14 A (see fig. 12). c. ISD  14 A, dI/dt  140 A/μs, VDD  VDS, TJ  175 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91020 www.vishay.com S11-1046-Rev. C, 30-May-11 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum Junction-to-Ambient R - 62 thJA Maximum Junction-to-Ambient R - 40 °C/W (PCB Mount)a thJA Maximum Junction-to-Case (Drain) R - 1.7 thJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS T = 25 °C, unless otherwise noted J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V V = 0, I = 250 μA 100 - - V DS GS D VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.12 - V/°C Gate-Source Threshold Voltage V V = V , I = 250 μA 2.0 - 4.0 V GS(th) DS GS D Gate-Source Leakage I V = ± 20 V - - ± 100 nA GSS GS V = 100 V, V = 0 V - - 25 DS GS Zero Gate Voltage Drain Current I μA DSS V = 80 V, V = 0 V, T = 150 °C - - 250 DS GS J Drain-Source On-State Resistance RDS(on) VGS = 10 V ID = 8.4 Ab - - 0.16  Forward Transconductance g V = 50 V, I = 8.4 Ab 5.1 - - S fs DS D Dynamic Input Capacitance C - 670 - iss V = 0 V, GS Output Capacitance C V = 25 V, - 250 - pF oss DS f = 1.0 MHz, see fig. 5 Reverse Transfer Capacitance C - 60 - rss Total Gate Charge Q - - 26 g I = 14 A, V = 80 V, Gate-Source Charge Q V = 10 V D DS - - 5.5 nC gs GS see fig. 6 and 13b Gate-Drain Charge Q - - 11 gd Turn-On Delay Time t - 10 - d(on) Rise Time tr VDD = 50 V, ID = 14 A, - 34 - ns Turn-Off Delay Time td(off) Rg = 12 , RD = 3.6 , see fig. 10b - 23 - Fall Time t - 24 - f Internal Drain Inductance L Between lead, D - 4.5 - D 6 mm (0.25") from package and center of nH G Internal Source Inductance LS die contact - 7.5 - S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I MOSFET symbol D - - 14 S showing the A integral reverse G Pulsed Diode Forward Currenta ISM p - n junction diode S - - 56 Body Diode Voltage V T = 25 °C, I = 14 A, V = 0 Vb - - 2.5 V SD J S GS Body Diode Reverse Recovery Time t - 150 280 ns rr T = 25 °C, I = 14 A, dI/dt = 100 A/μsb J F Body Diode Reverse Recovery Charge Q - 0.85 1.7 μC rr Forward Turn-On Time t Intrinsic turn-on time is negligible (turn-on is dominated by L and L ) on S D Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. www.vishay.com Document Number: 91020 2 S11-1046-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted V GS Top 15 V 10 V 25 °C 8.0 V Current (A) 101 Bottom76554.....00505 VVVVV Current (A) 101 175 °C Drain Drain 100 I, D 100 4.5 V I, D 20 µs Pulse Width 20 µs Pulse Width TC = 25 °C VDS = 50 V 10-1 100 101 4 5 6 7 8 9 10 91020_01 VDS, Drain-to-Source Voltage (V) 91020_03 VGS, Gate-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics, T = 25 °C Fig. 3 - Typical Transfer Characteristics C V e 3.5 Top 1150G VVS stanc 3.0 IVDG =S 1=4 1 A0 V A) 87..00 VV Resi urrent ( 101 655...050 VVV ce On zed) 22..05 C Bottom 4.5 V urali I, Drain D 100 4.5 V Drain-to-So(Norm 11..05 20 µs Pulse Width , n) 0.5 o TC = 175 °C DS( 10-1 100 101 R 0.0 - 60- 40- 20 0 20 40 60 80 100120140160180 91020_02 VDS, Drain-to-Source Voltage (V) 91020_04 TJ, Junction Temperature (°C) Fig. 2 - Typical Output Characteristics, T = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature C Document Number: 91020 www.vishay.com S11-1046-Rev. C, 30-May-11 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix 1400 VGS = 0 V, f = 1 MHz 1200 Ciss = Cgs + Cgd, Cds Shorted A) pF) 1000 CCrossss == CCgdds + Cgd Current ( 101 175 °C ance ( 800 Ciss Drain 25 °C cit 600 e Capa 400 Coss evers R 200 Crss I, SD 100 V = 0 V GS 0 100 101 0.4 0.8 1.2 1.6 2.0 91020_05 VDS, Drain-to-Source Voltage (V) 91020_07 VSD, Source-to-Drain Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage 20 I = 14 A 103 D ge (V) 16 VDS = 80 V 25 Operationb iyn RthDiSs( oanr)ea limited urce Volta 12 VDS = 20 VVDS = 50 V urrent (A) 10225 11000 µ µss o C 10 1 ms Gate-to-S 8 , Drain D 125 10 ms , S 4 I 5 T = 25 °C VG For test circuit TC = 175 °C 0 see figure 13 0.12 SJingle Pulse 0 5 10 15 20 25 0.1 2 5 1 2 5 10 2 5 102 2 5 103 91020_06 QG, Total Gate Charge (nC) 91020_08 VDS, Drain-to-Source Voltage (V) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com Document Number: 91020 4 S11-1046-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix R D V DS 14 V GS 12 D.U.T. R g + A) 10 -VDD nt ( e 10 V urr 8 Pulse width ≤ 1 µs C Duty factor ≤ 0.1 % n 6 ai , DrD 4 Fig. 10a - Switching Time Test Circuit I 2 V 0 DS 25 50 75 100 125 150 175 90 % 91020_09 TC, Case Temperature (°C) 10 % Fig. 9 - Maximum Drain Current vs. Case Temperature V GS t t t t d(on) r d(off) f Fig. 10b - Switching Time Waveforms 10 )C hJ Zt e ( 1 0 - 0.5 s n o sp 0.2 PDM e R 0.1 mal 0.1 0.05 t1 er 0.02 Single Pulse t2 h T 0.01 (Thermal Response) Notes: 1. Duty Factor, D = t/t 1 2 2. Peak T = P x Z + T j DM thJC C 10-2 10-5 10-4 10-3 10-2 0.1 1 10 91020_11 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case Document Number: 91020 www.vishay.com S11-1046-Rev. C, 30-May-11 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix L VDS VDS Vary t to obtain p t required I p AS V DD Rg D.U.T + V - DD V I DS AS 10 V t 0.01 Ω p I AS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms 200 I D J) Top 5.7 A m 160 9.9 A y ( Bottom 14 A g er En 120 e s ul P e 80 gl n Si , S 40 A E V = 25 V DD 0 25 50 75 100 125 150 175 91020_12c Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. Q 50 kΩ G VGS 12 V 0.2 µF 0.3 µF QGS QGD + V D.U.T. - DS V G V GS 3 mA Charge I I G D Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com Document Number: 91020 6 S11-1046-Rev. C, 30-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRF530S, SiHF530S Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. (cid:129) Low stray inductance (cid:129) Ground plane (cid:129) Low leakage inductance current transformer - + - + - Rg (cid:129) dV/dt controlled by Rg + (cid:129) Driver same type as D.U.T. V - DD (cid:129) ISD controlled by duty factor “D” (cid:129) D.U.T. - device under test Driver gate drive Period D = P.W. P.W. Period V = 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt V DD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. V = 5 V for logic level devices GS Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91020. Document Number: 91020 www.vishay.com S11-1046-Rev. C, 30-May-11 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 4 A A B E c2 H 4 L1 4 Gauge plane 0° to 8° B D 5 Detail A Seating plane H 1 2C 3 C L3 L L4 A1 Detail “A” L2 Rotated 90° CW BB BB scale 8:1 A 2 x b2 2 x b c E 0.010M AM B ± 0.004M B 2 x e Base Plating 5 metal D1 4 b1, b3 (c) c1 5 (b, b2) Lead tip Section B - B and C - C E1 4 Scale: none View A - A MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 - b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 www.vishay.com Revision: 15-Sep-08 1

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