Data Sheet No. PD60174 revG IR2184(4)(S) & (PbF) HALF-BRIDGE DRIVER Features • Packages Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dV/dt immune 14-Lead PDIP • Gate drive supply range from 10 to 20V IR21844 • Undervoltage lockout for both channels 8-Lead PDIP • 3.3V and 5V input logic compatible IR2184 • Matched propagation delay for both channels • Logic and power ground +/- 5V offset. • Lower di/dt gate driver for better noise immunity • Output source/sink current capability 1.4A/1.8A • 8-Lead SOIC 14-Lead SOIC Also available LEAD-FREE (PbF) IR2184S IR21844S Description IR2181/IR2183/IR2184 Feature Comparison The IR2184(4)(S) are high voltage, high speed power MOSFET and IGBT (cid:2)(cid:24)(cid:16)(cid:30)(cid:30)(cid:31) (cid:9)(cid:25)(cid:13)(cid:12)(cid:15)(cid:14) (cid:29)(cid:16)(cid:25)!(cid:12)(cid:29)(cid:15)(cid:28)(cid:16)(cid:25)(cid:14)(cid:14) drivers with dependent high and low (cid:22)(cid:23)(cid:24)(cid:15)(cid:14) (cid:26)(cid:16)(cid:27)(cid:28)(cid:29)(cid:14) (cid:13)(cid:24)"#"(cid:25)(cid:15)(cid:28)(cid:16)(cid:25)(cid:14) (cid:11)"(cid:23)!(cid:31)(cid:19)(cid:28)$"(cid:14) %(cid:24)(cid:16)(cid:12)(cid:25)!(cid:14)(cid:22)(cid:28)(cid:25)(cid:30)(cid:14) (cid:19)(cid:16)(cid:25)&(cid:19)(cid:16)’’(cid:14) side referenced output channels. Pro- (cid:26)(cid:16)(cid:27)(cid:28)(cid:29)(cid:14) *797(cid:14) (cid:2)(cid:6)(cid:8)(cid:14) prietary HVIC and latch immune (cid:5)(cid:9)(cid:10)&(cid:7)(cid:9)(cid:10)(cid:14) (cid:25)(cid:16)(cid:14) (cid:25)(cid:16)(cid:25)"(cid:14) 79(cid:18)&**(cid:18)(cid:14)(cid:25)(cid:30)(cid:14) *797:(cid:14) (cid:1)(cid:4)(cid:4)&(cid:2)(cid:6)(cid:8)(cid:14) CMOS technologies enable rugge- *79;(cid:14) (cid:9)(cid:25)(cid:15)"(cid:24)(cid:25)(cid:23)(cid:26)(cid:14)<(cid:18)(cid:18)(cid:25)(cid:30)(cid:14) (cid:2)(cid:6)(cid:8)(cid:14) (cid:5)(cid:9)(cid:10)&(cid:7)(cid:9)(cid:10)(cid:14) ="(cid:30)(cid:14) 79(cid:18)&**(cid:18)(cid:14)(cid:25)(cid:30)(cid:14) dized monolithic construction. The *79;:(cid:14) (cid:22)(cid:24)(cid:16)(cid:27)(cid:24)(cid:23)$(cid:14)(cid:18)>:(cid:14)?(cid:14)<(cid:14)(cid:12)(cid:30)(cid:14) (cid:1)(cid:4)(cid:4)&(cid:2)(cid:6)(cid:8)(cid:14) logic input is compatible with standard *79:(cid:14) (cid:9)(cid:10)&(cid:4)(cid:11)(cid:14) ="(cid:30)(cid:14) (cid:9)(cid:25)(cid:15)"(cid:24)(cid:25)(cid:23)(cid:26)(cid:14)<(cid:18)(cid:18)(cid:25)(cid:30)(cid:14) (cid:2)(cid:6)(cid:8)(cid:14) (cid:17)9(cid:18)&*@(cid:18)(cid:14)(cid:25)(cid:30)(cid:14) *79::(cid:14) (cid:22)(cid:24)(cid:16)(cid:27)(cid:24)(cid:23)$(cid:14)(cid:18)>:(cid:14)?(cid:14)<(cid:14)(cid:12)(cid:30)(cid:14) (cid:1)(cid:4)(cid:4)&(cid:2)(cid:6)(cid:8)(cid:14) CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:14)(cid:17)(cid:18)(cid:18)(cid:1) (cid:1)(cid:2)(cid:2) (cid:1) (cid:1) (cid:2)(cid:2) (cid:3) (cid:9)(cid:10) (cid:9)(cid:10) (cid:5)(cid:6) (cid:4)(cid:11) (cid:4)(cid:11) (cid:1)(cid:4) (cid:7)(cid:6)(cid:19)(cid:6)(cid:20)(cid:11) (cid:2)(cid:6)(cid:8) (cid:7)(cid:6) (cid:12)(cid:13)(cid:14)(cid:15)(cid:16)(cid:14)(cid:17)(cid:18)(cid:18)(cid:1) IR2184 (cid:5)(cid:6) IR21844 (cid:1)(cid:2)(cid:2) (cid:1)(cid:2)(cid:2) (cid:1)(cid:3) (cid:9)(cid:10) (cid:9)(cid:10) (cid:1)(cid:4) (cid:19)(cid:6) (cid:4)(cid:11) (cid:4)(cid:11) (cid:7)(cid:6)(cid:20)(cid:11) (Refer to Lead Assignments for correct (cid:11)(cid:19) configuration). This/These diagram(s) show (cid:1)(cid:4)(cid:4) (cid:21) (cid:1)(cid:4)(cid:4) (cid:2)(cid:6)(cid:8) electrical connections only. Please refer to (cid:11)(cid:19) (cid:7)(cid:6) our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1

IR2184(4)(S) & (PbF) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units VB High side floating absolute voltage -0.3 625 VS High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 25 V VLO Low side output voltage -0.3 VCC + 0.3 DT Programmable dead-time pin voltage (IR21844 only) VSS - 0.3 VCC + 0.3 VIN Logic input voltage (IN & SD) VSS - 0.3 VSS + 10 VSS Logic ground (IR21844 only) VCC - 25 VCC + 0.3 dVS/dt Allowable offset supply voltage transient — 50 V/ns PD Package power dissipation @ TA ≤ +25°C (8-lead PDIP) — 1.0 (8-lead SOIC) — 0.625 W (14-lead PDIP) — 1.6 (14-lead SOIC) — 1.0 RthJA Thermal resistance, junction to ambient (8-lead PDIP) — 125 (8-lead SOIC) — 200 °C/W (14-lead PDIP) — 75 (14-lead SOIC) — 120 TJ Junction temperature — 150 TS Storage temperature -50 150 °C TL Lead temperature (soldering, 10 seconds) — 300 Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential. Symbol Definition Min. Max. Units VB High side floating supply absolute voltage VS + 10 VS + 20 VS High side floating supply offset voltage Note 1 600 VHO High side floating output voltage VS VB VCC Low side and logic fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC VIN Logic input voltage (IN & SD) VSS VSS + 5 DT Programmable dead-time pin voltage (IR21844 only) VSS VCC VSS Logic ground (IR21844 only) -5 5 TA Ambient temperature -40 125 °C Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: IN and SD are internally clamped with a 5.2V zener diode. 2 www.irf.com

IR2184(4)(S) & (PbF) Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay — 680 900 VS = 0V toff Turn-off propagation delay — 270 400 VS = 0V or 600V tsd Shut-down propagation delay — 180 270 MTon Delay matching, HS & LS turn-on — 0 90 nsec MToff Delay matching, HS & LS turn-off — 0 40 tr Turn-on rise time — 40 60 VS = 0V tf Turn-off fall time — 20 35 VS = 0V DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0 HO turn-off to LO turn-on (DTHO-LO) 4 5 6 µsec RDT = 200k MDT Deadtime matching = DTLO - HO - DTHO-LO — 0 50 RDT=0 nsec — 0 600 RDT = 200k Static Electrical Characteristics VBIAS (VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VSS /COM and are applicable to the respective input leads: IN and SD. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “1” input voltage for HO & logic “0” for LO 2.7 — — VCC = 10V to 20V VIL Logic “0” input voltage for HO & logic “1” for LO — — 0.8 VCC = 10V to 20V VSD,TH+ SD input positive going threshold 2.7 — — VCC = 10V to 20V V VSD,TH- SD input negative going threshold — — 0.8 VCC = 10V to 20V VOH High level output voltage, VBIAS - VO — — 1.2 IO = 0A VOL Low level output voltage, VO — — 0.1 IO = 0A ILK Offset supply leakage current — — 50 VB = VS = 600V µA IQBS Quiescent VBS supply current 20 60 150 VIN = 0V or 5V IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V IIN+ Logic “1” input bias current — 25 60 IN = 5V, SD = 0V µA IIN- Logic “0” input bias current — — 1.0 IN = 0V, SD = 5V VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8 VBSUV+ threshold VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9.0 VBSUV- threshold V VCCUVH Hysteresis 0.3 0.7 — VBSUVH IO+ Output high short circuit pulsed current 1.4 1.9 — VO = 0V, PW ≤ 10 µs A IO- Output low short circuit pulsed current 1.8 2.3 — VO = 15V, PW ≤ 10 µs www.irf.com 3

IR2184(4)(S) & (PbF) Functional Block Diagrams VB 2184 UV DETECT R HO HV PULSE R Q LEVEL FILTER S IN VSS/COM SHIFTER VS LEVEL PULSE SHIFT GENERATOR DEADTIME VCC UV +5V DETECT LO VSS/COM SD LEVEL DELAY SHIFT COM VB 21844 UV DETECT R HO LEHVVEL FPIULTLSEER RS Q IN VSS/COM SHIFTER VS LEVEL PULSE SHIFT GENERATOR DT DEADTIME VCC UV +5V DETECT LO VSS/COM SD LEVEL DELAY SHIFT COM VSS 4 www.irf.com

IR2184(4)(S) & (PbF) Lead Definitions Symbol Description IN Logic input for high and low side gate driver outputs (HO and LO), in phase with HO (referenced to COM for IR2184 and VSS for IR21844) SD Logic input for shutdown (referenced to COM for IR2184 and VSS for IR21844) DT Programmable dead-time lead, referenced to VSS. (IR21844 only) VSS Logic Ground (21844 only) VB High side floating supply HO High side gate drive output VS High side floating supply return VCC Low side and logic fixed supply LO Low side gate drive output COM Low side return Lead Assignments 1 IN VB 8 1 IN VB 8 2 SD HO 7 2 SD HO 7 3 COM VS 6 3 COM VS 6 4 LO VCC 5 4 LO VCC 5 8-Lead PDIP 8-Lead SOIC IR2184 IR2184S 1 IN 14 1 IN 14 2 SD VB 13 2 SD VB 13 3 VSS HO 12 3 VSS HO 12 4 DT VS 11 4 DT VS 11 5 COM 10 5 COM 10 6 LO 9 6 LO 9 7 VCC 8 7 VCC 8 14-Lead PDIP 14-Lead SOIC IR21844 IR21844S www.irf.com 5

IR2184(4)(S) & (PbF) (cid:9)(cid:10) (cid:9)(cid:10)^(cid:7)(cid:6)_ <(cid:18)‘ <(cid:18)‘ (cid:4)(cid:11) (cid:9)(cid:10)^(cid:5)(cid:6)_ (cid:15)(cid:16)(cid:25) (cid:15)(cid:24) (cid:15)(cid:16)’’ (cid:15)’ (cid:5)(cid:6) q(cid:18)‘ q(cid:18)‘ (cid:7)(cid:6) (cid:7)(cid:6) (cid:5)(cid:6) 7(cid:18)‘ 7(cid:18)‘ Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions (cid:4)(cid:11) <(cid:18)‘ <(cid:18)‘ <(cid:18)‘ (cid:15)(cid:30)! (cid:9)(cid:10) (cid:5)(cid:6) q(cid:18)‘ (cid:7)(cid:6) q(cid:18)‘ (cid:5)(cid:6) (cid:11)(cid:19)(cid:7)(cid:6)(cid:31)(cid:5)(cid:6) 7(cid:18)‘ Figure 3. Shutdown Waveform Definitions (cid:7)(cid:6) q(cid:18)‘ (cid:11)(cid:19)(cid:5)(cid:6)(cid:31)(cid:7)(cid:6) 7(cid:18)‘ (cid:8)(cid:11)(cid:19){ (cid:11)(cid:19)(cid:7)(cid:6)(cid:31)(cid:5)(cid:6) (cid:31)(cid:14)(cid:14)(cid:11)(cid:19)(cid:5)(cid:6)(cid:31)(cid:7)(cid:6) (cid:9)(cid:10)^(cid:7)(cid:6)_ <(cid:18)‘ <(cid:18)‘ Figure 4. Deadtime Waveform Definitions (cid:9)(cid:10)^(cid:5)(cid:6)_ (cid:7)(cid:6) (cid:5)(cid:6) 7(cid:18)‘ (cid:8)(cid:19) (cid:8)(cid:19) q(cid:18)‘ (cid:7)(cid:6) (cid:5)(cid:6) Figure 5. Delay Matching Waveform Definitions 6 www.irf.com

IR2184(4)(S) & (PbF) 1400 1400 ns) ns) Delay ( 1200 Delay ( 1200 Max. opagation 1080000 Max. opagation 1080000 Typ. Pr Typ. Pr on 600 on 600 n- n- Tur 400 Tur 400 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 4A. Turn-on Propagation Delay Figure4B. Turn-on Propagation Delay vs. Temperature vs. Supply Voltage 700 700 ay (ns) 600 y (ns) 600 on Del 500 n Dela 500 Max. gati 400 atio 400 a Max. g Turn-off Prop 123000000 Typ. urn-off Propa 230000 Typ. T 100 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 5A. Turn-off Propagation Delay Figure 5B. Turn-off Propagation Delay vs. Temperature vs. Supply Voltage www.irf.com 7

IR2184(4)(S) & (PbF) 500 500 ns) 400 ns) 400 Delay ( 300 Delay ( 300 Max. opagation 200 TMyapx.. opagation 200 Typ. Pr 100 Pr 100 D D S S 0 0 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 6A. SD Propagation Delay Figure 6B. SD Propagation Delay vs. Temperature vs. Supply Voltage 120 120 ns) 100 ns) 100 me ( 80 me ( 80 Max. Ti Ti Rise 60 Rise 60 Typ. on 40 Max. on 40 Turn- 20 Typ. Turn- 20 0 0 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 7A. Turn-on Rise Time vs. Temperature Figure 7B. Turn-on Rise Time vs. Supply Voltage 8 www.irf.com

IR2184(4)(S) & (PbF) 80 80 s) 60 s) 60 n n e ( e ( m m Max. Ti Ti all 40 all 40 off F Max. off F Typ. n- 20 Typ n- 20 ur ur T T 0 0 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 8A. Turn-off Fall Time vs. Temperature Figure 8B. Turn-off Fall Time vs. Supply Voltage 1100 1100 900 900 me (ns) 700 Max. me (ns) 700 Max. dti 500 dui 500 Typ. a Typ. a e e D D Min. Min. 300 300 100 100 -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (v) Figure 9A. Deadtime vs. Temperature Figure 9B. Deadtime vs. Supply Voltage www.irf.com 9

IR2184(4)(S) & (PbF) 7 6 6 Max. V) 5 ΗDeadtime (s) 2345 MTyinp.. 1" Input Voltage ( 234 Min. 1 gic " 1 o 0 L 0 0 50 100 150 200 -50 -25 0 25 50 75 100 125 R (KΗ) DT Temperature (oC) Figure 9C. Deadtime vs. R DT Figure 10A. Logic "1" Input Voltage vs. Temperature 6 6 age (V) 45 ge (V) 45 Volt olta put 3 Min. ut V 3 n p ogic "1" I 12 gic "0" In 12 Max. L o L 0 0 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (oC) Figure 10B. Logic "1" Input Voltage Figure 11A. Logic "0" Input Voltage vs. Supply Voltage vs. Temperature 10 www.irf.com

IR2184(4)(S) & (PbF) 6 6 V) oltage (V) 45 hreshold ( 45 V T nput 3 oing 3 Min. 0" I 2 e G 2 ogic " 1 Max. ositiv 1 L P 0 put 0 10 12 14 16 18 20 D In -50 -25 0 25 50 75 100 125 S Supply Voltage (V) Temperature (oC) Figure 11B. Logic "0" Input Voltage Figure 12A. SD Input Positive Going Threshold vs. Supply Voltage vs. Temperature 6 5 V) V) d ( 5 d ( ol ol 4 h h s s e 4 e hr hr 3 T T ng 3 Min. ng Goi Goi 2 e 2 e v v put Positi 01 ut Negati 01 Max. n p SD I 10 12 14 16 18 20 D In -50 -25 0 25 50 75 100 125 S Supply Voltage (V) Temperature (oC) Figure 12B. SD Input Positive Going Threshold Figure 13A. SD Input Negative Going Threshold vs. Supply Voltage vs. Temperature www.irf.com 11

IR2184(4)(S) & (PbF) 5 V) 5 d ( shol 4 V) 4 hre ut ( T 3 p 3 g ut n O egative Goi 12 High Level 12 Max. N Max. put 0 0 n D I 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 S Supply Voltage (V) Temperature (oC) Figure 13B. SD Input Negative Going Threshold Figure 14A. High Level Output vs. Temperature vs. Supply Voltage 0.5 5 0.4 V) 4 V) Output ( 3 Output ( 0.3 h Level 2 Max. w Level 0.2 Max. Hig 1 Lo 0.1 0 0.0 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (oC) Figure 14B. High Level Output vs. Supply Voltage Figure 15A. Low Level Output vs. Temperature 12 www.irf.com

IR2184(4)(S) & (PbF) 0.5 A) 500 Η V) 0.4 ent ( 400 put ( 0.3 Curr 300 ut e O g el 0.2 ka 200 ev ea L L w Max. y o 0.1 pl 100 L p u S Max. 0.0 et 0 s 10 12 14 16 18 20 Off -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (oC) Figure 15B. Low Level Output vs. Supply Voltage Figure 16A. Offset Supply Leakage Current vs. Temperature ΗA) 500 250 nt ( 400 ΗA) 200 e ge Curr 300 urrent ( 150 Max. a C Supply Leak 120000 Max. V Supply BS10500 MTyinp.. set 0 0 Off 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 V Boost Voltage (V) Temperature (oC) B Figure 16B. Offset Supply Leakage Current vs. Figure 17A. V Supply Current BS V Boost Voltage vs. Temperature B www.irf.com 13

IR2184(4)(S) & (PbF) 250 5 ΗA) 200 mA) 4 nt ( nt ( urre 150 Max. urre 3 C C ply 100 Typ. ply 2 Max. p p u u S S Typ. V BS 50 Min. V CC1 Min. 0 0 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 V Floating Supply Voltage (V) Temperature (oC) BS Figure 17B. V Supply Current Figure 18A. V Supply Current BS CC vs. V Floating Supply Voltage vs. Temperature BS 5 A) 120 Η mA) 4 nt ( 100 nt ( urre 80 e 3 C pply Curr 2 TMyapx.. put Bias 4600 Max. u n V SCC1 Min. c "1" I 20 Typ. gi 0 Lo 0 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 V Supply Voltage (V) Temperature (oC) CC Figure 18B. V Supply Current Figure 19A. Logic "1" Input Bias Current CC vs. V Supply Voltage vs. Temperature CC 14 www.irf.com

IR2184(4)(S) & (PbF) A) 120 ΗA) 5 Η nt ( 100 ent ( 4 urre 80 Curr 3 ogic "1" Input Bias C 2460000 MTayxp.. Logic "0" Input Bias 012 Max. L 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (oC) Figure 19B. Logic "1" Input Bias Current Figure 20A. Logic "0" Input Bias Current vs. Supply Voltage vs. Temperature 12 A) 5 V) Η +) (11 0" Input Bias Current ( 1234 Max. d V UV Threshold (BS10789 MTMyianpx... ogic " 0 anCC 6 L V -50 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (oC) Supply Voltage (V) Figure 20B. Logic "0" Input Bias Current Figure 21. V and V Undervoltage Threshold (+) CC BS vs. Supply Voltage vs. Temperature www.irf.com 15

IR2184(4)(S) & (PbF) 12 5 V) old (-) ( 1101 nt (A) 4 h e es Max. urr 3 hr 9 C UVTBS 8 MTyinp.. Source 2 Typ. d V 7 put 1 Min. anCC 6 Out 0 V -50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (oC) Temperature (oC) Figure 22. V and V Undervoltage Threshold (-) CC BS Figure 23A. Output Source Current vs. Temperature vs. Temperature 5 5.0 A) 4 A) nt ( nt ( 4.0 e e urr 3 urr C C 3.0 e k Typ. c n ur 2 Si Output So 1 TMyipn.. Output 2.0 Min. 0 1.0 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 Supply Voltage (V) Temperature (oC) Figure 23B. Output Source Current Figure 24A. Output Sink Current vs. Supply Voltage vs. Temperature 16 www.irf.com

IR2184(4)(S) & (PbF) 5 140 A) 4 120 k Current ( 3 oature (C)10800 140v ut Sin 2 Typ. empr 60 7 00vv p T ut 1 O Min. 40 0 20 10 12 14 16 18 20 1 10 100 1000 Supply Voltage (V) Frequency (KHz) Figure 24B. Output Sink Current Figure 21. IR2181 vs. Frequency (IRFBC20), vs. Supply Voltage R =33Ω, V =15V gate CC 140 140 120 120 omperature (C) 1068000 1 47 000vvv omperature (C)1068000 1 7040v0vv Te Te 40 40 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 22. IR2181 vs. Frequency (IRFBC30), Figure 23. IR2181 vs. Frequency (IRFBC40), R =22Ω, V =15V R =15Ω, V =15V gate CC gate CC www.irf.com 17

IR2184(4)(S) & (PbF) 140 140v 140 70v 120 0v 120 oe (C) 100 oe (C) 100 atur 80 atur 80 mper 60 mper 60 e e 140v T T 70v 40 40 0v 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 24. IR2181 vs. Frequency (IRFPE50), Figure 25. IR21814 vs. Frequency (IRFBC20), R =10Ω, V =15V R =33Ω, V =15V gate CC gate CC 140 140 120 120 omperature (C)1068000 140v omperature (C) 1068000 1 7400vv Te 7 00vv Te 0v 40 40 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 26. IR21814 vs. Frequency (IRFBC30), Figure 27. IR21814 vs. Frequency (IRFBC40), R =22Ω, V =15V R =15Ω, V =15V gate CC gate CC 18 www.irf.com

IR2184(4)(S) & (PbF) 140 140v 140 120 70v 120 oe (C) 100 0v oe (C) 100 mperatur 6800 mperatur 6800 1 4700vv e e 0v T T 40 40 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 28. IR21814 vs. Frequency (IRFPE50), Figure 29. IR2181s vs. Frequency (IRFBC20), R =10Ω, V =15V R =33Ω, V =15V gate CC gate CC 140 140 140v 70v 120 120 oerature (C) 10800 1 7 4 000vvv operature (C) 10800 0v mp 60 em 60 e T T 40 40 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 30. IR2181s vs. Frequency (IRFBC30), Figure 31. IR2181s vs. Frequency (IRFBC40), R =22Ω, V =15V R =15Ω, V =15V gate CC gate CC www.irf.com 19

IR2184(4)(S) & (PbF) 140 140V 70V 0V 140 120 120 C) C) oe ( 100 oe ( 100 Tempretur 6800 Temperatur 6800 1 4700vv 40 40 0v 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 32. IR2181s vs. Frequency (IRFPE50), Figure 33. IR21814s vs. Frequency (IRFBC20), R =10Ω, V =15V R =33Ω, V =15V gate CC gate CC 140 140 120 120 C) C) oe ( 100 oe ( 100 140v ur ur perat 80 1 40v perat 80 7 00vv m 60 70v m 60 e 0v e T T 40 40 20 20 1 10 100 1000 1 10 100 1000 Frequency (KHz) Frequency (KHz) Figure 34. IR21814s vs. Frequency (IRFBC30), Figure 35. IR21814s vs. Frequency (IRFBC40), R =22Ω, V =15V R =15Ω, V =15V gate CC gate CC 20 www.irf.com

IR2184(4)(S) & (PbF) 140 140v 70v 0v 120 C) oe ( 100 ur at 80 er p m 60 e T 40 20 1 10 100 1000 Frequency (KHz) Figure 36. IR21814s vs. Frequency (IRFPE50), R =10Ω, V =15V gate CC www.irf.com 21

IR2184(4)(S) & (PbF) 01-6014 8-Lead PDIP 01-3003 01 (MS-001AB) INCHES MILLIMETERS D B DIM MIN MAX MIN MAX A 5 FOOTPRINT A .0532 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 8X 0.72 [.028] b .013 .020 0.33 0.51 8 7 6 5 c .0075 .0098 0.19 0.25 6 H D .189 .1968 4.80 5.00 E 0.25 [.010] A E .1497 .1574 3.80 4.00 1 2 3 4 6.46 [.255] e .050 BASIC 1.27 BASIC e1 .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 6X e 3X 1.27 [.050] 8X 1.78 [.070] y 0° 8° 0° 8° e1 K x 45° A C y 0.10 [.004] 8X b A1 8X L 8X c 7 0.25 [.010] C A B NOTES: 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. 1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 2. CONTROLLING DIMENSION: MILLIMETER 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. A SUBSTRATE. 01-6027 8-Lead SOIC 01-0021 11 (MS-012AA) 22 www.irf.com

IR2184(4)(S) & (PbF) 01-6010 14-Lead PDIP 01-3002 03 (MS-001AC) 01-6019 14-Lead SOIC (narrow body) 01-3063 00 (MS-012AB) www.irf.com 23

IR2184(4)(S) & (PbF) LEADFREE PART MARKING INFORMATION IRxxxxxx Part number YWW? Date code IR logo ?XXXX Pin 1 Identifier Lot Code ? MARKING CODE (Prod mode - 4 digit SPN code) P Lead Free Released Non-Lead Free Released Assembly site code Per SCOP 200-002 ORDER INFORMATION Basic Part (Non-Lead Free) Leadfree Part 8-Lead PDIP IR2184 order IR2184 8-Lead PDIP IR2184 order IR2184PbF 8-Lead SOIC IR2184S order IR2184S 8-Lead SOIC IR2184S order IR2184SPbF 14-Lead PDIP IR21844 order IR21844 14-Lead PDIP IR21844 order IR21844PbF 14-Lead SOIC IR21844 order IR21844S 14-Lead SOIC IR21844 order IR21844SPbF Thisproduct has been designed and qualified for the industrial market. Qualification Standards can be found on IR’s Web Site http://www.irf.com Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 4/4/2006 24 www.irf.com

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: I nfineon: IR2184PBF IR2184SPBF IR21844PBF IR21844SPBF IR21844STRPBF IR2184STRPBF