DATASHEET ICL7650S FN2920 2MHz, Super Chopper-Stabilized Operational Amplifier Rev 10.00 April 12, 2007 The ICL7650S Super Chopper-Stabilized Amplifier offers Features exceptionally low input offset voltage and is extremely stable • Guaranteed Max Input Offset Voltage for All Temperature with respect to time and temperature. It is a direct Ranges replacement for the industry-standard ICL7650 offering improved input offset voltage, lower input offset voltage • Low Long-Term and Temperature Drifts of Input Offset temperature coefficient, reduced input bias current, and Voltage wider common mode voltage range. All improvements are • Guaranteed Max Input Bias Current . . . . . . . . . . . . .10pA highlighted in bold italics in the Electrical Characteristics section. Critical parameters are guaranteed over the • Extremely Wide Common Mode Voltage Range. . . . . . . . . . . . . . . . . . . . . . . +3.5V to -5V entire commercial temperature range. • Reduced Supply Current . . . . . . . . . . . . . . . . . . . . . . 2mA Intersil’s unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional • Guaranteed Minimum Output Source/Sink Current chopper amplifier problems of intermodulation effects, • Extremely High Gain . . . . . . . . . . . . . . . . . . . . . . . .150dB chopping spikes, and overrange lockup. • Extremely High CMRR and PSRR. . . . . . . . . . . . . .140dB The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in a nulling • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V/s amplifier, nulled by alternate clock phases. Two external • Wide Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2MHz capacitors are required to store the correcting potentials on • Unity-Gain Compensated the two amplifier nulling inputs; these are the only external components necessary. • Clamp Circuit to Avoid Overload Recovery Problems and Allow Comparator Use The clock oscillator and all the other control circuitry is entirely self-contained. However the 14 lead version includes • Extremely Low Chopping Spikes at Input and Output a provision for the use of an external clock, if required for a • Improved, Direct Replacement for Industry-Standard particular application. In addition, the ICL7650S is internally ICL7650 and other Second-Source Parts compensated for unity-gain operation. • Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART PART NUMBER MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICL7650SCBA-1 7650S CBA-1 0 to +70 8 Ld SOIC M8.15 ICL7650SCBA-1T 7650S CBA-1 0 to +70 8 Ld SOIC (Tape and Reel)M8.15 ICL7650SCBA-1Z (Note) 7650S CBA-1Z 0 to +70 8 Ld SOIC M8.15 ICL7650SCBA-1ZT (Note) 7650S CBA-1Z 0 to +70 8 Ld SOIC (Tape and Reel)M8.15 ICL7650SCPA-1 7650S CPA-1 0 to +70 8 Ld PDIP E8.3 ICL7650SCPA-1Z (Note) 7650S CPA-1Z 0 to +70 8 Ld PDIP* (Pb-free) E8.3 ICL7650SCPD ICL7650SCPD 0 to +70 14 Ld PDIP E14.3 ICL7650SCPDZ 7650SCPDZ 0 to +70 14 Ld PDIP* (Pb-free) E14.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2920 Rev 10.00 Page 1 of 13 April 12, 2007

ICL7650S Pinouts ICL7650S (8 LD PDIP, SOIC) TOP VIEW CEXTA 1 8 CEXTB -IN 2 - 7 V+ + +IN 3 6 OUTPUT V- 4 5 CRETN ICL7650S (14 PDIP) TOP VIEW CEXTB 1 14 INT/EXT CEXTA 2 13 EXT CLK IN NC (GUARD) 3 12 INT CLK OUT -IN 4 - 11 V+ + +IN 5 10 OUTPUT NC (GUARD) 6 9 OUT CLAMP V- 7 8 CRETN Functional Diagram INT/EXT A A EXT CLK IN OSC. B CLK OUT C EXT CLK IN INTERNAL A = CLK OUT BIAS P +IN + A MAIN OUTPUT -IN - B A - C N C A NULL CLAMP + B CAP RETURN CEXTA CEXTB FN2920 Rev 10.00 Page 2 of 13 April 12, 2007

ICL7650S Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V Thermal Resistance (Typical, Note 2) JA (°C/W) JC (°C/W) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +0.3) to (V- -0.3) 8 Lead PDIP Package* . . . . . . . . . . . . 110 N/A Voltage on Oscillator Control Pins. . . . . . . . . . . . . . . . . . . . V+ to V- 14 Lead PDIP Package . . . . . . . . . . . . 90 N/A Duration of Output Short Circuit. . . . . . . . . . . . . . . . . . . . . Indefinite 8 Lead SOIC Package. . . . . . . . . . . . . 160 N/A Current to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C While Operating (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .100A Maximum Storage Temperature Range. . . . . . . . .. -55°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below Operating Conditions http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder Temperature Range processing only. They are not intended for use in Reflow solder ICL7650SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Limiting input current to 100A is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = 5V. See Test Circuit, Unless Otherwise Specified TEMP. PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNITS Input Offset Voltage (Note 3) VOS +25 - 0.7 5 V 0 to +70 - 1 8 V Average Temperature Coefficient of VOS/T 0 to +70 - 0.02 - V/°C Input Offset Voltage (Note 3) Change in Input Offset with Time VOS/T +25 - 100 - nV/month Input Bias Current |I(+)|, |I(-)| IBIAS +25 - 4 10 pA 0 to +70 - 5 20 pA Input Offset Current |I(-), |I(+)| IOS +25 - 8 20 pA 0 to +70 - 10 40 pA Input Resistance RIN +25 - 1012 -  Large Signal Voltage Gain (Note 3) AVOL RL = 10k, VO = 4V +25 135 150 - dB 0 to +70 130 - - dB Output Voltage Swing (Note 4) VOUT RL = 10k +25 4.7 4.85 - V RL = 100k +25 - 4.95 - V Common Mode Voltage Range (Note 3) CMVR +25 -5 -5.2 to +4 3.5 V 0 to +70 -5 - 3.5 V Common Mode Rejection Ratio CMRR CMVR = -5V to +3.5V +25 120 140 - dB (Note 3) 0 to +70 120 - - dB Power Supply Rejection Ratio PSRR VS = 3V to 8V +25 120 140 - dB Input Noise Voltage eN RS = 100, +25 - 2 - VP-P f = DC to 10Hz Input Noise Current iN f = 10Hz +25 - 0.01 - pA/Hz Gain Bandwidth Product GBWP +25 - 2 - MHz Slew Rate SR CL = 50pF, RL = 10k +25 - 2.5 - V/s Rise Time tR +25 - 0.2 - s Overshoot OS +25 - 20 - % Operating Supply Range V+ to V- +25 4.5 - 16 V Supply Current ISUPP No Load +25 - 2 3 mA 0 to +70 - - 3.2 mA FN2920 Rev 10.00 Page 3 of 13 April 12, 2007

ICL7650S Electrical Specifications VSUPPLY = 5V. See Test Circuit, Unless Otherwise Specified (Continued) TEMP. PARAMETER SYMBOL TEST CONDITIONS (°C) MIN TYP MAX UNITS Output Source Current IO SOURCE +25 2.9 4.5 - mA 0 to +70 2.3 - - mA Output Sink Current IO SINK +25 25 30 - mA 0 to +70 20 - - mA Internal Chopping Frequency fCH Pins 13 and 14 Open +25 120 250 375 Hz Clamp ON Current (Note 5) RL = 100k +25 25 70 - A Clamp OFF Current (Note 5) -4V  VOUT  +4V +25 - 0.001 5 nA 0 to +70 - - 10 nA NOTES: 3. These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent precise measurement of these voltages in automatic test equipment. 4. OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs clamp current characteristics. 5. See OUTPUT CLAMP under detailed description. 6. All significant improvements over the industry-standard ICL7650 are highlighted in bold italics. Test Circuit INTERMODULATION R2 Previous chopper-stabilized amplifiers have suffered from 1M intermodulation effects between the chopper frequency and R1 input signals. These arise because the finite AC gain of the 1M amplifier necessitates a small AC signal at the input. This is - seen by the zeroing circuit as an error signal, which is ICL7650S OUTPUT chopped and fed back, thus injecting sum and difference C + CR frequencies and causing disturbances to the gain and phase C vs frequency characteristics near the chopping frequency. 0.1F 0.1F These effects are substantially reduced in the ICL7650S by feeding the nulling circuit with a dynamic current, Application Information corresponding to the compensation capacitor current, in such a way as to cancel that portion of the input signal due to finite Detailed Description AC gain. Since that is the major error contribution to the AMPLIFIER ICL7650S, the intermodulation and gain/phase disturbances are held to very low values, and can generally be ignored. The functional diagram shows the major elements of the ICL7650S. There are two amplifiers, the main amplifier, and the CAPACITOR CONNECTION nulling amplifier. Both have offset-null capability. The main The null/storage capacitors should be connected to the amplifier is connected continuously from the input to the output, CEXTA and CEXTB pins, with a common connection to the while the nulling amplifier, under the control of the chopping CRETN pin. This connection should be made directly by oscillator and clock circuit, alternately nulls itself and the main either a separate wire or PC trace to avoid injecting load amplifier. The nulling connections, which are MOSFET gates, current IR drops into the capacitive circuitry. The outside foil, are inherently high impedance, and two external capacitors where available, should be connected to CRETN. provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement OUTPUT CLAMP operates over the full common-mode and power-supply The OUTPUT CLAMP pin allows reduction of the overload ranges, and is also independent of the output level, thus giving recovery time inherent with chopper-stabilized amplifiers. exceptionally high CMRR, PSRR, and AVOL. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin occurs Careful balancing of the input switches, and the inherent just before the device output saturates. Thus uncontrolled balance of the input circuit, minimizes chopper frequency input differentials are avoided, together with the consequent charge injection at the input terminals, and also the feed charge buildup on the correction-storage capacitors. The forward-type injection into the compensation capacitor, which output swing is slightly reduced. is the main cause of output spikes in this type of circuit. FN2920 Rev 10.00 Page 4 of 13 April 12, 2007

ICL7650S CLOCK the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to The ICL7650S has an internal oscillator, giving a chopping under 1mA to avoid latchup, even under fault conditions. frequency of 200Hz, available at the CLOCK OUT pin on the 14 pin devices. Provision has also been made for the use of an OUTPUT STAGE/LOAD DRIVING external clock in these parts. The INT/EXT pin has an internal The output circuit is a high-impedance type (approximately pull-up and may be left open for normal operation, but to utilize 18k), and therefore with loads less than this value, the an external clock this pin must be tied to V- to disable the chopper amplifier behaves in some ways like a internal clock. The external clock signal may then be applied to transconductance amplifier whose open-loop gain is the EXT CLOCK IN pin. An internal divide-by-two provides the proportional to load resistance. For example, the open-loop desired 50% input switching duty cycle. Since the capacitors gain will be 17dB lower with a 1k load than with a 10k are charged only when EXT CLOCK IN is high, a 50% to 80% load. If the amplifier is used strictly for DC, this lower gain is positive duty cycle is recommended, especially for higher of little consequence, since the DC gain is typically greater frequencies. The external clock can swing between V+ and V-. than 120dB even with a 1k load. However, for wideband The logic threshold will be at about 2.5V below V+. Note also applications, the best frequency response will be achieved that a signal of about 400 Hz, with a 70% duty cycle, will be with a load resistor of 10k or higher. This will result in a present at the EXT CLOCK IN pin with INT/EXT high or open. smooth 6dB/octave response from 0.1Hz to 2MHz, with This is the internal clock signal before being fed to the divider. phase shifts of less than 10° in the transition region where In those applications where a strobe signal is available, an the main amplifier takes over from the null amplifier. alternate approach to avoid capacitor misbalancing during THERMO-ELECTRIC EFFECTS overload can be used. If a strobe signal is connected to EXT The ultimate limitations to ultra-high precision DC amplifiers are CLK IN so that it is low during the time that the overload the thermo-electric or Peltier effects arising in thermocouple signal is applied to the amplifier, neither capacitor will be junctions of dissimilar metals, alloys, silicon, etc. Unless all charged. Since the leakage at the capacitor pins is quite low junctions are at the same temperature, thermoelectric voltages at room temperature, the typical amplifier will drift less than 10V/s, and relatively long measurements can be made with typically around 0.1V/°C, but up to tens of mV/°C for some little change in offset. materials, will be generated. In order to realize the extremely low offset voltages that the chopper amplifier can provide, it is COMPONENT SELECTION essential to take special precautions to avoid temperature The two required capacitors, CEXTA and CEXTB, have gradients. All components should be enclosed to eliminate air optimum values depending on the clock or chopping movement, especially that caused by power-dissipating frequency. For the preset internal clock, the correct value is elements in the system. Low thermoelectric-efficient 0.1F, and to maintain the same relationship between the connections should be used where possible and power supply chopping frequency and the nulling time constant this value voltages and power dissipation should be kept to a minimum. should be scaled approximately in proportion if an external High-impedance loads are preferable, and good separation clock is used. A high quality film type capacitor such as from surrounding heat-dissipating elements is advisable. mylar is preferred, although a ceramic or other lower-grade GUARDING capacitor may prove suitable in many applications. For quickest settling on initial turn-on, low dielectric absorption Extra care must be taken in the assembly of printed circuit capacitors (such as polypropylene) should be used. With boards to take full advantage of the low input currents of the ceramic capacitors, several seconds may be required to ICL7650S. Boards must be thoroughly cleaned with TCE or settle to 1V. alcohol and blown dry with compressed air. After cleaning, the boards should be coated with epoxy or silicone rubber to STATIC PROTECTION prevent contamination. All device pins are static-protected by the use of input diodes. Even with properly cleaned and coated boards, leakage However, strong static fields and discharges should be avoided, currents may cause trouble, particularly since the input pins as they can cause degraded diode junction characteristics, are adjacent to pins that are at supply potentials. This which may result in increased input-leakage currents. leakage can be significantly reduced by using guarding to LATCHUP AVOIDANCE lower the voltage difference between the inputs and adjacent metal runs. The guard, which is a conductive ring Junction-isolated CMOS circuits inherently include a parasitic surrounding the inputs, is connected to a low impedance 4-layer (PNPN) structure which has characteristics similar to point that is at approximately the same voltage as the inputs. an SCR. Under certain circumstances this junction may be Leakage currents from high-voltage pins are then absorbed triggered into a low-impedance state, resulting in excessive by the guard. supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established either at FN2920 Rev 10.00 Page 5 of 13 April 12, 2007

ICL7650S INPUT R1 - R2 - OUTPUT OUTPUT + INPUT + FIGURE 1A. INVERTING AMPLIFIER FIGURE 1B. FOLLOWER R2 - OUTPUT + R1 INPUT NOTE: R----R----1--+---R---R-2----- SIMHPOEUDLADN BCEE LFOOWR 1 2 OPTIMUM GUARDING FIGURE 1C. NON-INVERTING AMPLIFIER FIGURE 1. CONNECTION OF INPUT GUARDS PIN COMPATIBILITY as shown in Figure 4, to enable the full output capabilities of the LM741 (or any other standard device) to be combined The basic pinout of the 8-pin device corresponds, where with the input capabilities of the ICL7650S. The pair form a possible, to that of the industry standard 8-pin devices, the composite device, so loop gain stability, when the feedback LM741, LM101, etc. The null-storing external capacitors are network is added, should be watched carefully. connected to pins 1 and 8, usually used for offset null or compensation capacitors, or simply not connected. In the case of the OP-05 and OP-07 devices, the replacement of 0.1F 0.1F C the offset-null pot, connected between pins 1 and 8 and V+, R INPUT + C by two capacitors from those pins to pin 5, will provide easy 7650S OUTPUT compatibility. As for the LM108, replacement of the - CLAMP R2 compensation capacitor between pins 1 and 8 by the two coappearactiitoonrs, wtoi tphi nth 5e irse mallo tvhaal to isf anneyc ecsosnanreyc. tTiohne tsoa pmine 5, will R3 + (R1||R2)  100k R3 R1 For Full Clamp Effect suffice for the LM101, A748, and similar parts. NOTE: R1||R2 indicates the parallel combination of R1 and R2. The 14-pin device pinout corresponds most closely to that of FIGURE 2. NON INVERTING AMPLIFIER WITH OPTIONAL CLAMP the LM108 device, owing to the provision of “NC” pins for guarding between the input and all other pins. Since this Figure 5 shows the use of the clamp circuit to advantage in a device does not use any of the extra pins, and has no zero-offset comparator. The usual problems in using a provision for offset-nulling, but requires a compensation chopper stabilized amplifier in this application are avoided, capacitor, some changes will be required in layout to convert since the clamp circuit forces the inverting input to follow the it to the ICL7650S. input signal. The threshold input must tolerate the output clamp current  VlN/R without disturbing other portions of the Typical Applications system. Clearly the applications of the ICL7650S will mirror those of The pin configuration of the 14 pin dual in-line package is other op amps. Anywhere that the performance of a circuit designed to facilitate guarding, since the pins adjacent to the can be significantly improved by a reduction of input-offset inputs are not used (this is different from the standard 741 and voltage and bias current, the ICL7650S is the logical choice. 101A pin configuration, but corresponds to that of the LM108). Basic non-inverting and inverting amplifier circuits are shown in Figures 2 and 3. Both circuits can use the output clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of other op amps by the ICL7650S are the supply voltage (8V Max) and the output drive capability (10k load for full swing). Even these limitations can be overcome using a simple booster circuit, FN2920 Rev 10.00 Page 6 of 13 April 12, 2007

ICL7650S R2 CLAMP + +7.5V +15V CLAMP R1 IN 7650S + INPUT - - 741 OUT 7650S OUTPUT - + C -7.5V -15V R C 0.1F 0.1F 0.1F 0.1F 10k 10k (R1||R2)  100k For Full Clamp Effect NOTE: R1||R2 indicates the parallel combination of R1 and R2. FIGURE 4. USING 741 TO BOOST OUTPUT DRIVE CAPACITY FIGURE 3. INVERTING AMPLIFIER WITH (OPTIONAL) CLAMP 0.1F 0.1F C R VIN + C 7650S VOUT - CLAMP R VTH 200k - 2M FIGURE 5. LOW OFFSET COMPARATOR VREF RREF V+ (+15V) - 33k 33k IREF R5 ICL7650S 5 4 16 13 2k 12 + Q1 Q2 IIN VIN RIN 2 +-A1 R3 +-A2 10 VOUT 1 R1 ICL8048 GROUND GAIN 15.9k 150pF C1 7 15 R2 680 1k (LOW T.C.) R0 10k NOTE: For further Applications Assistance, see AN053. FIGURE 6. ICL8048 OFFSET NULLED BY ICL7650S Normal logarithmic amplifiers are limited in dynamic range in capability to their very high slew rates and bandwidths. Note the voltage-input mode by their input-offset voltage. The that these circuits will also have their DC gains, CMRR, and built-in temperature compensation and convenience PSRR enhanced. features of the ICL8048 can be extended to a voltage-input dynamic range of close to 6 decades by using the ICL7650S to offset-null the ICL8048, as shown in Figure 6. The same concept can also be used with such devices as the HA2500 or HA2600 families of op amps to add very low offset voltage FN2920 Rev 10.00 Page 7 of 13 April 12, 2007

ICL7650S Typical Performance Curves 3 3 A) A) m m ENT ( 2 ENT ( 2 R R R R U U C C PLY 1 PLY P P 1 U U S S 0 0 4 6 8 10 12 14 16 -50 -25 0 25 50 75 100 125 TOTAL SUPPLY VOLTAGE (V) TEMPERATURE (°C) FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 8. SUPPLY CURRENT vs AMBIENT TEMPERATURE 8 8 mA) 6 MIT 7 RRENT ( 4 LTAGE LI 65 NEGALTIMIVIET CU 2 VO T E 4 POSITIVE UTPU 0 MOD 3 LIMIT O N UM -10 MO 2 M M AXI -20 CO 1 M -30 0 0 1 2 3 4 5 6 7 8 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V) FIGURE 9. MAXIMUM OUTPUT CURRENT vs SUPPLY FIGURE 10. COMMON MODE INPUT VOLTAGE RANGE vs VOLTAGE SUPPLY VOLTAGE T 4 AKAGE CURREN RRED TO INPUT) 100 BROADBAND NOISE 0.1F GE (V)P-P 3 K RIPPLE DUE TO LE AP PINS (V REFEP-P 101 (AV = 1000) 1.0F 10Hz NOISE VOLTA 21 C C O T CL A 0.1 0 25 50 75 100 125 150 10 100 1k 10k TEMPERATURE (oC) CHOPPING FREQUENCY - CLOCK OUT (Hz) FIGURE 11. CLOCK RIPPLE REFERRED TO THE INPUT vs FIGURE 12. 10Hz NOISE VOLTAGE vs CHOPPING TEMPERATURE FREQUENCY FN2920 Rev 10.00 Page 8 of 13 April 12, 2007

ICL7650S Typical Performance Curves (Continued) 8 3 V)  GE ( 2 AN V) 6 CH 1 E ( E G G A OLTA 0 VOLT 4 V T FFSET -1 OFFSE 2 O T -2 U P N I 0 -3 10 100 1k 10k 4 6 8 10 12 14 16 CHOPPING FREQUENCY - CLOCK OUT (Hz) TOTAL SUPPLY VOLTAGE (V) FIGURE 14. INPUT OFFSET VOLTAGE vs CHOPPING FIGURE 13. INPUT OFFSET VOLTAGE CHANGE vs SUPPLY FREQUENCY VOLTAGE 160 RL = 10k 140 CEXT = 0.1F OUTPUT (mV) 22000 20mV/DIV.1ms/DIV. LOOP GAIN (dB) 11208000 975000 SE SHIFT (°) PEN 60 110 PHA O 130 40 20 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1k 10k 100k TIME (ms) FREQUENCY (Hz) FIGURE 15. OUTPUT WITH ZERO INPUT; GAIN = 1000; FIGURE 16. OPEN LOOP GAIN AND PHASE SHIFT vs BALANCED SOURCE IMPEDANCE = 10k FREQUENCY FN2920 Rev 10.00 Page 9 of 13 April 12, 2007

ICL7650S Typical Performance Curves (Continued) 160 2 RL = 10k 140 CEXT = 1F V) GAIN (dB) 112000 7500 FT (°) T VOLTAGE ( 10 CLOCK LOOUWT CHILGOHCK OUT OOP 80 90 E SHI UTPU -1 L S O PEN 60 110 PHA -2 O 130 40 0 0.5 1.0 1.5 2.0 2.5 20 TIME (s) 0.01 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) NOTE: The two different responses correspond to the two phases of the clock. FIGURE 17. OPEN LOOP GAIN AND PHASE SHIFT vs FIGURE 18. VOLTAGE FOLLOWER LARGE SIGNAL PULSE FREQUENCY RESPONSE (NOTE) 100A 2 10A T N V) E E ( 1 RR 1A G U A C OLT 0 MP 100nA PUT V CLOCKH OIGUHT CLOLOWCK OUT L CLA 10nA UT -1 NE 1nA O N A H100pA -2 C N- 10pA 0 0.5 1.0 1.5 2.0 1pA NOTE: 0.8 0.6 0.4 0.2 0 TIME (S) The two different responses correspond to the two phases of the clock. OUTPUT VOLTAGE (V-) FIGURE 19. VOLTAGE FOLLOWER LARGE SIGNAL PULSE FIGURE 20. N-CHANNEL CLAMP CURRENT vs OUTPUT RESPONSE (NOTE) VOLTAGE 100A T 10A N E RR 1A U C P 100nA M A L 10nA C L NE 1nA N A H 100pA C P- 10pA 1pA -0.8 -0.6 -0.4 -0.2 0 OUTPUT VOLTAGE (V+) FIGURE 21. P-CHANNEL CLAMP CURRENT vs OUTPUT VOLTAGE FN2920 Rev 10.00 Page 10 of 13 April 12, 2007

ICL7650S Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated N 8 8 9 in JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN2920 Rev 10.00 Page 11 of 13 April 12, 2007

ICL7650S Dual-In-Line Plastic Packages (PDIP) N E14.3 (JEDEC MS-001-AA ISSUE D) E1 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INDEX AREA 1 2 3 N/2 INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES -A- A - 0.210 - 5.33 4 D E A1 0.015 - 0.39 - 4 BASE PLANE A2 -C- A A2 0.115 0.195 2.93 4.95 - SEATING PLANE L CL B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8 D1 D1 A1 eA B1 e eC C C 0.008 0.014 0.204 0.355 - B D 0.735 0.775 18.66 19.68 5 e B 0.010 (0.25) M C A B S D1 0.005 - 0.13 - 5 NOTES: E 0.300 0.325 7.62 8.25 6 1. Controlling Dimensions: INCH. In case of conflict between English E1 0.240 0.280 6.10 7.11 5 and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eA 0.300 BSC 7.62 BSC 6 Publication No. 95. eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in L 0.115 0.150 2.93 3.81 4 JEDEC seating plane gauge GS-3. N 14 14 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). Rev. 0 12/93 6. E and eA are measured with the leads constrained to be perpen- dicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN2920 Rev 10.00 Page 12 of 13 April 12, 2007

ICL7650S Small Outline Plastic Packages (SOIC) N M8.15 (JEDEC MS-012-AA ISSUE C) INDEX AREA H 0.25(0.010) M B M 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE E INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 1 2 3 L A1 0.0040 0.0098 0.10 0.25 - SEATING PLANE B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - -A- D A h x 45o D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 -C- µ e 0.050 BSC 1.27 BSC - e A1 C H 0.2284 0.2440 5.80 6.20 - B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5 0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6 N 8 8 7 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  0° 8° 0° 8° - Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2002-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2920 Rev 10.00 Page 13 of 13 April 12, 2007