DATASHEET ICL7611, ICL7612 FN2919 1.4MHz, Low Power CMOS Operational Amplifiers Rev 9.00 April 26, 2007 The ICL761X series is a family of CMOS operational Features amplifiers. These devices provide the designer with high • Wide Operating Voltage Range . . . . . . . . . . . 1V to 8V performance operation at low supply voltages and selectable quiescent currents, and are an ideal design tool when ultra • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1012 low input current and low power dissipation are desired. • Programmable Power Consumption . . . . . Low as 20W The basic amplifier will operate at supply voltages ranging • Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ) from 1V to 8V, and may be operated from a single Lithiumcell. • Output Voltage Swing . . . . . . . . . . . . . . . . . . . V+ and V- A unique quiescent current programming pin allows setting • Input Common Mode Voltage Range Greater Than Supply Rails (ICL7612) of standby current to 1mA, 100A, or 10A, with no external components. This results in power consumption as low as • Pb-Free Plus Anneal Available (RoHS Compliant) 20W. The output swing ranges to within a few millivolts of Applications the supply voltages. Of particular significance is the extremely low (1pA) input • Portable Instruments current, input noise current of 0.01pA/Hz, and 1012 input • Telephone Headsets impedance. These features optimize performance in very high source impedance applications. • Hearing Aid/Microphone Amplifiers • Meter Amplifiers The inputs are internally protected. Outputs are fully protected against short circuits to ground or to either supply. • Medical Instruments AC performance is excellent, with a slew rate of 1.6V/s, and • High Impedance Buffers unity gain bandwidth of 1MHz at IQ = 1mA. Because of the low power dissipation, junction temperature rise and drift are quite low. Applications utilizing these features may include stable instruments, extended life designs, or high density packages. Pinouts ICL7611, ICL7612 (8 LD PDIP, 8 LD SOIC) TOP VIEW BAL 1 8 IQ SET -IN 2 - 7 V+ + +IN 3 6 OUT V- 4 5 BAL FN2919 Rev 9.00 Page 1 of 13 April 26, 2007

ICL7611, ICL7612 Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # ICL7611DCBA 7611 DCBA 0 to +70 8 Ld SOIC (150 mil) M8.15 ICL7611DCBAZ (Note) 7611 DCBAZ 0 to +70 8 Ld SOIC (150 mil) (Pb-free) M8.15 ICL7611DCBA-T 7611 DCBA 0 to +70 8 Ld SOIC (150 mil) Tape and Reel M8.15 ICL7611DCBAZ-T (Note) 7611 DCBAZ 0 to +70 8 Ld SOIC (150 mil) Tape and Reel (Pb-free) M8.15 ICL7611DCPA 7611 DCPA 0 to +70 8 Ld PDIP E8.3 ICL7611DCPAZ (Note) 7611 DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3 ICL7612BCPA 7612 BCPA 0 to +70 8 Ld PDIP E8.3 ICL7612BCPAZ 7612 BCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3 ICL7612DCBA 7612 DCBA 0 to +70 8 Ld SOIC (150 mil) M8.15 ICL7612DCBA-T 7612 DCBA 0 to +70 8 Ld SOIC (150 mil) Tape and Reel M8.15 ICL7612DCBAZ (Note) 7612 DCBAZ 0 to +70 8 Ld SOIC (150 mil) (Pb-free) M8.15 ICL7612DCBAZ-T (Note) 7612 DCBAZ 0 to +70 8 Ld SOIC (150 mil) Tape and Reel (Pb-free) M8.15 ICL7612DCPA 7612 DCPA 0 to +70 8 Ld PDIP E8.3 ICL7612DCPAZ (Note) 7612 DCPAZ 0 to +70 8 Ld PDIP* (Pb-free) E8.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN2919 Rev 9.00 Page 2 of 13 April 26, 2007

ICL7611, ICL7612 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Thermal Resistance (Typical, Note 3) JA (°C/W) Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Differential Input Voltage (Note 1) . . . . . . . . [(V+ +0.3) - (V- -0.3)]V SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Duration of Output Short Circuit (Note 2). . . . . . . . . . . . . . Unlimited Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C Operating Conditions Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Temperature Range ICL761XC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time. 2. The outputs may be shorted to ground or to either supply, for VSUPPLY 10V. Care must be taken to insure that the dissipation rating is not exceeded. 3. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = 5V, Unless Otherwise Specified. ICL7612B ICL7611D, ICL7612D TEST TEMP PARAMETER SYMBOL CONDITIONS (°C) MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage VOS RS  100k +25 - - 5 - - 15 mV Full - - 7 - - 20 mV Temperature Coefficient of VOS VOS/T RS  100k - - 15 - - 25 - V/°C Input Offset Current IOS +25 - 0.5 30 - 0.5 30 pA Full - - 300 - - 300 pA Input Bias Current IBIAS +25 - 1.0 50 - 1.0 50 pA Full - - 400 - - 400 pA Common Mode Voltage Range VCMR IQ = 10A +25 - - - 4.4 - - V (ICL7611 Only) IQ = 100A +25 - - - 4.2 - - V IQ = 1mA +25 - - - 3.7 - - V Extended Common Mode Voltage VCMR IQ = 10A +25 5.3 - - 5.3 - - V Range (ICL7612 Only) IQ = 100A +25 +5.3, - - +5.3, - - - V -5.1 5.1 IQ = 1mA +25 +5.3, - - - +5.3, - - - V 4.5 4.5 Output Voltage Swing VOUT IQ = 10A, RL = 1M +25 4.9 - - 4.9 - - V Full 4.8 - - 4.8 - - V IQ = 100A, RL = 100k +25 4.9 - - 4.9 - - V Full 4.8 - - 4.8 - - V IQ = 1mA, RL = 10k +25 4.5 - - 4.5 - - V Full 4.3 - - 4.3 - - V Large Signal Voltage Gain AVOL VO = 4.0V, RL=1M, +25 80 104 - 80 104 - dB IQ = 10A Full 75 - - 75 - - dB VO = 4.0V, RL=100k, +25 80 102 - 80 102 - dB IQ=100A Full 75 - - 75 - - dB VO = 4.0V, RL=10k, +25 76 83 - 76 83 - dB IQ = 1mA Full 72 - - 72 - - dB FN2919 Rev 9.00 Page 3 of 13 April 26, 2007

ICL7611, ICL7612 Electrical Specifications VSUPPLY = 5V, Unless Otherwise Specified. (Continued) ICL7612B ICL7611D, ICL7612D TEST TEMP PARAMETER SYMBOL CONDITIONS (°C) MIN TYP MAX MIN TYP MAX UNITS Unity Gain Bandwidth GBW IQ = 10A +25 - 0.044 - - 0.044 - MHz IQ = 100A +25 - 0.48 - - 0.48 - MHz IQ = 1mA +25 - 1.4 - - 1.4 - MHz Input Resistance RIN +25 - 1012 - - 1012 -  Common Mode Rejection Ratio CMRR RS  100kIQ = 10A +25 70 96 - 70 96 - dB RS  100kIQ = 100A +25 70 91 - 70 91 - dB RS  100kIQ = 1mA +25 60 87 - 60 87 - dB Power Supply Rejection Ratio PSRR RS  100kIQ = 10A +25 80 94 - 80 94 - dB (VSUPPLY = 8V to 2V) RS  100k +25 80 86 - 80 86 - dB IQ=100A RS  100kIQ = 1mA +25 70 77 - 70 77 - dB Input Referred Noise Voltage eN RS = 100, f = 1kHz +25 - 100 - - 100 - nV/Hz Input Referred Noise Current iN RS = 100, f = 1kHz +25 - 0.01 - - 0.01 - pA/Hz Supply Current (No Signal, No ISUPPLY IQ SET = +5V, Low Bias +25 - 0.01 0.02 - 0.01 0.02 mA Load) IQ SET = 0V, +25 - 0.1 0.25 - 0.1 0.25 mA Medium Bias IQ SET = -5V, High Bias +25 - 1.0 2.5 - 1.0 2.5 mA Channel Separation VO1/VO2 AV = 100 +25 - 120 - - 120 - dB Slew Rate SR IQ = 10A, RL = 1M +25 - 0.016 - - 0.016 - V/s (AV = 1, CL = 100pF, VIN = 8VP-P) IQ = 100A, RL=100k +25 - 0.16 - - 0.16 - V/s IQ = 1mA, RL = 10k +25 - 1.6 - - 1.6 - V/s Rise Time tr IQ = 10A, RL = 1M +25 - 20 - - 20 - s (VIN = 50mV, CL=100pF) IQ = 100A, +25 - 2 - - 2 - s RL=100k IQ = 1mA, RL = 10k +25 - 0.9 - - 0.9 - s Overshoot Factor OS IQ = 10A, RL = 1M +25 - 5 - - 5 - % (VIN = 50mV, CL=100pF) IQ = 100A, +25 - 10 - - 10 - % RL=100k IQ = 1mA, RL = 10k +25 - 40 - - 40 - % Electrical Specifications VSUPPLY = 1V, IQ = 10A, Unless Otherwise Specified. ICL7612B TEST PARAMETER SYMBOL CONDITIONS TEMP (°C) MIN TYP MAX UNITS Input Offset Voltage VOS RS  100k +25 - - 5 mV Full - - 7 mV Temperature Coefficient of VOS VOS/T RS  100k - - 15 - V/°C Input Offset Current IOS +25 - 0.5 30 pA Full - - 300 pA Input Bias Current IBIAS +25 - 1.0 50 pA Full - - 500 pA Extended Common Mode VCMR +25 +0.6 to -1.1 - - V Voltage Range FN2919 Rev 9.00 Page 4 of 13 April 26, 2007

ICL7611, ICL7612 Electrical Specifications VSUPPLY = 1V, IQ = 10A, Unless Otherwise Specified. (Continued) ICL7612B TEST PARAMETER SYMBOL CONDITIONS TEMP (°C) MIN TYP MAX UNITS Output Voltage Swing VOUT RL = 1M +25 0.98 - - V Full 0.96 - - V Large Signal Voltage Gain AVOL VO = 0.1V, RL=1M +25 - 90 - dB Full - 80 - dB Unity Gain Bandwidth GBW +25 - 0.044 - MHz Input Resistance RIN +25 - 1012 -  Common Mode Rejection Ratio CMRR RS  100k +25 - 80 - dB Power Supply Rejection Ratio PSRR RS  100k +25 - 80 - dB Input Referred Noise Voltage eN RS = 100, f = 1kHz +25 - 100 - nV/Hz Input Referred Noise Current iN RS = 100, f = 1kHz +25 - 0.01 - pA/Hz Supply Current ISUPPLY No Signal, No Load +25 - 6 15 A Slew Rate SR AV = 1, CL = 100pF, +25 - 0.016 - V/s VIN = 0.2VP-P, RL=1M Rise Time tr VIN = 50mV, CL=100pF RL = 1M +25 - 20 - s Overshoot Factor OS VIN = 50mV, CL=100pF, RL = 1M +25 - 5 - % Schematic Diagram IQ INPUT STAGE SETTING STAGE OUTPUT STAGE V+ 900k 3k 3k BAL BAL QP5 QP6 QP7 6.3V 100k QP8 QP1 QP1 QP3 QP4 V+ QP9 +INPUT QN1 QN2 CFF = 9pF OUTPUT V- CC = 33pF V+ -INPUT QN7 V- QN4 QN6 QN9 QN10 QN11 QN5 6.3V QN3 QN8 V- V+ IQ SET FN2919 Rev 9.00 Page 5 of 13 April 26, 2007

ICL7611, ICL7612 Application Information Static Protection IQ=10A, nulling may not be possible with higher values All devices are static protected by the use of input diodes. of VOS. However, strong static fields should be avoided, as it is Frequency Compensation possible for the strong fields to cause degraded diode The ICL7611 and ICL7612 are internally compensated, and junction characteristics, which may result in increased input are stable for closed loop gains as low as unity with leakage currents. capacitive loads up to 100pF. Latchup Avoidance Extended Common Mode Input Range Junction-isolated CMOS circuits employ configurations which The ICL7612 incorporates additional processing which produce a parasitic 4-layer (PNPN) structure. The 4-layer allows the input CMVR to exceed each power supply rail by structure has characteristics similar to an SCR, and under 0.1V for applications where VSUPP  1.5V. For those certain circumstances may be triggered into a low impedance applications where VSUPP  1.5V the input CMVR is limited state resulting in excessive supply current. To avoid this in the positive direction, but may exceed the negative supply condition, no voltage greater than 0.3V beyond the supply rail by 0.1V in the negative direction (e.g., for VSUPPLY=1V, rails may be applied to any pin. In general, the op amp the input CMVR would be +0.6V to -1.1V). supplies must be established simultaneously with, or before any input signals are applied. If this is not possible, the drive Operation At V = 1V SUPPLY circuits must limit input current flow to 2mA to prevent latchup. Operation at VSUPPLY = 1V is guaranteed at IQ = 10A for Choosing the Proper I A and B grades only. Q The ICL7611 and ICL7612 have a similar IQ set-up scheme, Output swings to within a few millivolts of the supply rails are which allows the amplifier to be set to nominal quiescent achievable for RL  1M. Guaranteed input CMVR is 0.6V currents of 10A, 100A or 1mA. These current settings minimum and typically +0.9V to -0.7V at VSUPPLY = 1V. For change only very slightly over the entire supply voltage applications where greater common mode range is range. The ICL7611 and ICL7612 have an external IQ desirable, refer to the description of ICL7612 above. control terminal, permitting user selection of quiescent Typical Applications current. To set the IQ connect the IQ terminal as follows: The user is cautioned that, due to extremely high input IQ = 10A - IQ pin to V+ impedances, care must be exercised in layout, construction, IQ = 100A - IQ pin to ground. If this is not possible, any board cleanliness, and supply filtering to avoid hum and voltage from V+ - 0.8 to V- +0.8 can be used. noise pickup. IQ = 1mA - IQ pin to V- Note that in no case is IQ shown. The value of IQ must be chosen by the designer with regard to frequency response NOTE: The output current available is a function of the quiescent current setting. For maximum peak-to-peak output voltage swings and power dissipation. into low impedance loads, IQ of 1mA should be selected. Output Stage and Load Driving Considerations VIN + Each amplifiers’ quiescent current flows primarily in the ICL7612 VOUT output stage. This is approximately 70% of the IQ settings. - This allows output swings to almost the supply rails for RL 10k output loads of 1M, 100k, and 10k, using the output stage in a highly linear class A mode. In this mode, FIGURE 1. SIMPLE FOLLOWER (NOTE 4) crossover distortion is avoided and the voltage gain is maximized. However, the output stage can also be operated in Class AB for higher output currents. (See graphs under VIN +5 - +5 Typical Operating Characteristics). During the transition from ICL7612 VOUT Class A to Class B operation, the output transfer 100k + TO CMOS OR characteristic is non-linear and the voltage gain decreases. LPTTL LOGIC Input Offset Nulling 1M Offset nulling may be achieved by connecting a 25k pot NOTE: between the BAL terminals with the wiper connected to V+. 4. By using the ICL7612 in this application, the circuit will follow rail At quiescent currents of 1mA and 100A the nulling range to rail inputs. provided is adequate for all VOS selections; however with FIGURE 2. LEVEL DETECTOR (NOTE 4) FN2919 Rev 9.00 Page 6 of 13 April 26, 2007

ICL7611, ICL7612 - 1M 1F ICL7611 - + + ICL7611 + - 1M ICL7611 VOUT 1M  + V- V+ DUTY CYCLE 680k WAVEFORM GENERATOR NOTE: Low leakage currents allow integration times up to several NOTE: Since the output range swings exactly from rail to rail, frequency hours. and duty cycle are virtually independent of power supply variations. FIGURE 3. PHOTOCURRENT INTEGRATOR FIGURE 4. PRECISE TRIANGLE/SQUARE WAVE GENERATOR 1M +8V VOH 0.5F 10k 2.2M 20k VIN TSOUCCEED- + V+ TA = +125°C + 10F 20k IINNGPUT ICL7611 STAGE OUT - 1.8k = 5% IQ SCALE - V- ADJUST VOL - V+ ICL7611 -8V COMMON + FIGURE 5. AVERAGING AC TO DC CONVERTER FOR A/D FIGURE 6. BURN-IN AND LIFE TEST CIRCUIT CONVERTERS SUCH AS ICL7106, ICL7107, ICL7109, ICL7116, ICL7117 - VIN BAL VOUT +BAL 25k V+ FIGURE 7. VOS NULL CIRCUIT FN2919 Rev 9.00 Page 7 of 13 April 26, 2007

ICL7611, ICL7612 0.2F 0.2F 0.2F 30k 160k + 680k 100k 51k ICL7611 + - ICL7611 - 360k INPUT 0.1F 0.2F 0.1F 1M OUTPUT 360k (NOTE 5) 1M (NOTE 5) NOTES: 5. Note that small capacitors (25pF to 50pF) may be needed for stability in some cases. 6. The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fC = 10Hz, AVCL = 4, Passband ripple = 0.1dB. FIGURE 8. FIFTH ORDER CHEBYCHEV MULTIPLE FEEDBACK LOW PASS FILTER Typical Performance Curves 10k 104 TA = +25°C V+ - V- = 10V NO LOAD IQ = 1mA NO LOAD NO SIGNAL NO SIGNAL A) 1k A) 103 IQ = 1mA T ( T ( N N RE IQ = 100A RE UR 100 UR 102 IQ = 100A C C Y Y L L PP IIQQ == 110mAA PP SU 10 SU 10 IQ = 10A 1 1 0 2 4 6 8 10 12 14 16 -50 -25 0 25 50 75 100 125 SUPPLY VOLTAGE (V) FREE-AIR TEMPERATURE (°C) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR VOLTAGE TEMPERATURE 1000 1000 V) VSUPP = 10V VS = 5V kV/ VOUT = 8V A) N ( T (p 100 GAI RIQL = = 1 10MA N E 100 E G URR LTA RIQL = = 1 10000kA AS C 10 L VO IRQL = = 1 1m0kA INPUT BI 1.0 FERENTIA 10 F DI 0.1 1 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125 FREE-AIR TEMPERATURE (°C) FREE-AIR TEMPERATURE (°C) FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 12. LARGE SIGNAL DIFFERENTIAL VOLTAGE GAIN vs FREE-AIR TEMPERATURE FN2919 Rev 9.00 Page 8 of 13 April 26, 2007

ICL7611, ICL7612 Typical Performance Curves (Continued) 107 105 V/V) 106 TVAS U=P +P2 =5 °1C5V O (dB) 100 VSUPP = 10V N ( ATI IQ = 10A ERENTIAL VOLTAGE GAI 111100004325 PH(IAQS =E 1 SmHAIF)T IQ =I Q10 =0 1AmA 04950 ASE SHIFT (°) ON MODE REJECTION R 99885050 IQ =I Q1 m= A100A DIFF 10 IQ = 10A 135 PH OMM 75 1 180 C 70 0.1 1.0 10 100 1k 10k 100k 1M -75 -50 -25 0 25 50 75 100 125 FREQUENCY (Hz) FREE-AIR TEMPERATURE (°C) FIGURE 13. LARGE SIGNAL FREQUENCY RESPONSE FIGURE 14. COMMON MODE REJECTION RATIO vs FREE-AIR TEMPERATURE 100 z) 600 H dB) IQ = 1mA VSUPP = 10V V/ TA = +25°C ATIO ( 95 GE (n 500 3V  VSUPP  16V ON R 90 IQ = 100A OLTA 400 TI V C 85 E EJE IQ = 10A OIS 300 E R 80 T N G U A P 200 OLT 75 T IN V N PLY 70 ALE 100 P V U UI S 65 Q 0 -75 -50 -25 0 25 50 75 100 125 E 10 100 1k 10k 100k FREE-AIR TEMPERATURE (°C) FREQUENCY (Hz) FIGURE 15. POWER SUPPLY REJECTION RATIO vs FREE-AIR FIGURE 16. EQUIVALENT INPUT NOISE VOLTAGE vs TEMPERATURE FREQUENCY 16 16 OUTPUT VOLTAGE (V)P-P 11142086 V=V=SSUU85PPVVPP TA = III+QQQ2 ===5 °111C00m0AAA OUTPUT VOLTAGE (V)P-P 11142086 VIQS =U P1Pm =A 10V TTTAAA === -++521552°°5CC°C M M MU 4 MU 4 MAXI 2 VSUPP MAXI 2 =2V 0 0 100 1k 10k 100k 1M 10M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 17. OUTPUT VOLTAGE vs FREQUENCY FIGURE 18. OUTPUT VOLTAGE vs FREQUENCY FN2919 Rev 9.00 Page 9 of 13 April 26, 2007

ICL7611, ICL7612 Typical Performance Curves (Continued) 16 12 )P-P 14 TA = +25°C )P-P 10 RL = 100k V V E ( E ( G 12 G VOLTA 10 RL = 100k - 1M VOLTA 8 RL = 10k T T 6 TPU 8 RL = 10k TPU RL = 2k U U O O 4 M 6 M U U AXIM 4 AXIM 2 VIQS =U P1Pm =A 10V M M 0 2 4 6 8 10 12 14 16 -75 -50 -25 0 25 50 75 100 125 SUPPLY VOLTAGE (V) FREE-AIR TEMPERATURE (°C) FIGURE 19. OUTPUT VOLTAGE vs SUPPLY VOLTAGE FIGURE 20. OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE mA) 40 A)0.01 NT ( IQ = 1mA T (m E N RR 30 RE IQ = 10A CU UR 0.1 E C OURC 20 SINK S T T U IQ = 100A U P TP UT 1.0 U O M O 10 UM U M XIM AXI IQ = 1mA A M M 0 10 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 21. OUTPUT SOURCE CURRENT vs SUPPLY VOLTAGE FIGURE 22. OUTPUT SINK CURRENT vs SUPPLY VOLTAGE 16 8 V)P-P 14 VITQA+ ==- 1V+m-2 =5A °1C0V E (V) 6 TRAL == +1205k°C, ,C VLS =U P1P0 0=p 1F0V AGE ( 12 LTAG 4 VOLT 10 T VO 2 PUT 8 UTPU 0 OUTPUT OUT 6 D O MUM 4 T AN -2 INPUT XI PU -4 A 2 N M I 0 -6 0.1 1.0 10 100 0 2 4 6 8 10 12 LOAD RESISTANCE (k) TIME (s) FIGURE 23. OUTPUT VOLTAGE vs LOAD RESISTANCE FIGURE 24. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 1mA) FN2919 Rev 9.00 Page 10 of 13 April 26, 2007

ICL7611, ICL7612 Typical Performance Curves (Continued) 8 8 V) TA = +25°C, VSUPP = 10V V) TA = +25°C, VSUPP = 10V E ( 6 RL = 100k, CL = 100pF E ( 6 RL = 1M, CL = 100pF G G A A LT 4 LT 4 O O V V UT 2 UT 2 TP OUTPUT TP OUTPUT U U O 0 O 0 ND ND INPUT T A -2 T A -2 PU INPUT PU N -4 N -4 I I -6 -6 0 20 40 60 80 100 120 0 200 400 600 800 1000 1200 TIME (s) TIME (s) FIGURE 25. VOLTAGE FOLLOWER LARGE SIGNAL PULSE FIGURE 26. VOLTAGE FOLLOWER LARGE SIGNAL PULSE RESPONSE (IQ = 100A) RESPONSE (IQ = 10A) FN2919 Rev 9.00 Page 11 of 13 April 26, 2007

ICL7611, ICL7612 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - 1 2 3 L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0075 0.0098 0.19 0.25 - -A- D 0.1890 0.1968 4.80 5.00 3 D A h x 45° E 0.1497 0.1574 3.80 4.00 4 -C- e 0.050 BSC 1.27 BSC -  H 0.2284 0.2440 5.80 6.20 - e A1 C h 0.0099 0.0196 0.25 0.50 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 8 8 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN2919 Rev 9.00 Page 12 of 13 April 26, 2007

ICL7611, ICL7612 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated N 8 8 9 in JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2004-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2919 Rev 9.00 Page 13 of 13 April 26, 2007