HSMP-389x Series, HSMP-489x Series Surface Mount RF PIN Switch Diodes Data Sheet Description/Applications Features The HSMP-389x series is optimized for switching appli- • Unique Configurations in Surface Mount Packages cations where low resistance at low current and low ca- – Add Flexibility pacitance are required. The HSMP-489x series products – Save Board Space feature ultra low parasitic inductance. These products are specifically designed for use at frequencies which – Reduce Cost are much higher than the upper limit for conventional • Switching PIN diodes. – Low Capacitance Pin Connections and Package Marking – Low Resistance at Low Current • Low Failure in Time (FIT) Rate[1] • Matched Diodes for Consistent Performance 1 6 • Better Thermal Conductivity for Higher Power G Dissipation 2 U 5 • Lead-free Note: x 1. For more information see the Surface Mount PIN Reliability Data Sheet. 3 4 Notes: 1. Package marking provides orientation, identification, and date code. 2. See “Electrical Specifications” for appropriate package marking.

Package Lead Code Identification, Package Lead Code Identification, Package Lead Code Identification, SOT-23/143 SOT-323 SOT-363 (Top View) (Top View) (Top View) SINGLE SERIES SINGLE SERIES UNCONNECTED DUALSWITCH TRIO MODEL 6 5 4 6 5 4 #0 #2 B C 1 2 3 1 2 3 L R COMMON COMMON COMMON COMMON ANODE CATHODE ANODE CATHODE LOW INDUCTANCE SERIES– SINGLE SHUNTPAIR 6 5 4 6 5 4 #3 #4 E F UNCONNECTED DUALANODE 1 2 3 1 2 3 T U PAIR DUALANODE HIGH FREQUENCY SERIES 489B 6 5 4 #5 4890 RING 1 2 3 QUAD V 3 4 1 2 #7 UNDERDEVELOPMENT Absolute Maximum Ratings[1] T = +25°C C Symbol Parameter Unit SOT-23/143 SOT-323/363 I Forward Current (1 µs Pulse) Amp 1 1 f P Peak Inverse Voltage V 100 100 IV T Junction Temperature °C 150 150 j T Storage Temperature °C -65 to 150 -65 to 150 stg θ Thermal Resistance[2] °C/W 500 150 jc Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. T = +25°C, where T is defined to be the temperature at the package pins where contact is made to the circuit board. C C ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge. 2

Electrical Specifications, T = 25°C, each diode C Package Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Configuration Voltage V (V) R (ý) C (pF) BR S T 3890 G0[1] 0 Single 100 2.5 0.30 3892 G2[1] 2 Series 3893 G3[1] 3 Common Anode 3894 G4[1] 4 Common Cathode 3895 G5[1] 5 Unconnected Pair 389B G0[2] B Single 389C G2[2] C Series 389E G3[2] E Common Anode 389F G4[2] F Common Cathode 389L GL[2] L Unconnected Trio 389R S[2] R Dual Switch Mode 389T Z[2] T Low Inductance Single 389U GU[2] U Series-Shunt Pair 389V GV[2] V High Frequency Series Pair Test Conditions V = V I = 5 mA V = 5 V R BR F R Measure f = 100 MHz f = 1 MHz I 10 µA R Notes: 1. Package marking code is white. 2. Package is laser marked. High Frequency (Low Inductance, 500 MHz–3 GHz) PIN Diodes Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Voltage Resistance Capacitance Capacitance Inductance HSMP- Code[1] Configuration V (V) R (ý) C (pF) C (pF) L (nH) BR S T T T 489x GA Dual Anode 100 2.5 0.33 0.375 1.0 Test Conditions V = V I = 5 mA f = 1 MHz V = 5 V f=500 MHz– R BR F R Measure V = 5V f = 1 MHz 3 GHz R I 10 µA R Note: 1. SOT-23 package marking code is white; SOT-323 is laser marked. Typical Parameters at T = 25°C C Part Number Series Resistance Carrier Lifetime Total Capacitance HSMP- R (ý) τ (ns) C (pF) S T 389x 3.8 200 0.20 @ 5V Test Conditions I = 1 mA I = 10 mA F F f = 100 MHz I = 6 mA R 3

HSMP-389x Series Typical Performance, T = 25°C, each diode C 100 0.55 120 Diode Mounted as a F) 0.50 Bm) 115 S50e rOiehsm A Mtteicnruoasttorirp i na nad MS) E (p 0.45 T (d 110 Tested at 123 MHz H 10 C N O N OI RF RESISTANCE ( 1 TOTAL CAPACITA 0000....43320505 1 MHz PUT INTERCEPT P 1100995050 1 GHz N I 0.1 0.20 85 0.01 0.1 1 10 100 0 4 8 12 16 20 1 10 30 IF – FORWARD BIAS CURRENT (mA) VR – REVERSE VOLTAGE (V) IF – FORWARD BIAS CURRENT (mA) Figure 1. Total RF Resistance at 25 C vs. Figure 2. Capacitance vs. Reverse Figure 3. 2nd Harmonic Input Intercept Forward Bias Current. Voltage. Point vs. Forward Bias Current. 200 100 S) n TIME ( 160 VR = –2V T (mA) 10 Y N R 120 E E R V R O U 1 C C RE 80 RD SE VR = –5V WA R R 0.1 T – REVErr 40010 15 VR = –2100V 25 30 I – FOF0.010 0.2 01.425 C02.65 C 0–.580 C 1.0 1.2 FORWARD CURRENT (mA) VF – FORWARD VOLTAGE (V) Figure 4. Typical Reverse Recovery Time Figure 5. Forward Current vs. Forward vs. Reverse Voltage. Voltage. Typical Applications for Multiple Diode Products 1 2 1 2 2 “ON” 0 +V 3 “OFF” 0 –V 3 2 1 1 3 2 1 1 4 5 6 0 b1 b2 b3 4 5 6 RF in RF out Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation Switch. Figure 6. HSMP-389L used in a SP3T Switch. 4

Typical Applications for Multiple Diode Products (continued) 1 2 “ON” +V 0 “OFF” 0 +V RF out 1 1 6 5 4 6 5 4 1 2 3 RF in RF out 1 2 3 2 RF in Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage, Figure 9. HSMP-389T used in a Low Inductance Shunt High Isolation Switch. Mounted Switch. Bias Ant λ 4 Xmtr C C Rcvr Bias Ant λ Bias 4 Xmtr Rcvr Antenna bias Xmtr PA HSMP-389V λ 4 λ 4 LNA HSMP-389U Rcvr Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz Transmit/Receive Switch. Transmit/Receive Switch. 5

Typical Applications for Multiple Diode Products (continued) RF COMMON RF COMMON RF 1 RF 2 RF 1 RF 2 BIAS 1 BIAS 2 BIAS BIAS Figure 12. Simple SPDT Switch, Using Only Positive Current. Figure 13. High Isolation SPDT Switch, Dual Bias. RF COMMON RF COMMON BIAS RF 1 RF 2 RF 1 RF 2 BIAS Figure 14. Switch Using Both Positive and Negative Bias Current. Figure 15. Very High Isolation SPDT Switch, Dual Bias. 6

Typical Applications for HSMP-489x Low Inductance Series Equivalent Circuit Model Microstrip Series Connection for HSMP-489x Series HSMP-389x Chip* In order to take full advantage of the low inductance Rs Rj of the HSMP-489x series when using them in series ap- plications, both lead 1 and lead 2 should be connected 0.5 Ω together, as shown in Figure 17. C 3 j 0.12 pF* * Measured at -20 V 1 2 RT = 0.5 + Rj HSMP-489x CT = CP + Cj Figure 16. Internal Connections. 20 Figure 16. Internal Connections. Rj = I0.9 Ω I = Forward Bias Current in mA * See AN1124 for package models Co-Planar Waveguide Shunt Connection for HSMP-489x Series Co-Planar waveguide, with ground on the top side of Figure 1F7ig. Cuirrceu it1 L7a.y oCuitr.cuit Layout. the printed circuit board, is shown in Figure 20. Since it eliminates the need for via holes to ground, it offers Microstrip Shunt Connections for HSMP-489x Series lower shunt parasitic inductance and higher maximum In Figure 18, the center conductor of the microstrip line attenuation when compared to a microstrip circuit. is interrupted and leads 1 and 2 of the HSMP-489x diode are placed across the resulting gap. This forces the 1.5 Co-Planar Waveguide nH lead inductance of leads 1 and 2 to appear as part of Groundplane a low pass filter, reducing the shunt parasitic inductance Center Conductor and increasing the maximum available attenuation. The Groundplane 0.3 nH of shunt inductance external to the diode is cre- ated by the via holes, and is a good estimate for 0.032" thick material. 50 OHM MICROSTRIP LINES FigureF 2ig0.u Crirec u2it0 L.a yCoiurtc.uit Layout. 0.3 pF PAD CONNECTED TO GROUND BY TWO 0.75 nH VIA HOLES Figure 18. Circuit Layout. Figure 18. Circuit Layout. Figure 21. Equivalent Circuit. 1.5 nH 1.5 nH Figure 21. Equivalent Circuit. A SPICE model is not available for PIN diodes as SPICE 0.3 pF does not provide for a key PIN diode characteristic, car- rier lifetime. 0.3 nH 0.3 nH Figure 19. Equivalent Circuit. Figure 19. Equivalent Circuit. 7

Assembly Information 0.026 0.075 0.035 0.016 Figure 22. PCB Pad Layout, SOT-363. (dimensions in inches). 0.026 0.07 0.035 0.016 Figure 23. PCB Pad Layout, SOT-323. (dimensions in inches). 0.037 0.037 0.95 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches DIMENSIONS IN mm Figure 24. PCB Pad Layout, SOT-23. SOT-23 Footprint 0.112 2.85 0.079 2 0.033 0.85 0.075 0.041 0.108 1.9 0.071 1.05 2.75 1.8 0.033 0.85 0.047 0.031 0.033 1.2 0.8 0.85 inches DIMENSIONS IN mm Figure 25. PCB Pad Layout, SOT-143. 8

SMT Assembly Reliable assembly of surface mount components is a zones. The preheat zones increase the temperature of complex process that involves many material, process, the board and components to prevent thermal shock and equipment factors, including: method of heating and begin evaporating solvents from the solder paste. (e.g., IR or vapor phase reflow, wave soldering, etc.) cir- The reflow zone briefly elevates the temperature suffi- cuit board material, conductor thickness and pattern, ciently to produce a reflow of the solder. type of solder alloy, and the thermal conductivity and The rates of change of temperature for the ramp-up and thermal mass of components. Components with a low cool-down zones are chosen to be low enough to not mass, such as the SOT package, will reach solder reflow cause deformation of the board or damage to compo- temperatures faster than those with a greater mass. nents due to thermal shock. The maximum temperature Avago Technologies’ diodes have been qualified to the in the reflow zone (T ) should not exceed 260°C. MAX time-temperature profile shown in Figure 26. This profile These parameters are typical for a surface mount assem- is representative of an IR reflow type of surface mount bly process for Avago Technologies diodes. As a general assembly process. guideline, the circuit board and components should be After ramping up from room temperature, the circuit exposed only to the minimum temperatures and times board with components attached to it (held in place necessary to achieve a uniform reflow of solder. with solder paste) passes through one or more preheat tp Tp CriticalZone T toTp Ramp-up L T L e Ts max tL r u t a r e p Ts m min e T ts Ramp-down Preheat 25 t25°CtoPeak Time Figure 26. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (T to Peak) 3°C/ second max S(max) Preheat Temperature Min (T ) 150°C S(min) Temperature Max (T ) 200°C S(max) Time (min to max) (t) 60-180 seconds S Ts(max) to TL Ramp-up Rate 3°C/second max Time maintained above: Temperature (T) 217°C L Time (t) 60-150 seconds L Peak Temperature (T) 260 +0/-5°C P Time within 5 °C of actual Peak temperature (t) 20-40 seconds P Ramp-down Rate 6°C/second max Time 25 °C to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface 9

Package Dimensions Outline 23 (SOT-23) Outline SOT-323 (SC-70 3 Lead) e2 e1 e1 E XXX E1 E XXX E1 e L e L B C D DIMENSIONS(mm) B C SYMBOL MIN. MAX. A 0.80 1.00 D DIMENSIONS(mm) A A1 0.00 0.10 SYMBOL MIN. MAX. B 0.15 0.40 A 0.79 1.20 C 0.08 0.25 A1 0.000 0.100 A1 D 1.80 2.25 A B 0.30 0.54 E1 1.10 1.40 C 0.08 0.20 e 0.65typical A1 D 2.73 3.13 Notes: e1 1.30typical E1 1.15 1.50 XXX-packagemarking E 1.80 2.40 e 0.89 1.02 Drawingsarenottoscale L 0.26 0.46 e1 1.78 2.04 Notes: e2 0.45 0.60 XXX-packagemarking E 2.10 2.70 Drawingsarenottoscale L 0.45 0.69 Outline 143 (SOT-143) Outline SOT-363 (SC-70 6 Lead) e2 e1 HE E B1 L E XXX E1 e c D DIMENSIONS(mm) L SYMBOL MIN. MAX. E 1.15 1.35 e B C D 1.80 2.25 A1 HE 1.80 2.40 A2 A A 0.80 1.10 DIMENSIONS (mm) A2 0.80 1.00 D SYMBOL MIN. MAX. A1 0.00 0.10 A 0.79 1.097 e 0.650BCS A1 0.013 0.10 b b 0.15 0.30 A B 0.36 0.54 c 0.08 0.25 B1 0.76 0.92 L 0.10 0.46 C 0.086 0.152 A1 D 2.80 3.06 E1 1.20 1.40 e 0.89 1.02 e1 1.78 2.04 Notes: e2 0.45 0.60 XXX-package marking E 2.10 2.65 Drawings are not to scale L 0.45 0.69 10

Package Characteristics Lead Material Copper (SOT-323/363); Alloy 42 (SOT-23/143) Lead Finish Tin 100% Maximum Soldering Temperature 260°C for 5 seconds Minimum Lead Strength 2 pounds pull Typical Package Inductance 2 nH Typical Package Capacitance 0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 389x - xxx Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” Device Orientation For Outlines SOT-23, -323 REEL TOP VIEW END VIEW 4 mm CARRIER 8 mm TAPE ABC ABC ABC ABC USER FEED DIRECTION Note: "AB" represents package marking code. COVER TAPE "C" represents date code. For Outline SOT-143 For Outline SOT-363 TOP VIEW END VIEW TOP VIEW END VIEW 4 mm 4 mm 8 mm 8 mm ABC ABC ABC ABC ABC ABC ABC ABC Note: "AB" represents package marking code. Note: "AB" represents package marking code. "C" represents date code. "C" represents date code. 11

Tape Dimensions and Product Orientation For Outline SOT-23 P D P2 E P0 F W t1 D1 9 MAX Ko 8 MAX 13.5 MAX A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH A0 3.15 ± 0.10 0.124 ± 0.004 WIDTH B0 2.77 ± 0.10 0.109 ± 0.004 DEPTH K0 1.22 ± 0.10 0.048 ± 0.004 PITCH P 4.00 ± 0.10 0.157 ± 0.004 BOTTOM HOLE DIAMETER D1 1.00 + 0.05 0.039 ± 0.002 PERFORATION DIAMETER D 1.50 + 0.10 0.059 + 0.004 PITCH P0 4.00 ± 0.10 0.157 ± 0.004 POSITION E 1.75 ± 0.10 0.069 ± 0.004 CARRIER TAPE WIDTH W 8.00 + 0.30 – 0.10 0.315 + 0.012 – 0.004 THICKNESS t1 0.229 ± 0.013 0.009 0.0005 DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002 BETWEEN (WIDTH DIRECTION) CENTERLINE CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002 (LENGTH DIRECTION) For Outline SOT-143 P D P0 P2 E F W D1 t1 9° MAX K0 9° MAX A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH A0 3.19 ± 0.10 0.126 ± 0.004 WIDTH B0 2.80 ± 0.10 0.110 ± 0.004 DEPTH K0 1.31 ± 0.10 0.052 ± 0.004 PITCH P 4.00 ± 0.10 0.157 ± 0.004 BOTTOM HOLE DIAMETER D1 1.00 + 0.25 0.039 + 0.010 PERFORATION DIAMETER D 1.50 + 0.10 0.059 + 0.004 PITCH P0 4.00 ± 0.10 0.157 ± 0.004 POSITION E 1.75 ± 0.10 0.069 ± 0.004 CARRIER TAPE WIDTH W 8.00 + 0.30 – 0.10 0.315+ 0.012 – 0.004 THICKNESS t1 0.254 ± 0.013 0.0100 0.0005 DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002 (WIDTH DIRECTION) CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002 (LENGTH DIRECTION) 12

Tape Dimensions and Product Orientation For Outlines SOT-323, -363 P D P2 P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) An K0 An A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH A0 2.40 ± 0.10 0.094 ± 0.004 WIDTH B0 2.40 ± 0.10 0.094 ± 0.004 DEPTH K0 1.20 ± 0.10 0.047 ± 0.004 PITCH P 4.00 ± 0.10 0.157 ± 0.004 BOTTOM HOLE DIAMETER D1 1.00 + 0.25 0.039 + 0.010 PERFORATION DIAMETER D 1.55 ± 0.05 0.061 ± 0.002 PITCH P0 4.00 ± 0.10 0.157 ± 0.004 POSITION E 1.75 ± 0.10 0.069 ± 0.004 CARRIER TAPE WIDTH W 8.00 ± 0.30 0.315 ± 0.012 THICKNESS t1 0.254 ± 0.02 0.0100 ± 0.0008 COVER TAPE WIDTH C 5.4 ± 0.10 0.205 ± 0.004 TAPE THICKNESS Tt 0.062 ± 0.001 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002 (WIDTH DIRECTION) CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002 (LENGTH DIRECTION) ANGLE FOR SOT-323 (SC70-3 LEAD) An 8°C MAX FOR SOT-363 (SC70-6 LEAD) 10°C MAX For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-0486EN AV02-0813EN - June 2, 2009