HSMP-386x Surface Mount PIN Diodes Data Sheet Description/Applications Features The HSMP-386x series of general purpose PIN diodes are • Unique Configurations in Surface Mount Packages designed for two classes of applications. The first is attenu- – Add Flexibility ators where current consumption is the most important – Save Board Space design consideration. The second application for this – Reduce Cost series of diodes is in switches where low capacitance is the • Switching driving issue for the designer. – Low Distortion Switching The HSMP-386x series Total Capacitance (C ) and Total – Low Capacitance T Resistance (R ) are typical specifications. For applications • Attenuating T that require guaranteed performance, the general purpose – Low Current Attenuating for Less Power HSMP-383x series is recommended. Consumption A SPICE model is not available for PIN diodes as SPICE • Matched Diodes for Consistent Performance does not provide for a key PIN diode characteristic, carrier • Better Thermal Conductivity for Higher Power lifetime. Dissipation Pin Connections and Package Marking, SOT-363 • Low Failure in Time (FIT) Rate[1] • Lead-free Note: 1 6 L 1. For more information see the Surface Mount PIN Reliability Data 2 U 5 Sheet. x 3 4 Notes: 1. Package marking provides orientation, identification, and date code. 2. See “Electrical Specifications” for appropriate package marking.

Package Lead Code Identification, Package Lead Code Identification, Package Lead Code Identification, SOT-23, SOT-143 SOT-323 SOT-363 (Top View) (Top View) (Top View) SINGLE SERIES SINGLE SERIES UNCONNECTED(cid:24) TRIO 6 5 4 #0 #2 B C 1 2 3 COMMON(cid:27) COMMON(cid:27) COMMON(cid:27) COMMON(cid:27) L ANODE CATHODE ANODE CATHODE #3 #4 E F RING QUAD 3 4 1 2 D See separate data sheet HSMP-386D Absolute Maximum Ratings[1] T = +25°C C Symbol Parameter Unit SOT-23 SOT-323 ESD WARNING: Handling Precautions Should Be Taken To Avoid I Forward Current (1 µs Pulse) Amp 1 1 f Static Discharge. P Peak Inverse Voltage V 50 50 IV T Junction Temperature °C 150 150 j T Storage Temperature °C -65 to 150 -65 to 150 stg q Thermal Resistance[2] °C/W 500 150 jc Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. T = +25°C, where T is defined to be the temperature at the package pins where contact is made to C C the circuit board. Electrical Specifications T = 25°C, each diode C PIN General Purpose Diodes, Typical Specifications T = 25°C A Package Minimum Typical Typical Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Configuration Voltage V (V) R (Ω) C (pF) BR S T 3860 L0 0 Single 50 3.0/1.5* 0.20 3862 L2 2 Series 3863 L3 3 Common Anode 3864 L4 4 Common Cathode 386B L0 B Single 386C L2 C Series 386E L3 E Common Anode 386F L4 F Common Cathode 386L LL L Unconnected Trio Test Conditions V = V I = 10 mA V = 50 V R BR F R Measure f = 100 MHz f = 1 MHz I ≤ 10 µA I = 100 mA* R F 2

HSMP-386x Typical Parameters at T = 25°C C Part Number Total Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance HSMP- R (Ω) t (ns) T (ns) C (pF) T rr T 386x 22 500 80 0.20 Test Conditions I = 1 mA I = 50 mA V = 10 V V = 50 V F F R R f = 100 MHz T = 250 mA I = 20 mA f = 1 MHz R F 90% Recovery Typical Performance, T = 25°C, each diode C 0.35 1000 120 OTAL CAPACITANCE (pF)000...322050 110 G0 H1M zMHzHz RESISTANCE (OHMS) 11000 TTTAAA === ++–825555 CCC UT INTERCEPT POINT (dBm) 11111100950505 DS5Te0eios r dit eMeesd i Mc Sarowto u1sitn2tcr3tihep Md ian Han aszd a T NP 90 I 0.15 1 85 0 2 4 6 8 10 12 14 16 18 20 0.01 0.1 1 10 100 1 10 30 REVERSE VOLTAGE (V) BIAS CURRENT (mA) IF – FORWARD BIAS CURRENT (mA) Figure 1. RF Capacitance vs. Reverse Bias. Figure 2. Typical RF Resistance vs. Forward Bias Figure 3. 2nd Harmonic Input Intercept Point Current. vs. Forward Bias Current for Switch Diodes. s)1000 100 ME (n mA) VERY TI VR = 5V RRENT ( 10 O U EC 100 VR = 10V D C 1 R R E A RS VR = 20V RW T – REVErr 10 I – FOF00.0.11 125 C 25 C –50 C 10 20 30 0 0.2 0.4 0.6 0.8 1.0 1.2 FORWARD CURRENT (mA) VF – FORWARD VOLTAGE (mA) Figure 4. Reverse Recovery Time vs. Forward Figure 5. Forward Current vs. Forward Current for Various Reverse Voltages. Voltage. Equivalent Circuit Model HSMP-386x Chip* R R s j R = 1.5 + R T j(cid:18) 1.5 Ω CT = CP + Cj 12 (cid:18) R = Ω C j I0.9 j (cid:18) I = Forward Bias Current in mA(cid:18) � * See AN1124 for package models 0.12 pF (cid:18) 3

Typical Applications for Multiple Diode Products RF COMMON RF COMMON RF 1 RF 2 RF 1 RF 2 BIAS 1 BIAS 2 BIAS BIAS Figure 6. Simple SPDT Switch, Using Only Positive Current. Figure 7. High Isolation SPDT Switch, Dual Bias. RF COMMON RF COMMON BIAS RF 1 RF 2 RF 1 RF 2 BIAS Figure 8. Switch Using Both Positive and Negative Current. Figure 9. Very High Isolation SPDT Switch, Dual Bias. VARIABLE BIAS INPUT RF IN/OUT FIXED BIAS VOLTAGE Figure 10. Four Diode p Attenuator. See AN1048 for details. Figure 10. Four Diode π Attenuator. See AN1048 for details. 4

Typical Applications for Multiple Diode Products (continued) BIAS (cid:22) 1(cid:22) 2(cid:22) “ON”(cid:22) +V(cid:22) 0(cid:22) “OFF” 0 +V 1 1 6 5 4 1 2 3 RF in RF out 2 Figure 11. High Isolation SPST Switch Figure 11. High Isolation SPST Switch Figure 12. HSMP-386L Unconnected Trio used in a Positive Voltage, (Repeat Cells as Required). (Repeat Cells as Required). High Isolation Switch. 1 2 3 3 2 1 2 (cid:17) 1(cid:17) 2(cid:17) “ON”(cid:17) 0(cid:17) +V(cid:17) “OFF” 0 –V 4 5 6 0 1 3 2 1 1 b1 b2 b3 4 5 6 RF in RF out Figure 13. HSMP-386L used in a SP3T Switch. Figure 14. HSMP-386L Unconnected Trio used in a Dual Voltage, High Isolation Switch. 5

Ordering Information Specify part number followed by option. For example: HSMP - 386x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” Assembly Information 0.026 SOT-323 PCB Footprint Recommended PCB pad layouts for the miniature SOT packages are shown in Figures 15, 16, 17. These layouts provide ample allowance for package placement by 0.079 automated assembly equipment without adding parasitics that could impair the performance. 0.039 0.026 0.018 Dimensions in inches 0.079 Figure 16. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363 Products. 0.039 0.039 0.039 1 1 0.022 Dimensions in inches 0.079 2.0 Figure 15. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products. 0.035 0.9 0.031 0.8 inches Dimensions in mm Figure 17. Recommended PCB Pad Layout for Avago’s SOT-23 Products. 6

SMT Assembly Reliable assembly of surface mount components is a preheat zones increase the temperature of the board and complex process that involves many material, process, and components to prevent thermal shock and begin evapo- equipment factors, including: method of heating (e.g., IR rating solvents from the solder paste. The reflow zone or vapor phase reflow, wave soldering, etc.) circuit board briefly elevates the temperature sufficiently to produce a material, conductor thickness and pattern, type of solder reflow of the solder. alloy, and the thermal conductivity and thermal mass of The rates of change of temperature for the ramp-up and components. Components with a low mass, such as the SOT cool-down zones are chosen to be low enough to not cause package, will reach solder reflow temperatures faster than deformation of the board or damage to components due those with a greater mass. to thermal shock. The maximum temperature in the reflow Avago’s diodes have been qualified to the time-temper- zone (T ) should not exceed 260°C. MAX ature profile shown in Figure 18. This profile is represen- These parameters are typical for a surface mount assembly tative of an IR reflow type of surface mount assembly process for Avago diodes. As a general guideline, the circuit process. board and components should be exposed only to the After ramping up from room temperature, the circuit board minimum temperatures and times necessary to achieve a with components attached to it (held in place with solder uniform reflow of solder. paste) passes through one or more preheat zones. The tp Tp Critical Zone T to Tp Ramp-up L T L e Ts max tL r u t a r e p Ts m min e T ts Ramp-down Preheat 25 t 25° C to Peak Time Figure 18. Surface Mount Assembly Profile. Lead-Free Reflow Profile Recommendation (IPC/JEDEC J-STD-020C) Reflow Parameter Lead-Free Assembly Average ramp-up rate (Liquidus Temperature (T to Peak) 3°C/ second max S(max) Preheat Temperature Min (T ) 150°C S(min) Temperature Max (T ) 200°C S(max) Time (min to max) (t) 60-180 seconds S Ts(max) to TL Ramp-up Rate 3°C/second max Time maintained above: Temperature (T) 217°C L Time (t) 60-150 seconds L Peak Temperature (T) 260 +0/-5°C P Time within 5 °C of actual Peak temperature (t) 20-40 seconds P Ramp-down Rate 6°C/second max Time 25 °C to Peak Temperature 8 minutes max Note 1: All temperatures refer to topside of the package, measured on the package body surface 7

Package Dimensions Outline 23 (SOT-23) Outline SOT-323 (SC-70, 3 Lead) e2 e1 e1 E XXX E1 E XXX E1 e L e L B C D DIMENSIONS (mm) B C SYMBOL MIN. MAX. A 0.80 1.00 D DIMENSIONS (mm) A A1 0.00 0.10 SYMBOL MIN. MAX. B 0.15 0.40 A 0.79 1.20 C 0.08 0.25 A1 0.000 0.100 A1 D 1.80 2.25 A B 0.30 0.54 E1 1.10 1.40 C 0.08 0.20 e 0.65 typical A1 D 2.73 3.13 Notes: e1 1.30 typical E1 1.15 1.50 XXX-package marking E 1.80 2.40 e 0.89 1.02 Drawings are not to scale L 0.26 0.46 e1 1.78 2.04 Notes: e2 0.45 0.60 XXX-package marking E 2.10 2.70 Drawings are not to scale L 0.45 0.69 Outline 363 (SC-70, 6 Lead) HE E L e c D DIMENSIONS (mm) SYMBOL MIN. MAX. E 1.15 1.35 D 1.80 2.25 A1 HE 1.80 2.40 A2 A A 0.80 1.10 A2 0.80 1.00 A1 0.00 0.10 e 0.650 BCS b b 0.15 0.30 c 0.08 0.25 L 0.10 0.46 Package Characteristics Lead Material ...........................................Copper (SOT-323/363); Alloy 42 (SOT-23) Lead Finish .........................................................................Tin 100% (Lead-free option) Maximum Soldering Temperature ............................................260°C for 5 seconds Minimum Lead Strength ...........................................................................2 pounds pull Typical Package Inductance ......................................................................................2 nH Typical Package Capacitance ..............................................0.08 pF (opposite leads) 8

Device Orientation REEL CARRIER TAPE USER FEED DIRECTION COVER TAPE For Outlines SOT-23, -323 For Outline SOT-363 TOP VIEW END VIEW TOP VIEW END VIEW 4 mm 4 mm 8 mm 8 mm ABC ABC ABC ABC ABC ABC ABC ABC Note: "AB" represents package marking code. Note: "AB" represents package marking code. "C" represents date code. "C" represents date code. Tape Dimensions and Product Orientation For Outline SOT-23 P D P2 E P0 F W t1 D1 9(cid:30) MAX Ko 8(cid:30) MAX 13.5(cid:30) MAX A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH A0 3.15 ± 0.10 0.124 ± 0.004 WIDTH B0 2.77 ± 0.10 0.109 ± 0.004 DEPTH K0 1.22 ± 0.10 0.048 ± 0.004 PITCH P 4.00 ± 0.10 0.157 ± 0.004 BOTTOM HOLE DIAMETER D1 1.00 + 0.05 0.039 ± 0.002 PERFORATION DIAMETER D 1.50 + 0.10 0.059 + 0.004 PITCH P0 4.00 ± 0.10 0.157 ± 0.004 POSITION E 1.75 ± 0.10 0.069 ± 0.004 CARRIER TAPE WIDTH W 8.00 + 0.30 - 0.10 0.315 + 0.012 - 0.004 THICKNESS t1 0.229 ± 0.013 0.009 ± 0.0005 DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002 BETWEEN (WIDTH DIRECTION) CENTERLINE CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002 (LENGTH DIRECTION) 9

Tape Dimensions and Product Orientation For Outlines SOT-323, -363 P D P2 P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) An K0 An A0 B0 DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH A0 2.40 ± 0.10 0.0(cid:144)4 ± 0.004 WIDTH B0 2.40 ± 0.10 0.0(cid:144)4 ± 0.004 DEPTH K0 1.20 ± 0.10 0.04(cid:144) ±(cid:144) 0.004 PITCH P 4.00 ± 0.10 0.15(cid:144) ± 0.004 BOTTOM HOLE DIAMETER D1 1.00 + 0.25 0.0(cid:144)(cid:144) + 0.010 PERFORATION DIAMETER D 1.55 ± 0.05 0.0(cid:144)1 ± 0.002 PITCH P0 4.00 ± 0.10 0.15(cid:144) ± 0.004 POSITION E 1.(cid:144)5 ± 0.10 0.0(cid:144)(cid:144) ± 0.004 CARRIER TAPE WIDTH W (cid:144).00 ± 0.(cid:144)0 0.(cid:144)15 ± 0.012 THICKNESS t1 0.254 ± 0.02 0.0100 ± 0.000(cid:144) COVER TAPE WIDTH C 5.4 ± 0.10 0.205 ± 0.004 TAPE THICKNESS Tt 0.0(cid:144)2 ± 0.001 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION F (cid:144).50 ± 0.05 0.1(cid:144)(cid:144) ± 0.002 (WIDTH DIRECTION) CAVITY TO PERFORATION P2 2.00 ± 0.05 0.0(cid:144)(cid:144) ± 0.002 (LENGTH DIRECTION) ANGLE FOR SOT(cid:144)(cid:144)2(cid:144) (SC(cid:144)0(cid:144)(cid:144) LEAD) An (cid:144)°C MA(cid:144) FOR SOT(cid:144)(cid:144)(cid:144)(cid:144) (SC(cid:144)0(cid:144)(cid:144) LEAD) 10°C MA(cid:144) For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-4028EN AV02-0293EN - October 21, 2013