HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Typical Applications Features The HMC1023LP5E is ideal for: Low Noise Figure: 10 dB • Baseband filtering before or after data converters High linearity: T for point-to-point fixed wireless and cellular In-Band Output IP3 > +30 dBm M infrastructure transceivers In-Band Output IP2 > +60 dBm S Pre-programmed and/or Programmable Bandwidth: • Software defined radio applications 5 MHz to 72 MHz. (Please see HMC1023LP5E - • Anti-aliasing and reconstruction filters Ordering Information) G • Test and measurement equipment Exceptional 3 dB Bandwidth Accuracy: ±2.5% N • ADC driver applications Programmable Gain: 0 or 10 dB I S Integrated ADC Driver Amplifier S 6th order Butterworth Magnitude & Phase Response E Automatic Filter Calibration C Externally Controlled Common Mode Output Level O Filter Bypass Option R Pin & Register Compatible to HMC900LP5E P Read/Write Serial Port Interface (SPI) D 32 Lead 5x5 mm SMT Package 25 mm2 N A Functional Diagram General Description B The HMC1023LP5E is a 6th order, programmable E bandwidth, fully calibrated, dual low pass filter. It S features programmable 0 or 10 dB gain and supports A arbitrary bandwidths from 5 MHz to 72 MHz. When B calibrated, the bandwidth is accurate to +/-2.5%. Built- in filter bypass option enables wider bandwidths while / maintaining programmed gain and common mode F control settings. I Integrated ADC driver, programmable input impedance, and adjustable output common mode voltage from 0.9 V to 3 V with 2 Vppd signal, or lower than 0.9 V common mode with lower signal swing enables simple interface while achieving maximum performance. Programmable bias settings enable performance/power dissipation trade-off optimized for each application. Filter calibration is accomplished with any reference clock rate from 20 to 80 MHz. One time programmable (OTP) memory offers unsurpassed flexibility allowing the user “set and forget” parameters like gain and bandwidth setting. Housed in a compact 5x5 mm SMT QFN package, the HMC1023LP5E is pin and register compatible to the existing HMC900LP5E programmable bandwidth Low Pass Filter. It requires minimal external components and provides a low cost alternative to more complicated switched discrete filter architectures. The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 1 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 1. Electrical Specifications T = +25°C, VDDI, VDDQ, VDDCAL, VDDBG, DVDD = 5V +/-5%, GND = 0V, 400 Ω load unless otherwise stated. A Parameter Conditions Min. Typ. Max. Units T M Analog Performance min gain setting 0 dB S Passband Gain [1] max gain setting 10 dB - 3 dB corner frequency (fc) [1] 5 72 MHz G Programmable to any frequency in this range Bypass mode 75 100 MHz uncalibrated ± 20 % N 3 dB corner frequency variation calibrated ±2.5 ± 3.5 % I S 3 dB corner frequency variation vs temperature over -40°C to +85°C ±0.03 % / °C S Max passband gain error[2] vs ideal 6th order LPF H(s) ±0.5 dB E Max passband group delay variation at 0.1 dB BW (~0.73 fc) 0.250 C (group delay * 3 dB frequency fc ) at 0.5 dB BW (~0.83 fc) 0.350 O e.g. for 1.0 dB BW of 40 MHz (fc ~ 44.9 MHz): at 1.0 dB BW (~ 0.89 fc) 0.400 max group delay variation = 0.400/ 44.9 MHz = 8.9 ns R at 3.0 dB BW (at fc) 0.400 P min gain, fc = 5 MHz 22 nV/rtHz min gain, fc = 28 MHz 22 nV/rtHz D Output Noise (f = 1 MHz) max gain fc = 5 MHz 25 nV/rtHz N max gain, fc = 28 MHz 25 nV/rtHz A min gain, fc = 5 MHz 8 nV/rtHz B max gain, fc = 5 MHz 8 nV/rtHz Output noise (f > 10*fc) E min gain fc = 28 MHz 8 nV/rtHz S max gain, fc = 28 MHz 8 nV/rtHz A min gain 25 dB Noise Figure (100 Ω source) B max gain 17 dB min gain 19 dB / Noise Figure (1 kΩ source) max gain 12 dB F half scale tones at 0.8fc and I 0.6fc Input referred Passband IM3 fc = 20 MHz -60 dBc fc = 72 MHz[2] -50 dBc half scale tones at 1.2fc and 1.6fc. IM3 product at 0.8fc Input referred Out of Band IM3 fc = 20 MHz -60 dBc fc = 72 MHz [2] -50 dBc half scale tones at 2fc and 3fc. IM3 product at 0.5fc Input referred Out of Band IM3 fc = 20 MHz -50 dBc fc = 72 MHz [2] -45 dBc half scale tones at 0.8fc and 0.6fc Output IP3 (inband) fc = 20 MHz 25 30 dBm fc = 72 MHz 17 20 dBm half scale tones at 1.2fc and 1.6fc. IM3 product at 0.8fc Output IP3 (out of band) fc = 20 MHz 25 30 dBm fc = 72 MHz [2] 17 20 dBm half scale tones at 2fc and 3fc. IM3 product at fc Output IP3 (out of band) fc = 20 MHz 25 30 dBm fc = 72 MHz[2] 17 20 dBm half scale tones at 0.8fc and 0.6fc IM2 product at 0.2fc Output IP2 (inband) fc = 20 MHz 55 60 dBm fc = 72 MHz [2] 55 60 dBm InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 2 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Electrical Specifications, TA = +25°C (Continued) Parameter Conditions Min. Typ. Max. Units half scale tones at 1.2fc and Output IP2 (out of band)[2] 60 65 dBm 1.6fc. IM2 product at 0.4fc T complex signal measured at M Sideband Suppression (Uncalibrated) 35 45 dB 0.8fc vs -0.8fc S I/Q Channel Balance magnitude 0.04 dB - phase 0.5 o G I/Q Channel Isolation 60 80 dB N Analog I/O I S 1000 / Differential Input Impedance Programmable Ω S 400 / 100 E Full Scale Differential Input min gain 2 Vppd (400 Ω Differential Load) max gain 0.613 Vppd C Full Scale Differential Input min gain 0.5 Vppd O (100 Ω Differential Load) max gain 0.156 Vppd R Input Common Mode Voltage Range 1 4 V P Full Scale Differential Output 400 Ω Differential Load 2 Vppd D Full Scale Differential Output 100 Ω Differential Load 0.5 Vppd N Output Voltage Range 0.5 Vdd-0.5 V A Output Common Mode Voltage Range 0.9 3 V B Digital I/O E Use doubler mode for clocks S CALCK Frequency 20 40 80 MHz between 20 MHz and 40 MHz A CALCK Duty Cycle 40 50 60 % B SCLK Frequency 20 30 MHz / Digital Input Low Level (VIL) 0.4 V F Digital Input High Level (VIH) 1.5 V I Digital Output Low Level (VOL) 0.4 V Digital Output High Level (VOH) Vdd - 0.4 Power Supply Analog & Digital Supplies 4.75 5 5.25 V Supply Current Dependent on Bias 240 mA Power on Reset 250 us [1] The attenuation of the filter transfer function can be calculated directly at any frequency f as: attenuation = 10*log (1+(f/f )^(2*6)), where f 10 0 0 is the 3 dB bandwidth or corner frequency for the filter. Similarly, for a given maximum attenuation and 3 dB bandwidth, f , the frequency 0 at which the attenuation is achieved can be calculated as: f=(10^(attenuation/10) -1)^(1/(2*6)) * f . Note that for a 6th order Butterworth filter the 0 1 dB bandwidth is at ~89% of the filter bandwidth and 0.5 dB bandwidth is at 84% of the filter bandwidth. [2] Specified distortion is measured with opamp_bias (Reg 02h[1:0]) settings recommended in Table 9. . Table 2. Test Conditions Unless otherwise specified, the following test conditions were used Parameter Condition Temperature +25 °C Reg 06h Setting 150 Gain Setting 0 dB bias settings (opamp_bias Reg 02h[1:0]/ drvr_bias Reg 02h[3:2]) 00/10 Input Signal Level 2 Vppd Input/Output Common Mode Level 2V Output Load 200 Ω / Output Supply Analog: +5V, Digital +5V InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 3 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 1. Filter Attenuation (all Bandwidths) [1] Figure 2. Filter Passband Gain Response 20 0.3 0 0.2 T 5 MHz 0.1 M N (dB) -20 72 MHz N (dB) 0 S FILTER GAI --6400 FILTER GAI --00..21 G - 5 MHz -0.3 72 MHz N -80 -0.4 I S -100 -0.5 0.1 1 10 100 1000 0.1 1 10 100 1000 S FREQUENCY (MHz) FREQUENCY (MHz) E 5 MHz 28 MHz 5 MHz 28 MHz 7 MHz 40 MHz 7 MHz 40 MHz C 10 MHz 50 MHz 10 MHz 50 MHz 1240 MMHHzz 7B2y pMaHssz 1240 MMHHzz 72 MHz O R Figure 4. Filter 3 dB Cutoff vs P Figure 3. Filter Attenuation, 10dB Gain [1] Temperature, 10 MHz Bandwidth D 20 5 N 0 A FILTER GAIN (dB) ---642000 5 MHz 72 MHz FILTER GAIN (dB) -05 -3 dB ASEB B -80 / -100 -10 F 0.1 1 FREQUE1N0CY (MHz) 100 1000 5 6 7 8 9 10 20 I FREQUENCY (MHz) 5 MHz 28 MHz 7 MHz 40 MHz -40 C 25 C 85 C 10 MHz 50 MHz 14 MHz 72 MHz 20 MHz Bypass Figure 5. Noise Figure, 100 Ω Source Figure 6. Noise Figure, 1 kΩ Source Impedance, 1 kΩ Impedance Selected [2] Impedance, 1 kΩ Impedance Selected [2] 26 24 24 20 22 0 dB Gain NOISE FIGURE (dB)112680 100 d dBB G Gaainin NOISE FIGURE (dB)1126 10 dB Gain 14 12 8 5 7 10 14 20 28 40 50 72 5 7 10 14 20 28 40 50 72 FILTER BANDWIDTH (MHz) FILTER BANDWIDTH (MHz) -40 C +25 C +85 C [1] Degrated stop-band rejection at frequencies > 100 MHz caused by the test fixture. [2] 1 kΩ input impedance into the HMC1023LP5E selected by writing Reg 02h[10]=0 and Reg 01h[9] = 0. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 4 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 7. Noise Figure, 1 kΩ Source Impedance, 100 Ω Impedance Selected Figure 8. Filter Output Noise [3] 30 100 T 28 NG - SM NOISE FIGURE (dB)222246 01 d0B d BG aGinain OUTPUT NOISE (nV/rtHz)10 72 MHz 20 I 5 MHz S 18 S 5 7 10 14 20 28 40 50 72 0.001 0.01 0.1 1 10 100 FILTER BANDWIDTH (MHz) FREQUENCY (MHz) E -40 C +25 C +85 C 5 MHz 28 MHz C 7 MHz 40 MHz 10 MHz 50 MHz 14 MHz 72 MHz O 20 MHz R Figure 9. Uncalibrated Figure 10. Uncalibrated Sideband Rejection, P Sideband Rejection, 0 dB Gain 10 dB Gain D 60 60 N A Bc) 55 Bc) 55 B ON (d 50 ON (d 50 E CTI CTI E E S REJ 45 REJ 45 D D A BAN 40 BAN 40 E E B SIB Internal Input Impedance Setting SIB Internal Input Impedance Setting 35 35 / F 30 30 I 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 FILTER BANDWIDTH (MHz) FILTER BANDWIDTH (MHz) 1000 W 400 W 100 W 1000 W 400 W 100 W Figure 11. Arbitrary Bandwidth Setting 3 Figure 12. Output IP3, dB Cutoff Frequency Error [5] 72 MHz Bandwidth Setting, 0 dB Gain [6] 4 50 R (%) 3 Opamp Bias = 00 Opamp Bias = 01 O Opamp Bias = 10 40 RR 2 UENCY E 1 P3 (dBm) 30 OFF FREQ -01 OUTPUT I 20 UT -2 B C 10 3 d -3 -4 0 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 ARBITRARY FILTER BANDWIDTH (MHz) FREQUENCY (MHz) Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 01 [3] 100 Ω source impedance used, and input impedanceo of HMC1023LP5E set to 1 kΩ [4] 100 Ω input impedance into the HMC1023LP5E selected by writing Reg 02h[10]=1. [5] Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9. [6] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 5 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 13. Output IP2, Figure 14. Output IP3, 72 MHz Bandwidth Setting, 0 dB Gain [7] Filter Bypass Enabled, 0 dB Gain [7] 90 50 T 80 40 M m) m) OUTPUT IP2 (dB 6700 OUTPUT IP3 (dB 2300 G - S 50 10 N I S 40 0 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 80 90 S FREQUENCY (MHz) FREQUENCY (MHz) E RReegg0022hh[[11::00]] == 0001 Reg02h[1:0] = 10 RReegg0022hh[[11::00]] ==0 001 Reg02h[1:0] = 10 C O R Figure 15. Output IP2, Figure 16. Output IP3, P Filter Bypass Mode Enabled, 0 dB Gain [7] Filter Bypass Enabled, 10 dB Gain [7] D 90 50 N 80 40 A m) m) B B B P2 (d 70 P3 (d 30 E UT I UT I S UTP 60 UTP 20 A O O B 50 10 / 40 0 F 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 I FREQUENCY (MHz) FREQUENCY (MHz) Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 01 Reg02h[1:0] = 01 Figure 17. Output IP2, Filter Bypass Figure 18. Output IP3 vs Output Common Enabled, 10 dB Gain [7] Mode Voltage, 30 MHz Input [8] 90 50 80 40 m) m) B B P2 (d 70 P3 (d 30 UT I UT I UTP 60 UTP 20 O O 50 10 40 0 0 10 20 30 40 50 60 70 80 90 0 1 2 3 4 5 FREQUENCY (MHz) COMMON MODE VOLTAGE (V) Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 01 Reg02h[1:0] = 01 [7] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB. [8] 72 MHz Filter Bandwidth Selected. OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 6 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 19. Output IP2 vs Output Common Figure 20. Output IP3 vs Output Common Mode Voltage, 30 MHz Input [9] Mode Voltage, 50 MHz Input [9] 80 50 T M 70 40 m) m) - S UT IP2 (dB 60 UT IP3 (dB 30 G UTP 50 UTP 20 O O N 40 10 I S 30 0 S 0 1 2 3 4 5 0 1 2 3 4 5 E COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) C Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 00 Reg02h[1:0] = 10 Reg02h[1:0] = 01 Reg02h[1:0] = 01 O R Figure 21. Output IP2 vs Output Common Figure 22. Output IP3 vs Output Common P Mode Voltage, 50 MHz Input [9] Mode Voltage, 70 MHz Input [9] D 80 50 N 70 40 A ASEB OUTPUT IP2 (dBm) 5600 OUTPUT IP3 (dBm) 2300 B 40 10 / 30 0 F 0 1 2 3 4 5 0 1 2 3 4 5 I COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V) RReegg0022hh[[11::00]] == 0001 Reg02h[1:0] = 10 RReegg0022hh[[11::00]] == 0001 Reg02h[1:0] = 10 Figure 23. Output IP2 vs Output Common Mode Figure 24. In-band Output IP3 & Output IP2 Voltage, 70 MHz Input [9] vs Filter Bandwidth & Impedance [10] 80 80 90 70 70 OUTPUT IP2 80 Internal Input OUTPUT IP2 (dBm) 5600 OUTPUT IP3 (dBm) 456000 Impedance Setting 567000 OUTPUT IP2 (dBm ) 40 30 40 OUTPUT IP3 30 20 30 0 1 2 3 4 5 5 7 10 14 20 28 40 50 72 COMMON MODE VOLTAGE (V) FILTER BANDWIDTH (MHz) Reg02h[1:0] = 00 Reg02h[1:0] = 10 1000 W 400 W 100 W Reg02h[1:0] = 01 [9] 72 MHz Filter Bandwidth selected. OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB [10] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 7 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Figure 25. In-band Output IP3 & Output IP2 Figure 26. 5 MHz Bandwidth Filter vs Bandwidth & Temperature [11] Magnitude and Group Delay 80 90 5 150 70 OUTPUT IP2 80 Gain NOR T OUTPUT IP3 (dBm) 456000 567000 OUTPUT IP2 (dBm GAIN (dB) -05 075 MALIZED GROUP DE G - SM 30 40 ) -10 Group Delay -75LAY (ns) N OUTPUT IP3 I 20 30 -15 -150 S 5 7 10 14 20 28 40 50 72 0.1 1 10 S FILTER BANDWIDTH (MHz) FREQUENCY (MHz) E -40 C +25 C +85 C C O Figure 27. 72 MHz Bandwidth Filter Figure 28. HMC1023LP5E Filter I/Q R P Magnitude and Group Delay Channel Isolation D 5 20 20 20 N GAIN (dB) -1-005 GrouGpa Dinelay -01100NORMALIZED GROUP DELAY (ns) S21 (dBc)----864200000 S21 ISOLATION ----086420000I/Q FILTER ISOLATION (dBc) / BASEBA -15 -20 -100 -100 F 1 10 100 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) I 72 MHz Bandwidth Filter Bypassed Figure 29. Input Impedance Figure 30. Output Impedance 1000 200 Reg02h[1:0] = 10 800 150 INPUT IMPEDANCE ()W 246000000 Internal Input Impedance Setting UTPUT IMPEDANCE ()W105000 Reg02h[712:0 M] =H 0z 1BanRdwegid0th2 hS[1e:t0ti]n =g 00 O Filter Bypassed -50 0 -100 1 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) 1000 W 400 W 100 W [11] OIP3 and OIP2 measured from 100 Ω differential source into 400 Ω differential load. Used recommended OpAmp bias settings (Reg 02h[1:0]) in Table 9. OIP3 and OIP2 measurements can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 8 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 3. Absolute Maximum Ratings Nominal 5V Supply to GND Stresses above those listed under Absolute Maximum Ratings may VDDCAL, VDDI, VDDQ, VDDBG, -0.3 to 5.5 V cause permanent damage to the device. This is a stress rating only; T DVDD functional operation of the device at these or any other conditions M above those indicated in the operational section of this specification Common Mode Inputs Pins -0.3 to 5.5 V is not implied. Exposure to absolute maximum rating conditions for S (CMI, CMQ) extended periods may affect device reliability. Input and Output Pins - IIP, IIN, IQP, IQN, OIP, OIN, OQP, -0.3 to 5.5 V G OQN ELECTROSTATIC SENSITIVE DEVICE N Digital Pins OBSERVE HANDLING PRECAUTIONS I SEN, SDI, SCK, SDO, CALCK -0.3 to 5.5 V S SDO min load impedance 1 kΩ S Operating Ambient Temperature -40 to +85 °C E Range C Storage Temperature -65 to + 150 °C O Maximum Junction Temperature 150 °C R Thermal Resistance (ѲJC) 10 °C/W P (junction to ground paddle) Reflow Soldering D Peak Temperature 260 °C N Time at Peak Temperature 40 µs A ESD Sensitivity (HBM) 1 kV Class 1C B E S Table 4. Recommended Operating Conditions A B Parameter Condition Min. Typ. Max. Units Temperature / F Junction Temperature 125 °C I Ambient Temperature -40 85 °C Supply Voltage VDDCAL, VDDI, VDDQ, VDDBG,DVDD 4.75 5 5.25 V [1] Layout design guidelines set out in Qualification Test Report are strongly recommended. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 9 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Outline Drawing T M S - G N I S S E C O R P NOTES: D [1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. N [2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. [3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN. A [4] DIMENSIONS ARE IN INCHES [MILLIMETERS]. B [5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE. [6] PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL E BE 0.25m MAX. [7] PACKAGE WARP SHALL NOT EXCEED 0.05mm S [8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO A PCB RF GOUND. [9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND B PATTERN. / Table 5. Package Information F I Part Number Package Body Material Lead Finish MSL Rating [1] Package Marking [2] H1023 HMC1023LP5E RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn MSL1 XXXX [1] Max peak reflow temperature of 260 °C [2] 4-Digit lot number XXXX InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 10 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 6. Pin Descriptions Pin Number Function Description Interface Schematic T The pins are not connected internally; however, all data 1, 3, 8 - 10, N/C shown herein was measured with these pins connected to M 17, 24, 25, 32 RF/DC ground externally. S Quadrature (Q) Channel 5V Supply. 2, 4 VDDQ Must be locally decoupled to GND - G N 5 CMQ Quadrature (Q) channel output common mode level I S S E C O R 6, 7 OQP, OQN Quadrature (Q) channel positive and negative differential outputs P D N A B E 11 CALCK Calibration clock input S A B / F I 12, 14, 15 SCK, SDI, SEN SPI Data clock, data input and enable respectively. 13 SDO SPI Data Output 16 DVDD Digital 5V Supply. Must be locally decoupled to GND. Inphase (I) channel negative and positive differential 18, 19 OIN, OIP outputs respectively InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 11 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 6. Pin Descriptions (Continued) Pin Number Function Description Interface Schematic T M 20 CMI Inphase (I) channel output common mode level S - G 21, 23 VDDi Inphase (I) Channel 5V Supply. Must be locally decoupled N to GND I S 22 VDDCAL Calibration 5V Supply. Must be locally decoupled to GND S E C 26, 27 IIP, IIN Inphase (I) channel positive and negative differential O inputs respectively R P D 28 VDDBG Bias 5V Supply. Must be locally decoupled to GND. N A B E 29 VBG 1.2V Bandgap output (testing only) S A B / F I Quadrature (Q) channel negative and positive differential 30, 31 IQN, IQP inputs respectively InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 12 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Evaluation PCB T M S - G N I S S E C O R P D N A B E S A B / F The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 I Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. Table 7. Evaluation Order Information Item Contents Part Number HMC1023LP5E Evaluation PCB USB Interface Board Evaluation Kit EKIT01-HMC1023LP5E 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software) InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 13 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Evaluation PCB Schematic To view Evaluation PCB Schematic please visit www.hittite.com and choose HMC1023LP5E from the “Search by Part Number” pull down menu to view the product splash page. T M S Evaluation Setup - G N I S S E C O R P D N A B E S A B / F I Figure 31. Characterization Setup Block Diagram InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 14 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER HMC1023LP5E Usage Information The HMC1023LP5E addresses different filter applications such as fixed frequency or variable bandwidth implementations dependent on the part selected (see HMC1023LP5E Ordering Information) and the control T provided to the HMC1023LP5E. These modes provide the user with different filter options depending on the system M implementation. S An overview of these trade-offs are shown below. - Table 8. HMC1023LP5E Modes of Operation G Unprogrammed Pre-programmed SPI CALCK N Function Comments HMC1023LP5E-00000 HMC1023LP5E-BBBGL Req’d Req’d I S Fixed Bandwidth Filter Yes Yes S Default Bandwidth Bandwidth and Default Bandwidth and Gain Pre-programmed gain and bandwidth E setting after Power On Reset and Gain as defined Gain as defined by are defined when ordering the part. See by register defaults. pre-programming at No No C (POR) HMC1023LP5E Ordering Information. (5 MHz /0dB gain) factory. O Typical Corner Frequency Ac- Accuracy is with respect to bandwidth +/- 20 % +/- 2.5 % R curacy at Default Bandwidth after POR. P Full control over HMC1023LP5E requires Variable Bandwidth Filter Yes Yes access via the digital serial port (SPI). D Default Bandwidth Bandwidth and Default Bandwidth and Gain Pre-programmed gain and bandwidth N and Gain as defined Gain as defined by setting after Power On Reset are defined when ordering the part. See A (POR) by register defaults. pre-programming at HMC1023LP5E Ordering Information. (5 MHz /0dB gain) factory. B Typical Corner Frequency Ac- Yes No Accuracy is with respect to bandwidth E +/- 20 % +/- 2.5 % curacy at Default Bandwidth after POR. S Accuracy is with respect to the desired A Typical Corner Frequency bandwidth. B Accuracy at all other Band- +/- 20 % +/- 5.0 % See “Filter Bandwidth Setting” for informa- widths tion regarding changing the bandwidth / after when calibration is not possible. F Full control over HMC1023LP5E requires I Variable Bandwidth Filter access via the digital serial port (SPI). (with ability to execute User Yes Yes Filter calibration requires valid calibration Calibration to calibrate filter clock (via CALCK pin). See “RC Calibra- bandwidth) tion Circuit” Default Bandwidth Bandwidth and Default Bandwidth and Gain Pre-programmed gain and bandwidth and Gain as defined Gain as defined by setting after Power On Reset are defined when ordering the part. See by register defaults. pre-programming at (POR) “HMC1023LP5E Ordering Information 20”. (5 MHz /0dB gain) factory. Typical Corner Frequency Accuracy is with respect to bandwidth Accuracy after POR (before +/- 20 % +/- 2.5 % after POR. User Calibration) Accuracy is with respect to calibrated Yes Yes bandwidth. Typical Corner Frequency Ac- User Calibration requires access to the curacy after User Calibration +/- 2.5 % +/- 2.5 % HMC1023LP5E via the digital serial port at calibrated bandwidth (SPI) and requires a valid calibration clock (via CALCK pin). Accuracy is with respect to the desired bandwidth. User Calibration requires access to the HMC1023LP5E via the digital serial port Typical Corner Frequency Ac- (SPI) and requires a valid calibration clock curacy after User Calibration +/- 5.0 % +/- 5.0 % (via pin CALCK). at non calibrated bandwidths See “Filter Bandwidth Setting” for informa- tion regarding changing the bandwidth after calibration when further calibration is not possible. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 15 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER HMC1023LP5E Application Information Accurate, arbitrary, user defined bandwidths, programmable gain, and flexible programmable IO interface provide the HMC1023LP5E with unmatched flexibility. This flexibility together with market leading performance, in terms of T linearity, Noise Figure, and bandwidth accuracy enable a universal solution capable of supporting numerous radio M standards, frequencies, and/or bandwidths with a single hardware platform. S The HMC1023LP5E is relevant in both transmitter and receiver applications (Figure 32 and Figure 33). In transmitter applications the HMC1023LP5E serves as an anti-aliasing filter that rejects Digital-to-Analog Converter aliases and - ensures the desired transmitted spectral mask. In receiver applications the HMC1023LP5E serves as an Analog-to- G Digital converter driver, an anti-aliasing filter, and a blocker rejection filter all in one. N In both transmitter and receiver applications, excellent 6th order butterworth filter response with virtually no pass-band I S ripple and exceptional +/-2.5% bandwidth accuracy enables simple modem designs that need not utilize complex S adaptive equalization schemes to compensate for filter ripple and group delay variation. E In such applications, together with Hittite’s Wideband PLLVCOs, the HMC1023LP5E enables truly wideband multi- C standard multi-carrier hardware platforms, software configurable to the demands of each particular application. O Compared to discrete filters, the HMC1023LP5E saves valuable board area and cost. Typically higher order discrete R filters are required to achieve comparable rejection as the HMC1023LP5E due to the inherent error tolerances in the P value of each individual component. In addition, discrete filters are fixed in bandwidth, typically requiring multiple band specific hardware versions that tends to increase the cost relative to supporting only one hardware version for D all bands supported by the HMC1023LP5E. N The HMC1023LP5E overcomes the matching problem that discrete filters present with respect to baseband signal A processing. The matched dual filter paths provide excellent gain and phase balance between the two channels B eliminating the image problem which results from poor matching. E S A B / F I Figure 32. Typical Receive Path Block Diagram showing HMC1023LP5E InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 16 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER T M S - G N I S S E C O R P Figure 33. Typical Transmit Path Block DiagramHMC1023LP5E Ordering Information D N Input Interface A Input stage features a programmable input impedance (100 Ω / 400 Ω / 1 kΩ differential, or 50 Ω / 200 Ω / 500 Ω B single-ended) that is configured via Reg 01h[9] and Reg 02h[10]. Programmable impedance enables a configurable E interface, tailored to the requirements of the component driving the HMC1023LP5E. It enables maximum Noise Figure S (NF) performance regardless of the device driving the HMC1023LP5E. NF of the HMC1023LP5E with various input A impedance settings is provided in Figure 5, Figure 6 and Figure 7. Actual input impedance over frequency is shown B in Figure 29. / Wide input common mode voltage range further simplifies input interface. The HMC1023LP5E does not require any F configuration for input common mode voltage as long as the part is operated within the specifications outlined in Table I 1. The HMC1023LP5E does not require any specific impedance at the input. Input interface should be designed according to the demands of the device driving the HMC1023LP5E, while programmable input impedance of the HMC1023LP5E permits optimal matching and/or NF performance. Both ac-coupled and dc-coupled interfaces are supported at the input. Output Interface Output common mode voltage of the HMC1023LP5E is set via CMI and CMQ pins for the in-phase and quadrature outputs respectively. Wide output common mode voltage range simplifies interface with numerous devices. The HMC1023LP5E‘s 0.9 V to 3 V output common mode voltage range is specified with a 2 Vppd output signal swing. Lower common mode output voltage is supported with lower signal swing. The key requirement is that the signal swing in combination with common mode voltage does not go below 0.5 V single-ended. Hence, as an example a 0.7 V output common mode voltage level is supported with 0.8 Vppd signal swing. Figure 18 to Figure 23 show the effect of output common mode voltage on linearity performance (Output IP2 & Output IP3) of the HMC1023LP5E. The plots indicate that even for a large output signal swing of 2 Vppd, the HMC1023LP5E typically maintains high linearity performance below 0.9 V nominal output common mode limit. Figure 34 shows measured output common mode voltage as a function of input common mode setting on CMI & CMQ pins. The plot is generated with 2 Vppd output signal and shows that output common mode voltage follows the settings on CMI & CMQ pins well beyond the rated 0.9 V to 3 V. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 17 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER 5 V) E ( 4 T D MO M MON 3 S M T CO 2 - U TP G U O 1 N I S 0 0 1 2 3 4 5 S COMMON MODE SETTING CMI & CMQ PIN (V) E Figure 34. Output vs. Input Common Mode Voltage C Output impedance of the HMC1023LP5E is nominally 10 Ω single-ended or 20 Ω differential. The HMC1023LP5E O does not require any special impedance matching at the output. The output of the HMC1023LP5E is an OpAmp driver R capable of driving small and large loads alike. Output interface of the HMC1023LP5E should be designed according P to the demands of the device the HMC1023LP5E is driving. D N Linearity, Bandwidth Accuracy, and Current Consumption A As shown in Figure 25, the HMC1023LP5E is a high linearity device, typically exhibiting in excess of 30 dBm Output B IP3, and over 60 dBm Output IP2 throughout the operating range of the part. To maintain maximum performance E as measured by linearity (Output IP2 and Output IP3) and bandwidth accuracy it is recommended to use OpAmp S bias settings (Reg 02h[1:0]) outlined in Table 9. Table 9 shows that higher OpAmp bias setting, and thereby higher A current consumption is required to maintain maximum linearity performance as well as bandwidth accuracy ( < 2.5% B bandwidth error) at bandwidth settings ≥ 10 MHz. Figure 12 to Figure 23 show the effect of OpAmp bias setting (Reg 02h[1:0]) on linearity (OIP2 and OIP3) performance of the HMC1023LP5E. / F Table 9. HMC1023LP5E Bias Table I Recommended Coarse OpAmp Bias HMC1023LP5E Bandwidth Coarse Bandwidth (MHz) Setting For Best Typical Current Setting Performance Consumption (mA) (Reg 02h[9:6]) Reg 02h[1:0] 5 0000 00 172 7 0001 00 172 10 0010 00 172 14 0011 01 227 20 0100 01 227 28 0101 01 227 40 0110 01 227 50 0111 01 227 72 1000 10 260 Figure 12 to Figure 23 show that the higher OpAmp bias setting typically increases linearity OIP3 & OIP2 by 5 to 10 dB at high bandwidth setting. However, they also show that the HMC1023LP5E maintains excellent linearity performance (~60 dBm OIP2 & ~30 dBm OIP3), even at minimum OpAmp bias setting (Reg 02h[1:0] = 0). Figure 35 shows typical calibrated filter bandwidth error (accuracy) vs OpAmp bias setting (Reg 02h[1:0]). It shows that higher OpAmp bias is required at filter bandwidth settings ≥ 10 MHz in order to achieve ≤ +/-2.5 % bandwidth accuracy. However it also shows that excellent bandwidth accuracy (≤ +/-5.5 %) is achievable at all filter bandwidth settings with even the lowest OpAmp bias setting (Reg 02h[1:0]). InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 18 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER 6 5 T %) M R ( 4 O S ERR 3 Reg02[1:0] = 00 H G - NDWIDT 12 Reg02[1:0] = 01 A B N B 0 I 3 d-1 Reg02[1:0] = 10 S S -2 0 10 20 30 40 50 60 70 80 E FILTER BANDWIDTH SETTING (MHz) C Figure 35. Calibrated HMC1023LP5E Bandwidth Error vs. OpAmp Bias (Reg 02h[1:0]) O Hence for applications in which current consumption is an important performance criteria it is possible to reduce the R HMC1023LP5E current consumption by ~90 mA or ~450 mW at a cost of ~5 dB lower linearity performance and lower, P but still excellent bandwidth accuracy performance of ≤ +/-5.5 %. D N Non-Volatile One Time Programmable (OTP) Memory A The HMC1023LP5E includes OTP (One Time Programmable) memory that enables the user to program the default B configuration of the HMC1023LP5E on start-up. The programmable settings are shown in Reg 0Ah they include: E • Bandwidth S • Filter bypass enable A • Gain B • Input impedance (100 Ω or 1kΩ differential), 400 Ω differential is also available but can only be set via SPI interface. / • OpAmp bias F • Driver bias I Once the OTP memory is programmed, by default on power-up, the HMC1023LP5E enters the state programmed in OTP memory. However, even after the OTP memory is programmed HMC1023LP5E retains full functionality, and can be re-configured to any other state via Serial Port Interface. Therefore the configuration burned in OTP memory is only a default configuration of the HMC1023LP5E on power up, which can be changed to any user defined configuration after power-up using the SPI. Detailed instructions on programming the OTP memory are provided in “One Time Programmable Memory (OTP)” section. Filter Programming & Calibration Detailed description of filter bandwidth programming is provided in “Filter Bandwidth Setting” section. To achieve the rated accuracy, each HMC1023LP5E device requires calibration at least once. Once calibrated, the settings are always valid for that particular HMC1023LP5E. Filter calibration requires an input clock. More information about calibration clock and calibration procedure is provided in “RC Calibration Circuit” section. The calibration clock is only required during calibration. It is not required for the operation of the HMC1023LP5E. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 19 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER HMC1023LP5E Ordering Information The HMC1023LP5E is available as product that is either un-programmed or pre-programmed. Programming is available to a variety of filter bandwidths (defined in this context as the 3dB bandwidth). T Other options available for pre-programmed product include the single path gain and bias state as described below. M Gain and bias settings are described in Reg 02h. S When placing an order for the HMC1023LP5E please observe the following guidelines. - 1. To order the un-programmed standard part please place order using the part number HMC1023LP5E-000000. G 2. To order a pre-programmed HMC1023LP5E please determine the part number as described below and then N contact Hittite Sales at sales@hittite.com or call (978) 250-3343. I S 2.1 Minimum quantity order for the pre-programmed HMC1023LP5E-BBBGLL is 500 pieces. S 3. Pre-Programmed part number description: HMC1023LP5E-BBBGL. E C 3.1 ‘BBB’ represents a three digit number from the Table 10 that represents the desired bandwidth setting O (3 dB bandwidth) from 5 MHz to 72 MHz (for example BBB = 050 specifies a 5 MHz corner frequency). R 3.2 ‘G’ represents the gain setting of either 0 dB (G = 0) or 10 dB (G = 1). P 3.3 ‘LL’ represents the OpAmp bias setting of the HMC1023LP5E. For more information please see “Linearity, Bandwidth Accuracy, and Current Consumption” section. D N For example, to order the HMC1023LP5E pre-programmed for 72 MHz 3 dB frequency, 10 dB gain, and standard low A ‘00’ OpAmp bias setting please specify part number HMC1023LP5E-720100. B E S A Table 10. Custom Part Frequency Options B BBB frequency for custom part (actual frequency is BBB x 0.1 MHz) / 050 069 093 128 171 229 307 411 554 709 F 052 070 095 131 175 235 315 422 565 720 I 053 071 098 134 179 240 322 432 576 054 073 100 137 180 246 330 443 587 056 075 102 140 184 253 338 454 598 057 076 105 141 188 259 347 465 609 058 078 108 144 193 265 355 476 621 060 080 110 148 198 272 364 488 632 061 082 113 151 203 278 373 500 643 063 084 116 155 208 280 382 510 654 064 086 119 159 213 285 392 521 665 066 088 121 163 218 292 400 532 676 068 091 124 167 224 300 401 543 687 For additional information or inquiries please contact Hittite Apps Support at apps@hittite.com. [1] The Output IP2 and Output IP3 for the two linearity settings are shown in Figure 13 and Figure 14. High linearity setting improves linearity for bandwidths greater than 30 MHz at the cost of increased current consumption (additional 25 mA). InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 20 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Theory of Operation The HMC1023LP5E consists of the following functional blocks T 1. Input Gain Stage M 2. 6th Order Butterworth LPF 3. Output Driver S 4. RC Calibration Circuit - 5. Bias Circuit G 6. One Time Programmable Memory 7. Serial Port interface N 8. Built in Self Test (RC-BIST) I S S Input Gain Stage E The HMC1023LP5E input stage consists of a programmable 0 or 10 dB gain stage which in turn drives the 6th order C LPF. A block diagram showing input impedance of the I channel is presented below, Q channel is similar. O R P D N A B E S A B / F I Figure 36. Input Stage Block Diagram 6th Order Low Pass Filter (LPF) The LPF allows for coarse bandwidth tuning by varying the capacitive elements in the filter, while the fine bandwidth tuning is accomplished by varying the resistors. Note that all Op-Amps in the LPF are class AB for minimum power consumption in the filter while maintaining excellent distortion characteristics even in large signal swing conditions. The attenuation due to the LPF can be calculated for any frequency, f, from the standard Butterworth transfer function for a 6th order filter. Specifically the attenuation of the filter, in dB, can be calculated as: attenuation = 10*log (1+(f/f)(2*6)) 10 c where f is the 3 dB bandwidth or corner frequency for the filter. c Note that for a 6th order Butterworth filter the 1 dB bandwidth is 90% of f, and the 0.3 dB bandwidth is 80% of f. c c Filter Bandwidth Setting The 3 dB bandwidth of the HMC1023LP5E is programmable anywhere within the range from 5 MHz to 72 MHz. When calibrated, filter bandwidth is accurate to within +/-2.5% of the programmed bandwidth, if not calibrated it is accurate to within +/-20% of the programmed bandwidth. The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E. Once InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 21 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER executed, if the calibration settings are remembered, they are always valid for a specific HMC1023LP5E. Please note that best bandwidth accuracy is achieved when the HMC1023LP5E is calibrated at its typical operating temperature. Programmed bandwidth varies 0.03 %/ºC. T M Filter Bandwidth Configuration S The HMC1023LP5E bandwidths are configured using Coarse Bandwidth Settings in Reg 02h[9:6], and Fine Bandwidth - Settings in Reg 03h[3:0]. Coarse Bandwidth Settings select from a choice of coarse bandwidth options in Table 11, G and the Fine Bandwidth Settings further refine the selected coarse bandwidth settings according to Table 12. N In all cases, once the Reg 02h[9:6] and/or Reg 03h[3:0] have been programmed it is required to set Reg 01h[4]=1 in I order to instruct the HMC1023LP5E to use provided settings. S S After calculating the settings for a given device they can be stored permanently in the non volatile memory (See “One E Time Programmable Memory (OTP)” for more information). C O Uncalibrated Bandwidth Configuration R When not calibrated, the coarse bandwidth is selected via Reg 02h[9:6] according to the desired coarse bandwidth P setting in Table 11. D Example: to select bandwidth of 14 MHz simply write Reg 02h[9:6] = ‘0011’b, then write Reg 01h[4]=1 to instruct the N HMC1023LP5E to use provided settings. A If desired, it is possible to tune to an arbitrary bandwidth choice not provided in Table 11. In that case nearest coarse B bandwidth is selected via Reg 02h[9:6] according to Table 11, and the bandwidth is further refined via Reg 03h[3:0] E according to Table 12, where S Reg 03h[3:0] = f / f , A WANTED BW_norm_coarse_typ where f corresponds to the selected typical coarse bandwidth setting in Table 11, programmed via Reg B BW_norm_coarse_typ 02h[9:6]. / Example: to select the bandwidth of 13 MHz, select the closest typical value in Table 11, and program Reg 02h[9:6] F accordingly (ie. Reg 02h[9:6] = ‘0011’b), then Reg 03h[3:0] = f / f = 13 MHz/14 MHz = 0.9286. I WANTED BW_norm_coarse_typ Hence from Table 12, Reg 03h[3:0] = ‘0100’. Finally, write Reg 01h[4]=1 to instruct the HMC1023LP5E to use provided settings. In all cases, when uncalibrated the bandwidth is accurate to within +/-20% of the programmed bandwidth. Calibrated Bandwidth Configuration The calibration of HMC1023LP5E is required to be executed only once for each individual HMC1023LP5E. Once executed, if the calibration settings are remembered, they are always valid for that specific HMC1023LP5E. Detailed instructions of how to calibrate the HMC1023LP5E are available in RC Calibration Circuit section. When calibrated the programmed bandwidth is accurate to +/-2.5%. The HMC1023LP5E calibrated bandwidth can be programmed in two ways, Automatic or Manual. The automatic calibration supports only Coarse Bandwidth Settings in Table 11, whereas the Manual calibration supports arbitrary bandwidths from 5 MHz to 72 MHz. In both cases the bandwidth is accurate to within +/-2.5%. Calibrated Automatic Bandwidth Configuration In Automatic bandwidth setting the user simply selects from a choice of Coarse Bandwidths in Table 11 via Reg 02h[9:6], and the HMC1023LP5E automatically programs Reg 03h[3:0] during calibration so that the selected bandwidth is accurate to within +/-2.5%. Example: to select bandwidth of 14 MHz simply write Reg 02h[9:6] = ‘0011’b, then write Reg 01h[4]=1 to instruct the HMC1023LP5E to use provided settings. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 22 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Calibrated Manual Bandwidth Configuration Manual bandwidth setting enables arbitrary user defined bandwidths between 5 MHz and 72 MHz accurate to within +/-2.5%. The coarse bandwidth is selected from Table 11 via Reg 02h[9:6], and that bandwidth is further refined using T selections in Table 12 via Reg 03h[3:0]. M S Initially the calibration result is read from Reg 09h[23:0]. Then required Coarse Bandwidth selection is calculated as follows: - f = f * (Reg 09h[23:0] + 153600)/10370000 (EQ 1) G BW_norm_coarse WANTED N where fWANTED is the desired arbitrary bandwidth. The Coarse Bandwidth nearest to calculated fBW_norm_coarse is selected from Table 11 and written to Reg 02h[9:6]. I S To calculate the Fine Bandwidth Setting fine_tune_ratio is calculated as shown in (EQ 2): S E fine_tune_ratio = f / f (EQ 2) BW_norm_coarse BW_norm_coarse_typ C where the f is given in (EQ 1), and f is the nearest corresponding bandwidth in Table 11. Then BW_norm_coarse BW_norm_coarse_typ O Fine Bandwidth Setting is selected from a nearest column in Table 12 that corresponds to the calculated fine_tune_ R ratio and programmed to Reg 03h[3:0]. P Example: to select the bandwidth of 13 MHz, initially read Reg 09h[23:0] (in this example Reg 09h[23:0] = 10470000). Then according to (EQ 1), f = 13 MHz * (10470000 + 153600)/10370000 = 13.318 MHz. Select the closest D BW_norm_coarse typical value in Table 11 to 13.318 MHz and program Reg 02h[9:6] accordingly (ie. Reg 02h[9:6] = ‘0011’b), then Reg N 03h[3:0] = f / f = 13.317917 MHz/14 MHz = 0.95128. Hence from Table 12, Reg 03h[3:0] = ‘0101’. WANTED BW_norm_coarse_typ A Finally, write Reg 01h[4]=1 to instruct the HMC1023LP5E to use provided settings. B Please note that the HMC1023LP5E Evaluation Software distributed with HMC1023LP5E Evaluation Kits implements E this Calibrated Arbitrary Bandwidth algorithm. S A Table 11. Normalized Bandwidth Look up Table B f BW_norm_coarse / coarse_bandwidth_code[3:0] min typ max F (MHz) (MHz) (MHz) I 0000 3.948 5 6.050 0001 5.527 7 8.470 0010 7.896 10 12.100 0011 11.054 14 16.940 0100 15.792 20 24.200 0101 22.109 28 33.880 0110 31.584 40 48.400 0111 39.480 50 60.500 1000 56.851 72 87.120 InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 23 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 12. Calibration Code Look up Table fine_tune_ratio T fine_bandwidth_code [3:0] min typ max M (MHz/MHz) (MHz/MHz) (MHz/MHz) S 0000 0.790 0.803 0.818 0001 0.818 0.832 0.846 - G 0010 0.846 0.862 0.878 N 0011 0.878 0.893 0.909 I 0100 0.909 0.926 0.943 S 0101 0.943 0.959 0.976 S 0110 0.976 0.994 1.012 E C 0111 1.012 1.030 1.048 O 1000 1.048 1.063 1.078 R 1001 1.078 1.097 1.116 P 1010 1.116 1.136 1.155 1011 1.155 1.183 1.210 D To reprogram the HMC1023LP5E to any other bandwidth simply repeat the steps above. N A B Filter Bandwidth Setting After Calibration E In cases where ctune is unknown but the calibrated and programmed bandwidth is known, it is possible to estimate S the value of ctune based on the values of Coarse Bandwidth Code and Fine Bandwidth Code and the corresponding A values in Table 11 and Table 12. B For example, if the 3 dB bandwidth for the HMC1023LP5E was factory pre-programmed to a customer defined / requirement of 34 MHz and Reg 02h[9:6] = “0110” (Coarse Bandwidth Code) and Reg 03h[3:0] = “0010” (Fine F Bandwidth Code), as determined from Reg 0Ah for a pre-programmed part or from Reg 02h & Reg 03h for a non I programmed part, then ctune can be estimated as follows: 1. Lookup the nominal coarse bandwidth and fine bandwidth frequencies. a. From Table 11 the nominal coarse frequency is 40 MHz b. From Table 12 the nominal fine normalized frequency is 0.862 MHz/ MHz or simply 0.862 2. Estimate ctune as: ctune=(40 MHz * 0.862 )/ 34 MHz = 1.0141 This value of ctune can now be used to calculate any arbitrary filter frequency as described above. RC Calibration Circuit The RC Calibration block uses a known user supplied clock to measure an on chip RC time constant. This measurement is representative of the uncorrected corner frequency error for a given bandwidth for the HMC1023LP5E. Calibration is normally done at room temperature. Refer to “Table 1. Electrical Specifications” for further details on the variation of the 3 dB cutoff point with temperature. Typically programmed bandwidth varies 0.03 %/ºC. With this information, the HMC1023LP5E can correctly fine tune the LPF by adjusting the resistors in the LPF to center the corner frequency to the desired bandwidth. To calibrate the HMC1023LP5E proceeds as follows: 1. Apply a clock signal of frequency between 20 MHz and 100 MHz on the CALCK pin (pin 11) of the HMC1023LP5E. The clock signal only needs to be applied during the calibration procedure and is not InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 24 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER required at other time. Please note that an integrated clock doubler must be enabled for clock frequencies less than 40 MHz. To enable the clock doubler simply write Reg 01h[5] = 1. 2. Write the applied clock signal period to Reg 05h[14:0] in picoseconds. T 3. Enable the RC calibration circuit by writing Reg 01h[1] = 1. M 4. Write Reg 06h[8:0] = 152d = 96h. S 5. Write Reg 04h = 0 to initialize the calibration cycle. - G The HMC1023LP5E indicates that the calibration is in process when Reg 08h [4]=1. When Reg 08h [4]=0 calibration has finished. When complete, the calibration Fine Bandwidth Value can be retrieved from Reg 08h[3:0] Once calibrated N the HMC1023LP5E automatically writes the calibrated fine Fine Bandwidth values to Reg 03h[3:0] (ie. Reg 03h[3:0] = I S Reg 08h[3:0]) as explained in Calibrated Automatic Bandwidth Configuration section. If desired, the calibration results S can be overridden via Reg 03h [3:0], as explained in Calibrated Manual Bandwidth Configuration section. E C Output Driver O The HMC1023LP5E output driver consists of a differential class AB driver which is designed to drive typical ADC R loads directly or can drive up to 200 Ω in parallel with 50 pF to AC ground per differential output. Note that the output P common mode of the driver is controlled directly via the CMI/CMQ pin and can be set as per “Table 1. Electrical D Specifications”. Also note, that driver loading does not impact filter transfer responses. N A block diagram showing output connections is presented below. A B E S A B / F I Figure 37. Output Driver Block Diagram Bias Circuit A band gap reference circuit generates the reference currents used by the different sections. The bias circuit is enabled or disabled as required with the I or Q channel as appropriate. One Time Programmable Memory (OTP) The HMC1023LP5E features one time programmable memory which can be programmed by the end user or ordered from the factory precalibrated. The OTP memory is programmed via the standard 4 wire serial port (SPI) as follows: InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 25 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER 1. enable OTP write mode (see Reg 0Bh bit 0 enables OTP programming). 2. read the status of the OTP active flag (see Reg 08h, bit 5 is the OTP active flag). The Write Pulse Status (OTP active flag) must be 0 to allow the OTP to be programmed. T 3. write the OTP bit address to be set (Reg 0Ch). This address is a 4 bit number representing the address of the M bit to be programmed. Note that when programming a bit we change its state from 0 to 1 and this operation S cannot be reversed. OTP bit addresses can be found in Reg 08h. 4. start the OTP Write operation. Write any data to the OTP strobe register (Reg 0Dh). - G 5. read the status of the OTP active flag (Reg 08h, bit 5 is the OTP active flag). If bit 5 is set then the Write pulse N is still high. Repeat until bit 5 is 0 which indicates that the write pulse is finished. I 6. Repeat steps 3 to 5 to program the remaining desired bits. S S Note that bit 13 OTP_prg_flag must be set by the user to use OTP values. E 7. When completed, disable OTP write mode (Reg 0Bh). C O Power on Reset and Soft Reset R The HMC1023LP5E has a built in Power On Reset and also a serial port accessible Soft Reset. Power On Reset is P accomplished when power is cycled to the HMC1023LP5E, while Soft Reset is accomplished via the SPI by writing D Reg 00h[5] = 1 followed by writing Reg 00h[5] = 0. All chip registers will be reset to default states approximately 250us N after power up. A B Serial Port Interface E The HMC1023LP5E features a four wire SPI. Four wires (SEN,SCK,SDI,SDO) are necessary to implement a SPI S Read/Write functionality, while a Write only functionality can be implemented with 3 wires (SEN,SCK,SDI). The A HMC1023LP5E SPI features a 3-bit Chip_ID that enables operation of up to 8 devices on the same SPI bus. Chip_ID B of HMC1023LP5E is set to ‘101’b. / Please note that every SPI operation is both a Read and a Write. Data is written to the HMC1023LP5E on the SDI line, F and read from the HMC1023LP5E on the SDO line every Read/Write cycle, as shown in Figure 38. Every SPI write I the HMC1023LP5E returns the data contained in the register whose address is specified in Reg 00h[4:0] prior to the Write/Read cycle. Hence to read from a particular HMC1023LP5E register, it is necessary to initially write the address of that register to Register 0 (ie. Reg 00h[4:0] = REG_ADDR, where REG_ADDR is the address of the register to be read on the next Read/Write cycle). The desired register will be read on the next (2nd) Write/Read cycle. If nothing additional is desired to be written to the HMC1023LP5E on the 2nd Write/Read cycle, simply rewrite Reg 00h[4:0] = REG_ADDR on the second Read/Write cycle to conclude the register read. In summary, the Read cycle uses indirect addressing where Reg 00h contains the pointer to the address of the register to be Read. Note that in any SPI cycle the Write data is stored in the register at the end of the cycle when SEN goes high. This means that the address pointer (Reg 00h[4:0]) must be set prior to the Read/Write cycle in which the desired data is read. Typical serial port operation can be run with SCK at speeds up to 30 MHz. Serial Port WRITE Operation The host changes the data on the falling edge of SCK and the HMC1023LP5E reads the data on the rising edge. A typical WRITE cycle is shown in Figure 38. It is 32 clock cycles long. 1. The host sets Serial Port Enable (SEN) low and places the MSB of the data on Serial Data Input (SDI) followed by a rising edge on SCK. 2. HMC1023LP5E reads SDI (MSB first) on the 1st rising edge of SCK after SEN. InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 26 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER 3. HMC1023LP5E registers the data bits, D23:D0, on the next 23 rising edges of SCK (total of 24 data bits). 4. Host places the 5 register address bits, A4:A0, on the next 5 falling edges of SCK (MSB to LSB) while the HMC1023LP5E reads the address bits on the corresponding rising edge of SCK. T 5. Host places the 3 chip address bits, CA2:CA0=[101], on the next 3 falling edges of SCK (MSB to LSB). Note M the HMC1023LP5E chip address is fixed as “5d” or “101b”. S 6. SEN goes from low to high after the 32nd rising edge of SCK. This completes the WRITE cycle. - 7. HMC1023LP5E also exports data back on the Serial Data Out (SDO) line. For details see the section on G READ operation. N I S Serial Port READ Operation S The Read data is available on SDO line. This line itself is tri-stated when the device is not being addressed. However E when the device is active and has been addressed by the SPI, the HMC1023LP5E controls the SDO line and exports C data on this line during the next SPI cycle. O HMC1023LP5E changes the data to the host on the rising edge of SCK and the host reads the data from HMC1023LP5E R on the falling edge. P A typical READ cycle is shown in Figure 38. Read cycle is 32 clock cycles long. To specifically read a register, the D address of that register must be written to dedicated Reg 00h. This requires two full cycles, one to write the N required address, and a 2nd to retrieve the data. A read cycle can then be initiated as follows; A 1. The host sets SEN line low, followed by a rising edge SCK. B 2. HMC1023LP5E reads SDI (MSB first) on the 1st rising edge of SCK after SEN is set low. E S 3. HMC1023LP5E registers the data bits in the next 23 rising edges of SCK (total of 24 data bits). The LSBs of the data bits represent the address of the register that is intended to be read. A B 4. Host places the 5 register address bits on the next 5 falling edges of SCK (MSB to LSB) while the HMC1023LP5E reads the address bits on the corresponding rising edge of SCK. For a read operation this / is “00000”b. F I 5. Host places the 3 chip address bits <101> on the next 3 falling edges of SCK (MSB to LSB). Note the HMC1023LP5E chip address is fixed as “5d” or “101b”. 6. SEN goes from low to high after the 32th rising edge of SCK. This completes the first portion of the READ cycle, in which the address of the register to be read on the next Read/Write cycle is written to Reg 00h. 7. The host sets SEN line low, followed by a rising edge SCK. 8. HMC1023LP5E places the 24 data bits, 5 address bits, and 3 Chip_ID bits, on the SDO, on each rising edge of the SCK, commencing with the first rising edge beginning with MSB. 9. The host sets SEN line high after reading the 32 bits from the SDO output. The 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. 10. This completes the READ cycle. Note that the second Read/Write cycle is also both a Read and a Write. Hence if it is not desired to write anything new to the HMC1023LP5E on the second Read/Write cycle simply rewrite the same data to Reg 00h that was written on the previous cycle. Serial Port Bus Operation with Multiple Devices The SPI bus architecture supports multiple devices on the same SPI bus. Each HMC1023LP5E on the bus requires a dedicated SEN line to enable the appropriate device. The SDO line is normally driven by the HMC1023LP5E during and after an SPI read/write which is addressed directly to the HMC1023LP5E (chip address = 5d or ‘101’b). A write to the HMC1023LP5E where chip address is set to any value other than 5d or ‘101’b is required in order to ensure that the SDO pin remains tri-stated by the HMC1023LP5E InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 27 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER after accessing the HMC1023LP5E. Such a write will not result in any change in the HMC1023LP5E configuration because of the incorrect chip address. T M S - G N I S S E C O R P D N Figure 38. SPI Timing Diagram A B E Table 13. Main SPI Timing Characteristics S DVDD = 5V ±5%, GND = 0V A Parameter Conditions Min Typ Max Units B t1 SDI to SCK Setup Time 8 nsec / t2 SDI to SCK Hold Time 8 nsec F t3 SCK High Duration [a] 10 nsec I t4 SCK Low Duration 10 nsec t5 SEN Low Duration 20 nsec t6 SEN High Duration 20 nsec t7 SCK to SEN [b] 8 nsec t8 SCK to SDO Out[c] 8 nsec a. The SPI is relative insensitive to the duty cycle of SCK. b. SEN must rise after the 32nd falling edge of SCK but before the next rising SCK edge. If SCK is shared amongst several devices this timing must be respected. c. Typical load to SDO 10pF, max 20pF Built In Self Test (RC-BIST) The HMC1023LP5E RC Calibration state machine features built in self test (RC-BIST) to facilitate improved device testing. The RC-BIST can be exercised as follows: 1. Apply reset to the chip via a power cycle (hard reset) or via the SPI (soft reset). Soft reset is accomplished by writing Reg 00h = 20h, followed by writing Reg 00h = 0h. 2. Setup the RCCAL input parameters if desired. Note that the RC-BIST will work with the default settings from power up however test coverage will improve if the following SPI registers are also accessed: a. program the RC clock period (Reg 05h). InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 28 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER b. program the measurement adjustment setting (Reg 06h). c. program the threshold adjustment settings. T 3. enable BIST mode (Reg 0Eh). M 4. start the BIST by writing any data to the BIST strobe register (Reg 04h). Note that the BIST will take 2^18 ~ S 260k clock cycles to complete. - 5. read the result of the BIST test. Read the value in the BIST Out register (Reg 0F). Bit 16 is the busy flag and G will be set when the BIST is still running. When this bit is reset then the BIST output value in bits 15:0 are N valid. I S Note that the value of the BIST output must be compared to the expected result depending on values S programmed into the registers in step 2. E The BIST procedure can be repeated as desired to ensure adequate test coverage for the RC Calibration engine. The C suggested register settings to maximize test coverage with BIST is provided below. O R P Table 14. Test Conditions Register Settings Expected Result D Reg 05h[14:0]=65, Reg 06h[8:0]=255, Reg10h[4:0] to eg1Ah[4:0]=0d or 0h Reg 0Fh[15:0]=36092, Reg 09h[23:0]=14942167 N Reg 05h[14:0]=32702, Reg 06h[8:0]=36, Reg10h[4:0] to Reg1Ah[4:0]=31d or 1Fh Reg 0Fh[15:0]=55027, Reg 09h[23:0]=14143649 A B Reg 05h[14:0]=10922, Reg 06h[8:0]=170, Reg10h[4:0] to Reg1Ah[4:0]=10d or Ah Reg 0Fh[15:0]=28618, Reg 09h[23:0]=8907563 E Reg 05h[14:0]=21845, Reg06h[8:0]=853, Reg10h[4:0] to Reg1Ah[4:0]=21d or 15h Reg oFg[15:0]=16368, Reg 09h[23:0]=3396981 S A B / F I InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 29 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Register Map Table 15. Reg 00h - Chip_ID (Read Only) Bit Name Width Default Description T [23:0] Chip_ID 24 D7780 HMC1023LP5E Chip_ID. M S - Table 16. Reg 00h - Read Address (Write Only) G Bit Name Width Default Description N [4:0] Register Read Address 5 - Address of the register to be read on the next read/write cycle. I S Soft Reset. 1: Soft reset. It is recommended to set this bit to 0 after soft reset event (ie. after S [5] Soft Reset 1 - writing Reg 00h[5] = 1) E 0: No change C [23:6] Not Defined 1 - Don’t Care. O R Table 17. Reg 01h - Enable P Bit Name Width Default Description D [0] OTP_DontUse 1 0 Default use stored OTP values (only if OTP is programmed) N [1] cal_enable 1 0 Enable RC Calibration circuit A B [2] filter_I_enable 1 1 Enable I channel gain stage, filter, and driver E [3] filter_Q_enable 1 1 Enable Q channel gain stage, filter, and driver S [4] force_cal_code 1 0 Force calibration setting to use SPI values (Reg 03h - Calibration) A 0-- Doubler Disabled. RC Calibration clock B 40 MHz<RC calibration clock<80 MHz [5] doubler_enable 1 0 1 -- Doubler Enabled. RC Calibration clock / 20 MHz<RC calibration clock<40 MHz F I Note: calibration clock duty cycle must be within 50% +/- 10% [8:6] reserved 3 000 Sets the I and Q channel input impedances together with Reg 01h[9]. Reg 02h[10] Reg 01h[9] impedance 0 0 1000 Ω (default) [9] LSB_Zinput_select 1 0 0 1 400 Ω 1 x 100 Ω (Reg 02h[10] and One Time Programmable memory Reg 0Ah[15] select between 100 Ω and 1000/400 Ω) [23:10] unused InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 30 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 18. Reg 02h - Settings Bit Name Width Default Description T Opamp bias setting. M 00 -- min bias S [1:0] opamp_bias[1:0] 2 01 11 -- max bias opamp_bias[1:0]=01 standard bias (characterized value) - opamp_bias[1:0]=10 high linearity bias G Driver bias setting. 00 -- min bias N [3:2] drvr_bias[1:0] 2 10 11 -- max bias I drvr_bias[1:0]=10 standard bias (characterized value) S S VGA gain setting. [4] gain_10dB 1 0 0: 0dB VGA gain E 1: 10dB VGA gain C Filter bypass setting. O [5] bypass_filter 1 0 0: Filter bypass disabled 1: Filter bypass enabled R P Sets filter coarse tuning range 0000 - 5 MHz D 0001 - 7 MHz 0010 - 10 MHz N 0011 - 14 MHz [9:6] coarse_bandwidth_code[3:0] 4 0000 A 0100 - 20 MHz B 0101 - 28 MHz 0110 - 40 MHz E 0111 - 50 MHz S 1000 - 72 MHz A Sets the I and Q channel input impedances together with Reg 01h[9]. B Reg 02h[10] Reg 01h[9] impedance 0 0 1000 Ω (default) / [10] MSB_Zinput_select 1 0 0 1 400 Ω F 1 x 100 Ω I (Reg 02h[10] and One Time Programmable memory Reg 0Ah[15] select between 100 Ω and 1000/400 Ω) [23:11] unused Table 19. Reg 03h - Calibration Bit Name Width Default Description fine bandwidth setting override bits (register 01 bit 4, force_cal_code, must be set). 0000 - Minimum frequency 0001 0010 0011 0100 [3:0] fine_bandwidth_code[3:0] 4 0000 0101 0110 0111 1000 1001 1010 1011 - Maximum frequency [23:4] unused InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 31 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 20. Reg 04h - Calibration/RC-BIST Strobe T Calibration strobe register is used only to initialize a calibration cycle. Writing any value to this register serves to M request a new calibration cycle. S Note that this register is also used to start the Built In Self Test (RC-BIST) mode and this is used to test the fault coverage of the RC calibration engine. - Bit Name Width Default Description G [23:0] Request calibration 1 0 Writing to any bit in this register starts a calibration cycle. N I S S Table 21. Reg 05h - Clk Period E Bit Name Width Default Description C Sets the clock period for the RC calibration circuit. Clock period entered is in O [14:0] clock_period[14:0] 15 0000h pico seconds. R i.e. 1/40 MHz clock =25000ps= 110000110101000b=61A8h P [23:15] unused D N A Table 22. Reg 06h - Measure Adjust B Correction value used to adjust RC Calibration result. Value is in 1.024ns increments. E S Bit Name Width Default Description A Correction value to ADD to counter output before counter is decoded for B calibration setting. [8:0] meas_adj[8:0] 9 000h Number is in 2’s complement format. / Note this applies to all settings universally. F [23:9] unused I Table 23. Reg 07h Unused Table 24. Reg 08h - Calibration Status (read only) Bit Name Width Default Description fine_bandwidth_setting (must run a calibration cycle to get valid data) [3:0] fine_bandwidth_code[3:0] 4 0000 Valid states are 0000 to 1011 (see Table 3. Reg 03h - Calibration) [4] cal_busy 1 Calibration active flag [5] OPT _write_busy 1 OTP write active flag [23:6] unused Table 25. Reg 09h - Calibration Count (read-only) Bit Name Width Default Description [23:0] count_read[23:0] 24 Output of calibration counter in pico seconds (unadjusted) InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 32 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 26. Reg 0Ah - OTP Values (read-only) Bit Name Width Default Description T OTP_fine_bandwidth_ Non volatile fine_bandwidth_code[3:0]. Definition is same as per “Reg 03h - M [3:0] 4 code[3:0] Calibration” S OTP_course_bandwidth_ [6:4] 3 Non volatile version of SPI values found in Reg 02h[6:8] code[2:0] - [7] OTP_Gain_10dB 1 G [8] OTP_bypass_filter 1 N Non volatile version of SPI values found in “Reg 02h - Settings” [10:9] OTP_opamp_bias[1:0] 2 I S [12:11] OTP_drvr_bias[1:0] 2 S This flag must be set if the OTP values are to be used and must be set by the E [13] OTP_prg_flag 1 user. C If not set, this flag overrides bit 0 of Reg 01h. O [14] OTP_Coarse_Bandwidth[3] Non volatile version of SPI values found in Reg 02h[9] R [15] OTP__Zinput_select 1 Non volatile version of SPI value found in Reg 02h[10] P [23:16] unused D N A Table 27. Reg 0Bh - OTP Write Enable B Bit Name Width Default Description E [0] EFR_Write_enable 1 0 Enables OTP Programming S [23:1] unused A B / Table 28. Reg 0Ch - OTP Write F OTP address register is used in programming of OTP. I Bit Name Width Default Description [3:0] OTP Address 4 0 Address of OTP bit to be set [23:4] unused Table 29. Reg 0Dh - OTP Write Pulse OTP strobe register is used in programming of OTP. Bit Name Width Default Description [23:0] reserved 1 0 reserved Table 30. Reg 0Eh - RC-BIST Enable Bit Name Width Default Description [0] enable_RCBIST_mode 1 0 RC-BIST mode enable [23:1] unused InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 33 rliicgehntss eo fi sth girrda nptaerdti ebsy t himatp mlicaaPyt iorhenso uonlrt ofertoh:m e9r wit7sis 8ues -eu2.n dS5ep0re ca-inf3iyc 3aptia4otne3sn ts ou rb jpeFacttae tnoxt c:r hig9ahn7tgs 8eo wf- 2Aithn5oau0lot g-n 3oDti3ecve7i.c 3eNso . POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D

HMC1023LP5E v01.0113 72 MHz DUAL PROGRAMMABLE LOW PASS FILTER WITH DRIVER Table 31. Reg 0Fh - RC-BIST Out T Bit Name Width Default Description M [15:0] crc_BIST[15:0] 16 0 RC-BIST CRC check result S RC-BIST busy flag. Indicates that BIST cycle is not completed and data crc_ [16] crc_RC-BIST_busy_flag 1 0 BIST[15:0] is invalid - [23:17] unused G N Table 32. Reg 10h to Reg1A - Window Threshold SI S OTP strobe register is used in programming of OTP. E Bit Name Width Default Description C [23:0] reserved reserved O R P D N A B E S A B / F I InfoFrmoart iopn rfiucrneis,h edde blyi vAenraylo ga Dnedvic teos ips lbaelcieeve do rtod beer sac:c Huraittet iatned Mreliiacbrleo. wHoawveeve rC, noo rpoForar tpioricne,, 2d eElilviezrayb, aentdh tDo rpivlaec,e C ohrdeelrms: sAfonardlo,g MDeAv i0ce1s8, 2In4c., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that maPy rhesounlt fero:m 9 it7s 8us-e2. S5p0ec-if3ic3ati4on3s s u b jeFcta tox c: h9an7g8e w-2ith5ou0t -n3oti3ce7. 3No POhrodnee:r 7 O81n-3-2li9n-e4 7a0t0 w(cid:127) wOrwde.hr oitntliitnee. cato wmww.analog.com 34 license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arAe tphep plriocpearttyi oof nth eSir urepsppecotivret :o wPnehrso.ne: 978-250-3A3p4p3li c aotrio na Spuppsp@orht: iPtthitoen.ec: o1-m800-ANALOG-D