DATASHEET HIP4081A FN3659 80V/2.5A Peak, High Frequency Full Bridge FET Driver Rev 8.00 September 15, 2015 The HIP4081A is a high frequency, medium voltage Full Features Bridge N-Channel FET driver IC, available in 20 lead plastic • Independently Drives 4 N-Channel FET in Half Bridge or SOIC and DIP packages. The HIP4081A can drive every Full Bridge Configurations possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch • Bootstrap Supply Max Voltage to 95V DC at frequencies up to 1MHz and is well suited to driving Voice • Drives 1000pF Load at 1MHz in Free Air at 50°C with Rise Coil Motors, high-frequency switching power amplifiers, and and Fall Times of Typically 10ns power supplies. • User-Programmable Dead Time For example, the HIP4081A can drive medium voltage brush • On-Chip Charge-Pump and Bootstrap Upper Bias motors, and two HIP4081As can be used to drive high Supplies performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. • DIS (Disable) Overrides Input Control Short propagation delays of approximately 55ns maximizes • Input Logic Thresholds Compatible with 5V to 15V Logic control loop crossover frequencies and dead-times which Levels can be adjusted to near zero to minimize distortion, resulting • Very Low Power Consumption in rapid, precise control of the driven load. • Undervoltage Protection A similar part, the HIP4080A, includes an on-chip input • Pb-free Available comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching. Applications The Application Note for the HIP4081A is the AN9405. • Medium/Large Voice Coil Motors Ordering Information • Full Bridge Power Supplies TEMP • Switching Power Amplifiers PART RANGE PKG. NUMBER (°C) PACKAGE DWG. # • High Performance Motor Controls HIP4081AIP (No longer -40 to 85 20 Ld PDIP E20.3 • Noise Cancellation Systems available, recommended replacement: HIP4081AIPZ) • Battery Powered Vehicles HIP4081AIPZ (Note) -40 to 85 20 Ld PDIP E20.3 • Peripherals (Pb-free) • U.P.S. HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3 HIP4081AIBZ (Note) -40 to 85 20 Ld SOIC (W) M20.3 Pinout (Pb-free) HIP4081A NOTE: Intersil Pb-free products employ special Pb-free material (PDIP, SOIC) sets; molding compounds/die attach materials and 100% matte tin TOP VIEW plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed BHB 1 20 BHO the Pb-free requirements of IPC/JEDEC J Std-020B. BHI 2 19 BHS DIS 3 18 BLO VSS 4 17 BLS BLI 5 16 VDD ALI 6 15 VCC AHI 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO FN3659 Rev 8.00 Page 1 of 17 September 15, 2015

HIP4081A Application Block Diagram 80V 12V BHO BHS LOAD BHI BLO BLI HIP4081A ALI ALO AHS AHI AHO GND GND Functional Block Diagram (1/2 HIP4081A) AHB HIGH VOLTAGE BUS  80VDC 10 UNDER- CHARGE LEVEL SHIFT DRIVER AHO VOLTAGE PUMP AND LATCH 11 CBS AHS VDD 16 12 AHI 7 TURN-ON DELAY DBS TO VDD (PIN 16) DIS 3 15 VCC DRIVER ALO +12VDC TURN-ON 13 BIAS ALI 6 DELAY SUPPLY ALS CBF 14 HDEL 8 LDEL 9 VSS 4 FN3659 Rev 8.00 Page 2 of 17 September 15, 2015

HIP4081A Typical Application (PWM Mode Switching) 80V 1 BHB BHO 20 12V 2 BHI BHS 19 A LOAD DIS 3 DIS 81 BLO 18 0 4 VSS P4 BLS 17 PWM HI INPUT 5 BLI 81/ VDD 16 6 ALI P40 VCC 15 12V 7 AHI HI ALS 14 8 HDEL ALO 13 9 LDEL AHS 12 10 AHB AHO 11 GND TO OPTIONAL - CURRENT CONTROLLER + 6V GND FN3659 Rev 8.00 Page 3 of 17 September 15, 2015

HIP4081A Absolute Maximum Ratings Thermal Information Supply Voltage, V and V . . . . . . . . . . . . . . . . . . . .-0.3V to 16V Thermal Resistance (Typical, Note 1)  (°C/W) DD CC JA Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C) DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Voltage on AHS, BHS . . .-6.0V (Transient) to 70V (-55°C to 125°C) Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65°C to 150°C Voltage on ALS, BLS. . . . . . .-2.0V (Transient) to +2.0V (Transient) Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . .125°C Voltage on AHB, BHB . . . . . . . .VAHS, BHS -0.3V to VAHS, BHS +VDD Lead Temperature (Soldering 10s)). . . . . . . . . . . . . . . . . . . . .300°C Voltage on ALO, BLO . . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V (For SOIC - Lead Tips Only Voltage on AHO, BHO. . . . . . . V -0.3V to V +0.3V AHS, BHS AHB, BHB Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to V , unless otherwise specified. SS Operating Conditions Supply Voltage, V and V . . . . . . . . . . . . . . . . . . +9.5V to +15V DD CC Voltage on ALS, BLS. . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . .V +5V to V +15V AHS, BHS AHS, BHS Input Current, HDEL and LDEL. . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . . .-40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1.  is measured with the component mounted on an evaluation PC board in free air. JA Electrical Specifications V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 100K and DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL T = 25°C, Unless Otherwise Specified A T = -40°C TO JS T = 25°C 125°C J PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS SUPPLY CURRENTS AND CHARGE PUMPS V Quiescent Current I All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA DD DD V Operating Current I Outputs switching f = 500kHz 9.5 12.5 15.5 8.5 15.5 mA DD DDO V Quiescent Current I All Inputs = 0V, I = I = 0 - 0.1 10 - 20 A CC CC ALO BLO V Operating Current I f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA CC CCO AHB, BHB Quiescent Current - I , I All Inputs = 0V, I = I = 0 -50 -30 -11 -60 -10 A AHB BHB AHO BHO Qpump Output Current V = V = V = V = 10V DD CC AHB BHB AHB, BHB Operating Current I , I f = 500kHz, No Load 0.6 1.2 1.5 0.5 1.9 mA AHBO BHBO AHS, BHS, AHB, BHB Leakage I V = V = 80V, - 0.02 1.0 - 10 A HLK BHS AHS Current V = V = 93V AHB BHB AHB-AHS, BHB-BHS Qpump V -V I = I = 0, No Load 11.5 12.6 14.0 10.5 14.5 V AHB AHS AHB AHB Output Voltage V -V BHB BHS INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage V Full Operating Conditions - - 1.0 - 0.8 V IL High Level Input Voltage V Full Operating Conditions 2.5 - - 2.7 - V IH Input Voltage Hysteresis - 35 - - - mV Low Level Input Current I V = 0V, Full Operating Conditions -130 -100 -75 -135 -65 A IL IN High Level Input Current I V = 5V, Full Operating Conditions -1 - +1 -10 +10 A IH IN TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V , V I = I = -100A 4.9 5.1 5.3 4.8 5.4 V HDEL LDEL HDEL LDEL GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage V I = 100mA 0.7 0.85 1.0 0.5 1.1 V OL OUT High Level Output Voltage V -V I = -100mA 0.8 0.95 1.1 0.5 1.2 V CC OH OUT Peak Pullup Current I + V = 0V 1.7 2.6 3.8 1.4 4.1 A O OUT FN3659 Rev 8.00 Page 4 of 17 September 15, 2015

HIP4081A Electrical Specifications V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 100K and DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL T = 25°C, Unless Otherwise Specified (Continued) A T = -40°C TO JS T = 25°C 125°C J PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Peak Pulldown Current I - V = 12V 1.7 2.4 3.3 1.3 3.6 A O O UT Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V Switching Specifications V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 10K, DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL C = 1000pF. L T = -40°C JS T = 25°C TO 125°C J PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay T - 30 60 - 80 ns LPHL (ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay T - 35 70 - 90 ns HPHL (AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay T R = R = 10K - 45 70 - 90 ns LPLH HDEL LDEL (ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay T R = R = 10K - 60 90 - 110 ns HPLH HDEL LDEL (AHI-AHO, BHI-BHO) Rise Time T - 10 25 - 35 ns R Fall Time T - 10 25 - 35 ns F Turn-on Input Pulse Width T R = R = 10K 50 - - 50 - ns PWIN-ON HDEL LDEL Turn-off Input Pulse Width T R = R = 10K 40 - - 40 - ns PWIN-OFF HDEL LDEL Turn-on Output Pulse Width T R = R = 10K 40 - - 40 - ns PWOUT-ON HDEL LDEL Turn-off Output Pulse Width T R = R = 10K 30 - - 30 - ns PWOUT-OFF HDEL LDEL Disable Turn-off Propagation Delay T - 45 75 - 95 ns DISLOW (DIS - Lower Outputs) Disable Turn-off Propagation Delay T - 55 85 - 105 ns DISHIGH (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay T - 40 70 - 90 ns DLPLH (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) T 240 410 550 200 600 ns REF-PW Disable to Upper Enable (DIS - AHO and BHO) T - 450 620 - 690 ns UEN TRUTH TABLE INPUT OUTPUT ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO X X X 1 0 0 1 X 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 X X 1 X 0 0 NOTE: X signifies that input can be either a “1” or “0”. FN3659 Rev 8.00 Page 5 of 17 September 15, 2015

HIP4081A Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V ). DD 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than V ). DD 4 V Chip negative supply, generally will be ground. SS 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V ). DD 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V ). DD 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than V ). DD 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V to set timing current that defines the turn-on delay of SS both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V to set timing current that defines the turn-on delay of SS both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 V Positive supply to gate drivers. Must be same potential as V (Pin 16). Connect to anodes of two bootstrap diodes. CC DD 16 V Positive supply to lower gate drivers. Must be same potential as V (Pin 15). De-couple this pin to V (Pin 4). DD CC SS 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN3659 Rev 8.00 Page 6 of 17 September 15, 2015

HIP4081A Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL THPHL U/V = DIS = 0 XLI XHI XLO XHO THPLH TLPLH TR TF (10% - 90%) (10% - 90%) FIGURE 1. INDEPENDENT MODE U/V = DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO (10% - 90%) (10% - 90%) FIGURE 2. BISTATE MODE TDLPLH TDIS U/V OR DIS TREF-PW XLI XHI XLO XHO TUEN FIGURE 3. DISABLE FUNCTION FN3659 Rev 8.00 Page 7 of 17 September 15, 2015

HIP4081A Typical Performance Curves V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 100K DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL and T = 25°C, Unless Otherwise Specified A 11.0 14.0 10.5 A) 12.0 A) m m T ( T ( 10.0 EN 10.0 EN R R R R U U 9.5 C 8.0 C Y Y L L P P P P 9.0 U 6.0 U S S D D D D I 4.0 I 8.5 2.0 8.0 6 8 10 12 14 0 100 200 300 400 500 600 700 800 900 1000 VDD SUPPLY VOLTAGE (V) SWITCHING FREQUENCY (kHz) FIGURE 4. QUIESCENT I SUPPLY CURRENT vs V SUPPLY FIGURE 5. I , NO-LOAD I SUPPLY CURRENT vs DD DD DDO DD VOLTAGE FREQUENCY (kHz) 30.0 5.0 A) 125°C m T ( 25.0 75°C EN A) 4.0 R m 25°C UR 20.0 T ( C N 0°C AS RE 3.0 BI 15.0 UR -40°C Y C UPPL 10.0 PPLY 2.0 S U G S N C ATI 5.0 IC 1.0 O L F 0.0 0 100 200 300 400 500 600 700 800 900 1000 0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FIGURE 7. I , NO-LOAD I SUPPLY CURRENT vs CCO CC FREQUENCY (LOAD = 1000pF) FREQUENCY (kHz) TEMPERATURE 2.5 -90 A) m A) NT ( 2 T ( E N R E R R -100 U R AS C 1.5 T CU Y BI NPU PL 1 L I P E -110 U V S E NG W L TI 0.5 O A L O L F -120 -50 -25 0 25 50 75 100 125 0 200 400 600 800 1000 JUNCTION TEMPERATURE (°C) SWITCHING FREQUENCY (kHz) FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL CURRENT vs FREQUENCY vs TEMPERATURE FN3659 Rev 8.00 Page 8 of 17 September 15, 2015

HIP4081A Typical Performance Curves V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 10K DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL and T = 25°C, Unless Otherwise Specified A V) E ( 15.0 80 G A T L P VO 14.0 ns) 70 UM AY ( E P 13.0 EL 60 G D R N A O G CH 12.0 GATI 50 N A ATI OP O R L 11.0 P 40 F D A O L 10.0 O- 30 N -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION VOLTAGE vs TEMPERATURE DELAY T vs TEMPERATURE DISHIGH 525 80 ON DELAY (ns) 457050 ON DELAY (ns) 6700 GATI GATI 50 PROPA 450 PROPA 40 425 30 -50 -25 0 25 50 75 100 125 150 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 12. DISABLE TO UPPER ENABLE, T , FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION UEN PROPAGATION DELAY vs TEMPERATURE DELAY T vs TEMPERATURE DISLOW 80 450 70 WIDTH (ns) 425 DELAY (ns) 60 E 400 N 50 S O UL ATI P G H A 40 S P E 375 O R R F P E 30 R 350 -50 -25 0 25 50 75 100 125 150 20 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 14. T REFRESH PULSE WIDTH vs FIGURE 15. DISABLE TO LOWER ENABLE T REF-PW DLPLH TEMPERATURE PROPAGATION DELAY vs TEMPERATURE FN3659 Rev 8.00 Page 9 of 17 September 15, 2015

HIP4081A Typical Performance Curves V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = 10K DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL and T = 25°C, Unless Otherwise Specified (Continued) A 80 80 70 70 ns) s) LAY ( 60 AY (n 60 E L D E ATION 50 TION D 50 G A PA 40 AG 40 O P R O P R 30 P 30 20 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY T vs HPHL FIGURE 17. UPPER TURN-ON PROPAGATION DELAY T vs HPLH TEMPERATURE TEMPERATURE 80 80 70 70 s) s) n n AY ( 60 AY ( 60 L L E E D D ON 50 ON 50 TI TI A A G G A 40 A 40 P P O O R R P P 30 30 20 20 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY T FIGURE 19. LOWER TURN-ON PROPAGATION DELAY T vs LPHL LPLH vs TEMPERATURE TEMPERATURE 13.5 13.5 ns) 12.5 s) 12.5 ME ( E (n LL TI 11.5 E TIM 11.5 A S DRIVE F 10.5 N-ON RI 10.5 GATE 9.5 TUR 9.5 8.5 8.5 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE FN3659 Rev 8.00 Page 10 of 17 September 15, 2015

HIP4081A Typical Performance Curves V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL 100K and T = 25°C, Unless Otherwise Specified A 6.0 1500 V) 1250 E ( G 5.5 A OLT V) 1000 V m PUT 5.0 (OH 750 L IN - VC -40°C E C D V 500 0°C L EL, 4.5 25°C D H 250 75°C 4.0 125°C 0 -40 -20 0 20 40 60 80 100 120 10 12 14 JUNCTION TEMPERATURE (°C) BIAS SUPPLY VOLTAGE (V) FIGURE 22. V , V VOLTAGE vs TEMPERATURE FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE V - V vs BIAS LDEL HDEL CC OH SUPPLY AND TEMPERATURE AT 100mA 1500 3.5 3.0 1250 A) T ( EN 2.5 1000 R R U V) C 2.0 m K V (OL 750 -40°C E SIN 1.5 V 500 0°C RI D 1.0 25°C TE A 250 75°C G 0.5 125°C 0 0.0 10 12 14 6 7 8 9 10 11 12 13 14 15 16 BIAS SUPPLY VOLTAGE (V) VDD, VCC, VAHB, VBHB (V) FIGURE 24. LOW LEVEL OUTPUT VOLTAGE V vs BIAS FIGURE 25. PEAK PULLDOWN CURRENT I vs BIAS SUPPLY OL O SUPPLY AND TEMPERATURE AT 100mA VOLTAGE 3.5 500 10,000pF 3.0 A) 200 T (A) T (m 100 3,000pF EN 2.5 EN 50 1,000pF R R R R U U 20 100pF C 2.0 C K S 10 N A SI 1.5 BI 5 E E V G RI A 2 E D 1.0 OLT 1 T V GA 0.5 W 0.5 O L 0.2 0.0 0.1 6 7 8 9 10 11 12 13 14 15 16 1 2 5 10 20 50 100 200 500 1000 VDD, VCC, VAHB, VBHB (V) SWITCHING FREQUENCY (kHz) FIGURE 26. PEAK PULLUP CURRENT I vs BIAS SUPPLY FIGURE 27. LOW VOLTAGE BIAS CURRENT I (LESS O+ DD VOLTAGE QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE FN3659 Rev 8.00 Page 11 of 17 September 15, 2015

HIP4081A Typical Performance Curves V = V = V = V = 12V, V = V = V = V = V = 0V, R = R = DD CC AHB BHB SS ALS BLS AHS BHS HDEL LDEL 100K and T = 25°C, Unless Otherwise Specified (Continued) A 1000 500 A)  T ( N 200 E R R U C 100 T F HI S 50 L- E V E L 20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE 9.0 150 UV+ V) (DD 8.8 120 V E, G s) A n 90 LT E ( O 8.6 M LY V D-TI P A 60 P E U UV- D S S 8.4 A BI 30 8.2 50 25 0 25 50 75 100 125 150 0 10 50 100 150 200 250 TEMPERATURE (°C) HDEL/LDEL RESISTANCE (k) FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE FN3659 Rev 8.00 Page 12 of 17 September 15, 2015

SF H epN3 IP temb659 IN2 IN1 +12V POWER SECTION 4081 eR B+ A r 15, 201ev 8.00 CONSTERCOTILO LNOGIC R29 PR5 +C6 DRIVER SECTION CR2 R21 1 Q1 2 C8 5 JM HIP4080A/81A 3 Q3 2 JMPR1 U1 C4 1 1 2 OUT/BLI U2 1 BHB BHO 20 R22 2 HEN/BHI BHS 19 3 CD4069UB 3 DIS BLO 18 L1 AO 13 U2 12 JMPR2IN+/ALI 45 OVSUST/BLI VBDLDS 1167 +12V R23 1 Q2 2 C1 L2 BO CD4069UB 67 IINN-+//AAHLII AVCLCS 1145 C2 5 6 JMPR3HEN/BHI 8 HDEL ALO 13 3 U2 9 LDEL AHS 12 Q4 2 10 11 R24 1 CD4069UB R33 R34 AHB AHO 3 3 JMPR4 3 11 10 IN-/AHI 2 2 CR1 U2 CW CW 1 1 C3 CD4069UB R30 R31 CX CY C5 COM ENABLE IN 3 4 O I U2 ALS BLS R32 CD4069UB NOTES: 1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 9 8 U2 O 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT CD4069UB LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4. FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC P a g e 1 3 o f 1 7

SF H epN3 IP tem659 408 b 1 eR A r 1ev 5, 2 8.0 00 1 5 GND +12V B+ COM R29 C7+ JMPR5 R27 R28 R26 C6+ CR2 C8 C1 AO 32 Q1 Q3 R U1 C4 R22 1 1 BHO R24 2 U2 DIS 1 BLO C IN1 0/8 BLS L1 L2 BO 8 I JMPR1 40 JMPR2 P O JMPR3 HI ALS R23 Q2 Q4 IN2 JMPR4 ALO 1 1 R21 O AHO LDEL C3 L E D 5 ALS H CR1 C CX CY R33 R34 0 1 BLS 3 3 R R FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN P a g e 1 4 o f 1 7

HIP4081A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 15, 2015 FN3659.8 Updated Ordering Information Table on page1. Added Revision History and About Intersil sections. Updated POD M20.3 from rev 1 to rev 3. Changes since rev 1: Top View: Corrected "7.50 BSC" to "7.60/7.40" (no change from rev 2; error was introduced in conversion) Changed "10.30 BSC" to "10.65/10.00" (no change from rev 2; error was introduced in conversion) Side View: Changed "12.80 BSC" to "13.00/12.60" (no change from rev 2; error was introduced in conversion) Changed "2.65 max" to "2.65/2.35" (no change from rev 2; error was introduced in conversion) Changed Note 1 from "ANSI Y14.5M-1982." to "ASME Y14.5M-1994" Updated to new POD format by moving dimensions from table onto drawing and adding land pattern About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support FN3659 Rev 8.00 Page 15 of 17 September 15, 2015

HIP4081A Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.55 1.77 8 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 B e eC C D 0.980 1.060 24.89 26.9 5 e D1 0.005 - 0.13 - 5 B 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 NOTES: e 0.100 BSC 2.54 BSC - 1. Controlling Dimensions: INCH. In case of conflict between English e 0.300 BSC 7.62 BSC 6 and Metric dimensions, the inch dimensions control. A e - 0.430 - 10.92 7 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. B 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 L 0.115 0.150 2.93 3.81 4 of Publication No. 95. N 20 20 9 4. Dimensions A, A1 and L are measured with the package seated in Rev. 0 12/93 JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpen- dicular to datum -C- . 7. e and e are measured at the lead tips with the leads uncon- B C strained. e must be zero or greater. C 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2003-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3659 Rev 8.00 Page 16 of 17 September 15, 2015

HIP4081A Package Outline Drawing M20.3 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 3, 2/11 20 INDEX AREA 10.65 0.25 (0.10) M B M 10.00 7.60 3 7.40 1 2 3 TOP VIEW 2 SEATING PLANE 1132..0600 2.65 5 1.27 2.35 0.40 0.75 x 45° 1.27 7 0.49 0.30 0.25 BSC 0.35 MAX 8° 0.25 (0.10) M C A M B S MAX 0.10 (0.004) 0.32 SIDE VIEW DETAIL "X" 0.23 NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. (0.60) 1.27 BSC 2. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 20 0.15mm (0.006 inch) per side. (2.00) 3. Dimension does not include interlead lash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.40mm) 5. Dimension is the length of terminal for soldering to a substrate. 6. Terminal numbers are shown for reference only. 7. The lead width as measured 0.36mm (0.14 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 8. Controlling dimension: MILLIMETER. 1 2 3 9. Dimensions in ( ) for reference only. TYPICAL RECOMMENDED LAND PATTERN 10. JEDEC reference drawing number: MS-013-AC. FN3659 Rev 8.00 Page 17 of 17 September 15, 2015