DATASHEET HIN232A FN4316 High Speed +5V Powered RS-232 Transmitters/Receivers Rev 1.00 March 13, 2006 The HIN232A high-speed RS-232 transmitter/receiver Features interface circuit meets all ElA high-speed RS-232E and V.28 • Meets All RS-232E and V.28 Specifications specifications, and is particularly suited for those applications where 12V is not available. They require a • Requires Only 0.1F or Greater External Capacitors single +5V power supply and feature onboard charge pump • High Data Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 230kbit/s voltage converters which generate +10V and -10V supplies from the 5V supply. • Requires Only Single +5V Power Supply The drivers feature true TTL/CMOS input compatibility, slew • Onboard Voltage Doubler/Inverter rate-limited output, and 300 power-off source impedance. • Low Power Consumption (Typ) . . . . . . . . . . . . . . . . . 5mA The receivers can handle up to 30V input, and have a 3k • Multiple Drivers to 7k input impedance. The receivers also feature hysteresis to greatly improve noise rejection. - 10V Output Swing for +5V lnput - 300 Power-Off Source Impedance Ordering Information - Output Current Limiting - TTL/CMOS Compatible TEMP. PKG. PART RANGE DWG. • Multiple Receivers PART NO. MARKING (oC) PACKAGE # - 30V Input Voltage Range HIN232ACB 232ACB 0 to 70 16 Ld SOIC M16.3 - 3k to 7k Input Impedance HIN232ACB-T 232ACB 0 to 70 16 Ld SOIC M16.3 - 0.5V Hysteresis to Improve Noise Rejection Tape and Reel HIN232ACBZ 232ACBZ 0 to 70 16 Ld SOIC M16.3 • Pb-Free Plus Anneal Available (RoHS Compliant) (See Note) (Pb-free) Applications HIN232ACBZ-T 232ACBZ 0 to 70 16 Ld SOIC M16.3 (See Note) Tape and Reel • Any System Requiring High-Speed RS-232 (Pb-free) Communication Ports HIN232ACBN 232ACBN 0 to 70 16 Ld SOIC (N) M16.15 - Computer - Portable, Mainframe, Laptop HIN232ACBN-T 232ACBN 0 to 70 16 Ld SOIC (N) M16.15 - Peripheral - Printers and Terminals Tape and Reel - Instrumentation, UPS HIN232ACBNZ 232ACBNZ 0 to 70 16 Ld SOIC (N) M16.15 - Modems (See Note) (Pb-free) HIN232ACBNZ-T 232ACBNZ 0 to 70 16 Ld SOIC (N) M16.15 (See Note) Tape and Reel (Pb-free) HIN232ACP HIN232ACP 0 to 70 16 Ld PDIP E16.3 HIN232ACPZ 232ACPZ 0 to 70 16 Ld PDIP* E16.3 (See Note) (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Selection Table NUMBER OF NUMBER OF NUMBER OF 0.1F LOW POWER NUMBER OF PART POWER SUPPLY RS-232 RS-232 EXTERNAL SHUTDOWN/TTL THREE- RECEIVERS ACTIVE NUMBER VOLTAGE DRIVERS RECEIVERS CAPACITORS STATE IN SHUTDOWN HIN232A +5V 2 2 4 Capacitors No/No 0 FN4316 Rev 1.00 Page 1 of 10 March 13, 2006

HIN232A Pinout HIN232A (PDIP, SOIC) TOP VIEW +5V C1+ 1 16 VCC 16 V+ 2 15 GND C1- 3 14 T1OUT VCC CC22+- 45 1132 RR11IONUT 0.1F +13 C1+ VOLT+A5GVE T OIN V10EVRTER V+ 2 +0.1F C1- V- 6 11 T1IN 4 C2+ T2OUT 7 10 T2IN 0.1F +5 VOL+T1A0GVE T ION V-1E0RVTER V- 6 R2IN 8 9 R2OUT C2- +0.1F +5V T1 11 400k 14 T1IN T1OUT +5V T2 10 400k 7 T2IN T2OUT 12 13 R1OUT R1IN R1 5k 9 8 R2OUT R2IN R2 5k GND 15 Pin Descriptions PIN FUNCTION VCC Power Supply Input 5V 10%. V+ Internally generated positive supply (+10V nominal). V- Internally generated negative supply (-10V nominal). GND Ground Lead. Connect to 0V. C1+ External capacitor (+ terminal) is connected to this lead. C1- External capacitor (- terminal) is connected to this lead. C2+ External capacitor (+ terminal) is connected to this lead. C2- External capacitor (- terminal) is connected to this lead. TIN Transmitter Inputs. These leads accept TTL/CMOS levels. An internal 400k pull-up resistor to VCC is connected to each lead. TOUT Transmitter Outputs. These are RS-232 levels (nominally 10V). RIN Receiver Inputs. These inputs accept RS-232 input levels. An internal 5k pull-down resistor to GND is connected to each input. ROUT Receiver Outputs. These are TTL/CMOS levels. FN4316 Rev 1.00 Page 2 of 10 March 13, 2006

HIN232A Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) <VCC < 6V Thermal Resistance (Typical, Note 1) JA (oC/W) V+ to Ground. . . . . . . . . . . . . . . . . . . . . . . . (VCC -0.3V) <V+ < 12V 16 Ld SOIC (N) Package. . . . . . . . . . . . . . . . . . . . . 105 V- to Ground. . . . . . . . . . . . . . . . . . . . . . . .-12V < V- < (GND +0.3V) 16 Ld SOIC (W) Package. . . . . . . . . . . . . . . . . . . . . 110 Input Voltages 16 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 85 TIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V < VIN < (V+ +0.3V) Maximum Junction Temperature (Plastic Package) . . . . . .150oC RIN30V Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC Output Voltages Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC TOUT . . . . . . . . . . . . . . . . . . . .(V- -0.3V) < VTXOUT < (V+ +0.3V) (SOIC - Lead Tips Only) ROUT . . . . . . . . . . . . . . . . . (GND -0.3V) < VRXOUT < (V+ +0.3V) *Pb-free PDIPs can be used for through hole wave solder processing Short Circuit Duration only. They are not intended for use in Reflow solder processing TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous applications. ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous Operating Conditions ESD Classification. . . . . . . . . . . . . . . . . . . . See Specification Table Temperature Range HIN232ACX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: VCC = +5V 10%, C1-C4 = 0.1F; TA = Operating Temperature Range PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SUPPLY CURRENTS Power Supply Current, ICC No Load, TA = 25oC - 5 10 mA LOGIC AND TRANSMITTER INPUTS, RECEIVER OUTPUTS Input Logic Low, VlL TIN - - 0.8 V Input Logic High, VlH TIN 2.0 - - V Transmitter Input Pullup Current, IP TIN = 0V - 15 200 A TTL/CMOS Receiver Output Voltage Low, VOL IOUT = 3.2mA - 0.1 0.4 V TTL/CMOS Receiver Output Voltage High, VOH IOUT = -1mA 3.5 4.6 - V RECEIVER INPUTS RS-232 Input Voltage Range, VIN -30 - +30 V Receiver Input Impedance, RIN VIN = 3V, TA = 25oC 3.0 5.0 7.0 k Receiver Input Low Threshold, VIN (H-L) VCC = 5V, TA = 25oC - 1.2 - V Receiver Input High Threshold, VIN (L-H) VCC = 5V, TA = 25oC - 1.7 2.4 V Receiver Input Hysteresis, VHYST VCC = 5V 0.2 0.5 1.0 V TIMING CHARACTERISTICS Transmitter, Receiver Propagation Delay, tPD - 0.5 10 s Transition Region Slew Rate, SRT RL = 3k, CL = 1000pF, Measured from +3V to 3 20 45 V/s -3V or -3V to +3V, (Note 2) 1 Transmitter Switching TRANSMITTER OUTPUTS Output Voltage Swing, TOUT Transmitter Outputs, 3k to Ground 5 9 10 V Output Resistance, TOUT VCC = V+ = V- = 0V, VOUT = 2V 300 - -  RS-232 Output Short Circuit Current, ISC TOUT Shorted to GND - 10 - mA ESD PERFORMANCE RS-232 Pins Human Body Model - 15 - kV (TOUT, RIN) IEC1000-4-2 Contact Discharge - 8 - kV IEC1000-4-2 Air Gap (Note 3) - 15 - kV All Other Pins Human Body Model - 2 - kV NOTES: 2. Guaranteed by design. 3. Meets level 4. FN4316 Rev 1.00 Page 3 of 10 March 13, 2006

HIN232A Test Circuits (HIN232A) +4.5V TO +5.5V INPUT - 1 C1+ VCC 16 0.1F C3 + 2 V+ GND 15 + 1 C1+ VCC 16 3 C1- T1OUT 14 0.1CF1 - 2 V+ GND 15 3k 4 C2+ R1IN 13 3 C1- T1OUT 14 T1 OUTPUT 5 C2- R1OUT 12 0.1F+ 4 C2+ R1IN 13 RS-232 30V INPUT 6 V- T1IN 11 C2- 5 C2- R1OUT 12 TTL/CMOS OUTPUT 7 T2OUT T2IN 10 + - 6 V- T1IN 11 TTL/CMOS INPUT 8 R2IN R2OUT 9 0.1F C4 3k 7 T2OUT T2IN 10 TTL/CMOS INPUT T2 8 R2IN R2OUT 9 TTL/CMOS OUTPUT ROUT = VIN/I T2OUT OUTPUT T1OUT RS-232 30V INPUT VIN = 2V A FIGURE 1. GENERAL TEST CIRCUIT FIGURE 2. POWER-OFF SOURCE RESISTANCE CONFIGURATION VOLTAGE DOUBLER VOLTAGE INVERTER S1 C1+ S2 V+ = 2VCC S5 C2+ S6 VCC GND + + + + C1 C3 C2 C4 - - - - GND VCC GND V- = - (V+) S3 C1- S4 S7 C2- S8 RC OSCILLATOR FIGURE 3. CHARGE PUMP Detailed Description (V+) is approximately 200, and the output impedance of the voltage inverter section (V-) is approximately 450. A typical The HIN232A is a high-speed RS-232 transmitter/receiver that application uses 0.1F capacitors for C1-C4, however, the is powered by a single +5V power supply, features low power value is not critical. Increasing the values of C1 and C2 will consumption, and meets all ElA RS232C and V.28 lower the output impedance of the voltage doubler and inverter, specifications. The circuit is divided into three sections: the increasing the values of the reservoir capacitors, C3 and C4, charge pump, transmitter, and receiver. lowers the ripple on the V+ and V- supplies. Charge Pump Transmitters An equivalent circuit of the charge pump is illustrated in Figure The transmitters are TTL/CMOS compatible inverters which 3. The charge pump contains two sections: The voltage translate the inputs to RS-232 outputs. The input logic threshold is doubler and the voltage inverter. Each section is driven by a two phase, internally generated clock to generate +10V and - about 26% of VCC, or 1.3V for VCC = 5V. A logic 1 at the input results in a voltage of between -5V and V- at the output, and a 10V. The nominal clock frequency is 125kHz. During phase logic 0 results in a voltage between +5V and (V+ -0.6V). Each one of the clock, capacitor C1 is charged to VCC. During transmitter input has an internal 400k pullup resistor so any phase two, the voltage on C1 is added to VCC, producing a unused input can be left unconnected and its output remains in its signal across C3 equal to twice VCC. During phase two, C2 is low state. The output voltage swing meets the RS-232C also charged to 2VCC, and then during phase one, it is specifications of 5V minimum with the worst case conditions of: inverted with respect to ground to produce a signal across C4 equal to -2VCC. The charge pump accepts input voltages up to all transmitters driving 3k minimum load impedance, VCC = 4.5V, and maximum allowable operating temperature. The 5.5V. The output impedance of the voltage doubler section FN4316 Rev 1.00 Page 4 of 10 March 13, 2006

HIN232A transmitters have an internally limited output slew rate which is TIN less than 30V/s. The outputs are short circuit protected and can OR be shorted to ground indefinitely. The powered down output RIN impedance is a minimum of 300 with 2V applied to the outputs TOUT VOH and VCC= 0V. ROORUT VOL Receivers tPHL tPLH The receiver inputs accept up to 30V while presenting the tPHL + tPLH AVERAGE PROPAGATION DELAY = 2 required 3k to 7k input impedance even if the power is off (VCC = 0V). The receivers have a typical input threshold of 1.3V FIGURE 6. PROPAGATION DELAY DEFINITION which is within the 3V limits, known as the transition region, of Application Information the RS-232 specifications. The receiver output is 0V to VCC. The output will be low whenever the input is greater than 2.4V and The HIN232A may be used for all RS-232 data terminal and high whenever the input is floating or driven between +0.8V and - communication links. It is particularly useful in applications 30V. The receivers feature 0.5V hysteresis (except during where 12V power supplies are not available for conventional shutdown) to improve noise rejection. RS-232 interface circuits. The applications presented represent typical interface configurations. V+ A simple duplex RS-232 port with CTS/RTS handshaking is VCC illustrated in Figure 7. Fixed output signals such as DTR (data 400k 300 terminal ready) and DSRS (data signaling rate select) is TXIN TOUT generated by driving them through a 5k resistor connected to GND < TXIN < VCC V- < VTOUT < V+ V+. V- In applications requiring four RS-232 inputs and outputs FIGURE 4. TRANSMITTER (Figure 8), note that each circuit requires two charge pump capacitors (C1 and C2) but can share common reservoir VCC capacitors (C3 and C4). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the RXIN ROUT reduction of the charge pump source impedance which -30V < RXIN < +30V 5k GND < VROUT < VCC effectively increases the output swing of the transmitters. GND FIGURE 5. RECEIVER +5V - + 1 16 CTR (20) DATA C1 + TERMINAL READY 0.1F - 3 DSRS (24) DATA HIN232A SIGNALING RATE 4 6 SELECT C2 + - 0.1F - 5 + RS-232 INPUTS AND OUTPUTS 11 T1 14 TD TD (2) TRANSMIT DATA T2 10 7 INPUTS RTS RTS (4) REQUEST TO SEND OUTPUTS 12 13 TTL/CMOS RD RD (3) RECEIVE DATA 9 R2 R1 8 CTS CTS (5) CLEAR TO SEND 15 SIGNAL GROUND (7) FIGURE 7. SIMPLE DUPLEX RS-232 PORT WITH CTS/RTS HANDSHAKING FN4316 Rev 1.00 Page 5 of 10 March 13, 2006

HIN232A 1 4 C1 + HIN232A + C2 0.1F - 3 5 - 0.1F 11 T1 14 TD TD (2) TRANSMIT DATA T2 10 7 INPUTS RTS RTS (4) REQUEST TO SEND OUTPUTS 12 13 TTL/CMOS RD RD (3) RECEIVE DATA 9 R2 R1 8 CTS CTS (5) CLEAR TO SEND 15 16 VCC 6 2 C4 C3 +5V + - + - V- V+ 0.2F 0.2F RS-232 6 2 INPUTS AND OUTPUTS 16 VCC HIN232A 1 4 C1 + + C2 0.1F - 3 5 - 0.1F 11 T1 14 DTR DTR (20) DATA TERMINAL READY T2 10 7 INPUTS DSRS DSRS (24) DATA SIGNALING RATE SELECT OUTPUTS 12 13 TTL/CMOS DCD DCD (8) DATA CARRIER DETECT 9 R2 R1 8 R1 R1 (22) RING INDICATOR 15 SIGNAL GROUND (7) FIGURE 8. COMBINING TWO HIN232As FOR 4 PAIRS OF RS-232 INPUTS AND OUTPUTS Typical Performance Curves 12 12 0.1F GE (V) 10 E (V) 10 LTA 8 TAG 8 V+ (VCC = 5V) O L V O LY 6 Y V 6 PP PL V+ (VCC = 4V) V- SU 4 SUP 4 V- (VCC = 4V) 2 2 TTAR A= N2S5MoCITTER OUTPUTS V- (VCC = 5V) OPEN CIRCUIT 0 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35 VCC |ILOAD| (mA) FIGURE 9. V- SUPPLY VOLTAGE vs VCC FIGURE 10. V+, V- OUTPUT VOLTAGE vs LOAD FN4316 Rev 1.00 Page 6 of 10 March 13, 2006

HIN232A Die Characteristics DIE DIMENSIONS 160 mils x 140 mils METALLIZATION Type: Al Thickness: 10kÅ 1kÅ SUBSTRATE POTENTIAL V+ PASSIVATION Type: Nitride over Silox Nitride Thickness: 8kÅ Silox Thickness: 7kÅ TRANSISTOR COUNT 238 PROCESS CMOS Metal Gate FN4316 Rev 1.00 Page 7 of 10 March 13, 2006

HIN232A Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.735 0.775 18.66 19.68 5 B e D1 0.005 - 0.13 - 5 B 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7 Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. N 16 16 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendic- ular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN4316 Rev 1.00 Page 8 of 10 March 13, 2006

HIN232A Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0926 0.1043 2.35 2.65 - 1 2 3 A1 0.0040 0.0118 0.10 0.30 - L B 0.013 0.0200 0.33 0.51 9 SEATING PLANE C 0.0091 0.0125 0.23 0.32 - -A- D 0.3977 0.4133 10.10 10.50 3 D A h x 45° E 0.2914 0.2992 7.40 7.60 4 -C- e 0.050 BSC 1.27 BSC -  H 0.394 0.419 10.00 10.65 - e A1 C h 0.010 0.029 0.25 0.75 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 16 16 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN4316 Rev 1.00 Page 9 of 10 March 13, 2006

HIN232A Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES MILLIMETERS IANRDEEAX H 0.25(0.010) M B M SYMBOL MIN MAX MIN MAX NOTES E A 0.053 0.069 1.35 1.75 - -B- A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 1 2 3 L C 0.007 0.010 0.19 0.25 - SEATING PLANE D 0.386 0.394 9.80 10.00 3 -A- E 0.150 0.157 3.80 4.00 4 D A h x 45o e 0.050 BSC 1.27 BSC - -C- H 0.228 0.244 5.80 6.20 - µ h 0.010 0.020 0.25 0.50 5 e A1 C L 0.016 0.050 0.40 1.27 6 B 0.10(0.004) N 16 16 7 0.25(0.010) M C A M B S  0o 8o 0o 8o - Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. © Copyright Intersil Americas LLC 2001-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4316 Rev 1.00 Page 10 of 10 March 13, 2006