DATASHEET HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 FN3127 CMOS Analog Switches Rev 7.00 June 16, 2016 This family of CMOS analog switches offers low resistance Features switching performance for analog voltages up to the supply • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . 15V rails and for signal currents up to 80mA. “ON” resistance is low and stays reasonably constant over the full range of • Low “ON” Resistance. . . . . . . . . . . . . . . . . . . . . . . . . 25 operating signal voltage and current. rON remains • High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA exceptionally constant for input voltages between +5V and -5V and currents up to 50mA. Switch impedance also • Break-Before-Make Switching changes very little over temperature, particularly between - Turn-On Time. . . . . . . . . . . . . . . . . . . . . . . . . . . .370ns 0oC and 75oC. rON is nominally 25 for HI-5049 and - Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns HI-5051 and 50 for HI-5042 through HI-5047. • No Latch-Up All devices provide break-before-make switching and are • Input MOS Gates are Protected from Electrostatic TTL and CMOS compatible for maximum application Discharge versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with • DTL, TTL, CMOS, PMOS Compatible very low input and output leakage currents (0.8nA at 25oC). • Pb-Free Available (RoHS Compliant) This family of switches also features very low power operation (1.5mW at 25oC). Applications There are 7 devices in this switch series which are • High Frequency Switching differentiated by type of switch action and value of rON (see • Sample and Hold Functional Description Table). The HI-504X and HI-505X series switches can directly replace IH-5040 series devices, and are • Digital Filters functionally compatible with the DG180 and DG190 family • Operational Amplifier Gain Switching Functional Diagram S A N P D Functional Description PART NUMBER TYPE rON HI-5042 SPDT 50 HI-5043 Dual SPDT 50 HI-5047 4PST 50 HI-5049 Dual DPST 25 HI-5051 Dual SPDT 25 FN3127 Rev 7.00 Page 1 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Ordering Information PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. DWG. # HI1-5042-2 -55 to 125 16 Ld CERDIP F16.3 HI1-5043-2 -55 to 125 16 Ld CERDIP F16.3 HI1-5043-5 0 to 75 16 Ld CERDIP F16.3 HI3-5043-5 0 to 75 16 Ld PDIP E16.3 HI3-5043-5Z 0 to 75 16 Ld PDIP* F16.3 (See Note) (Pb-free) HI9P5043-5 0 to 75 16 Ld SOIC M16.15 HI9P5043-5Z 0 to 75 16 Ld SOIC M16.15 (See Note) (Pb-free) HI1-5047-5 0 to 75 16 Ld CERDIP F16.3 HI1-5049-5 0 to 75 16 Ld CERDIP F16.3 HI1-5051-2 -55 to 125 16 Ld CERDIP F16.3 HI1-5051-5 0 to 75 16 Ld CERDIP F16.3 HI3-5051-5 0 to 75 16 Ld PDIP E16.3 HI3-5051-5Z (No longer available, recommended 0 to 75 16 Ld PDIP * E16.3 replacement: HI9P5051-9Z (See Note) (Pb-free) HI9P5051-9 -40 to 85 16 Ld SOIC M16.15 HI9P5051-9Z -40 to 85 16 Ld SOIC M16.15 (See Note) (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT) (SWITCHES SHOWN FOR LOGIC “0” INPUT) Single Control Dual Control SPDT 4PST DUAL SPDT DUAL DPST HI-5042 (50) HI-5047 (50) HI-5043 (50), HI-5051 (25) HI-5049 (25) D1 1 16 S1 D2 1 16 S2 D1 1 16 S1 D1 1 16 S1 2 15 A 2 15 A 2 15 A1 2 15 A1 D2 3 14 V- D1 3 14 V- D3 3 14 V- D3 3 14 V- S2 4 13 VR S1 4 13 VR S3 4 13 VR S3 4 13 VR 5 12 VL S4 5 12 VL S4 5 12 VL S4 5 12 VL 6 11 V+ D4 6 11 V+ D4 6 11 V+ D4 6 11 V+ 7 10 7 10 7 10 A2 7 10 A2 8 9 D3 8 9 S3 D2 8 9 S2 D2 8 9 S2 NOTE: Unused pins may be internally connected. Ground all NOTE: Unused pins may be internally connected. Ground all unused pins. unused pins. FN3127 Rev 7.00 Page 2 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT) SPDT DUAL SPDT HI-5042 (50) HI-5043 (50) VL V+ VL V+ 12 11 12 11 16 1 16 1 S1 D1 S1 4 3 D1 S3 D3 4 3 15 S2 D2 A1 10 A2 15 9 8 A S2 D2 5 6 S4 D4 13 14 13 14 VR V- VR V- 4PST DUAL DPST DUAL SPDT HI-5047 (50) HI-5049 (25) HI-5051 (25) VL V+ VL V+ VL V+ 12 11 12 11 12 11 4 3 16 1 16 1 S1 16 1 D1 S1 4 3 D1 S1 4 3 D1 S2 D2 S3 15 D3 S3 15 D3 S3 9 8 D3 A1 A1 5 6 10 10 S4 15 D4 A2 9 8 A2 9 8 A S2 5 6 D2 S2 5 6 D2 S4 D4 S4 D4 13 14 13 14 13 14 VR V- VR V- VR V- FN3127 Rev 7.00 Page 3 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Schematic Diagrams V+ P15 P16 VL A P14  35 R6 R3 QN1 N13 QP1 QP3 QP4 A  A A A 0    0 5 5 5 1 2 2 2 R4 QP5 QP6 P13 QP8 A V+ A TO VR’ 25 R5 6 A R2 1  QP7 QN2 25 R7 VR QP2 V- N14 N15 N16 to VL’ NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits. TTL/CMOS REFERENCE CIRCUIT (NOTE) A1 (A2) N1 V+ IN N3 OUT P2 N2 V- P1 A1 (A2) SWITCH CELL V+ P3 P5 P1 V+ P4 N1 P8 P9 P10 P11 P12 P6 P7 D1 A1 R4 VR' A1 A 200 VL' A2 D2 A2 N6 N7 N8 N9 N10 N11 N12 P2 V- N4 N2 N5 N3 V- NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown. DIGITAL INPUT BUFFER AND LEVEL SHIFTER FN3127 Rev 7.00 Page 4 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) VR to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+, V- CERDIP Package. . . . . . . . . . . . . . . . . 75 22 Digital and Analog Input Voltage . . . . . . . . . . . .(V+) +4V to (V-) -4V SOIC Package. . . . . . . . . . . . . . . . . . . 110 N/A Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA PDIP Package* . . . . . . . . . . . . . . . . . . 90 N/A Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC Operating Conditions Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC Temperature Range HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC (SOIC - Lead Tips Only) HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL=5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins are Grounded -2 -5, -9 TEST TEMP PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Switch ON Time, tON (Note 5) 25 - 370 500 - 370 500 ns Switch OFF Time, tOFF (Note 5) 25 - 280 500 - 280 500 ns Charge Injection, Q (Note 3) 25 - 5 20 - 5 - mV OFF Isolation (Note 4) 25 75 80 - - 80 - dB Crosstalk (Note 4) 25 -80 -88 - - -88 - dB Input Switch Capacitance, CS(OFF) 25 - 11 - - 11 - pF Output Switch Capacitance, CD(OFF) 25 - 11 - - 11 - pF Output Switch Capacitance, CD(ON) 25 - 22 - - 22 - pF Digital Input Capacitance, CA 25 - 5 - - 5 - pF Drain To Source Capacitance, CDS(OFF) 25 - 0.5 - - 0.5 - pF DIGITAL INPUT CHARACTERISTICS Input Low Threshold, VAL Full - - 0.8 - - 0.8 V Input High Threshold, VAH Full 2.4 - - 2.4 - - V Input Leakage Current (High or Low), IA Full - 0.01 1.0 - 0.01 1.0 A ANALOG SWITCH CHARACTERISTICS Analog Signal Range Full -15 - +15 -15 - +15 V ON Resistance, rON HI-5042 to HI-5047 (Note 2) 25 - 50 75 - 50 75  Full - - 150 - - 150  HI-5049, HI-5051 (Note 2) 25 - 25 45 - 25 45  Full - - 50 - - 50  Channel-to-Channel Match, rON HI-5042 to HI-5047 25 - 2 10 - 2 10  HI-5049, HI-5051 25 - 1 5 - 1 5  FN3127 Rev 7.00 Page 5 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Electrical Specifications Supplies = +15V, -15V; VR = 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL=5V, Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics, Unused Pins are Grounded (Continued) -2 -5, -9 TEST TEMP PARAMETER CONDITIONS (oC) MIN TYP MAX MIN TYP MAX UNITS OFF Input or Output Leakage Current, 25 - 0.8 2 - 0.8 2 nA IS(OFF) = ID(OFF) Full - 100 200 - 100 200 nA ON Leakage Current, ID(ON) 25 - 0.01 2 - 0.01 2 nA Full - 2 200 - 2 200 nA POWER REQUIREMENTS Quiescent Power Dissipation, PD 25 - 1.5 - - 1.5 - mW I+, I-, IL, IR 25 - - 0.2 - - 0.3 mA I+, +15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA I-, -15V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA IL, +5V Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA IR, Ground Quiescent Current (Note 5) Full - - 0.3 - - 0.5 mA NOTES: 2. VOUT = 10V, IOUT = 1mA. 3. VIN = 0V, CL = 10nF. 4. RL = 100, f = 100kHz, VIN = 2.0VP-P, CL = 5pF. 5. VAL = 0V, VAH = 5V. Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH=3V and VAL = 0.8V Unless Otherwise Specified 1mA V2 rON = 1mA V2 IN OUT VIN FIGURE 1A. TEST CIRCUIT 80 1.2 E C N ON RESISTANCE () 642000 VV-+ = = - +1100VV VVV-++ = == - ++1211V25VV RMALIZED ON RESISTAo(REFERRED TO 25C) 1100....1098 VIN = 0V V- = -15V O N 0.7 0 0.6 -15 -10 -5 0 5 10 15 -50 -25 0 25 50 75 100 125 ANALOG SIGNAL LEVEL (V) TEMPERATURE (oC) FIGURE 1B. ON RESISTANCE vs ANALOG SIGNAL LEVEL FIGURE 1C. NORMALIZED ON RESISTANCE vs TEMPERATURE FIGURE 1. ON RESISTANCE FN3127 Rev 7.00 Page 6 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH=3V and VAL = 0.8V Unless Otherwise Specified (Continued) 100nA OFF LEAKAGE CURRENT IS(OFF) ID(OFF) IN OUT A A 10nA IS(OFF) = ID(OFF) NT 10V 10V E R R CU ON LEAKAGE CURRENT E 1nA G A IN OUT K EA ID(ON) L100pA A ID(ON) 10pA 10V 25 50 75 100 125 TEMPERATURE (oC) FIGURE 2A. LEAKAGE CURRENTS vs TEMPERATURE FIGURE 2B. TEST CIRCUITS FIGURE 2. LEAKAGE CURRENTS 1.4 E C N 1.3 TAA) Sm SI1 EO D ON RRED T 1.2 IN OUT I ER RMALIZ(REFE 1.1 VIN rON = V-----II--N-- O N 1.0 0 20 40 60 80 ANALOG CURRENT (mA) FIGURE 3A. NORMALIZED ON RESISTANCE vs ANALOG FIGURE 3B. TEST CIRCUIT CURRENT FIGURE 3. NORMALIZED ON RESISTANCE 200 B) IN OUT N (d 160 VIN VOUT O 50 ATI 120 RL = 100 2VP-P RL L O S F I 80 F O  VIN  40 RL = 10k OFF ISOLATION = 20 LogV-----O----U----T--- 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4B. TEST CIRCUIT FIGURE 4C. OFF ISOLATION FN3127 Rev 7.00 Page 7 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH=3V and VAL = 0.8V Unless Otherwise Specified (Continued) -200 SWITCHED CHANNEL B) -160 d STALK ( -120 RL = 100 2VVP-INP 50 VOUT RL S CRO -80 RL -40 RL = 10k RL = 1k VOUT CROSSTALK = 20 Log---------------- 0  VIN  1 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 5A. CROSSTALK vs FREQUENCY FIGURE 5B. TEST CIRCUIT FIGURE 5. CROSSTALK 200 W) m N ( 160 +10V O TI -10V P A M 120 TOGGLE U S AT 50% ON DUTY VL VR V+ V- C 80 R E IL I+ I- W PO 40 +5V +15V -15V 0 1K 10K 100K 1M TOGGLE FREQUENCY (50% DUTY CYCLE) (Hz) FIGURE 6A. POWER CONSUMPTION vs FREQUENCY FIGURE 6B. TEST CIRCUIT FIGURE 6. POWER CONSUMPTION VAH VA IN1 90% 90% OUT 1 +10V OUT 1 IN2 OUT 2 tON tOFF OUT 2 1K 1K 90% 90% VA tOFF tON FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FN3127 Rev 7.00 Page 8 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Test Circuits and Waveforms TA = 25oC, V+ = +15V, V- = -15V, VL = +5V, VR = 0V, VAH=3V and VAL = 0.8V Unless Otherwise Specified (Continued) VA VA OUTPUT OUTPUT VA = 0V to 5V VA = 0V to 10V Vertical: 2V/Div. Vertical: 5V/Div. Horizontal: 200ns/Div. Horizontal: 200ns/Div. FIGURE 7C. WAVEFORMS WITH TTL COMPATIBLE LOGIC FIGURE 7D. WAVEFORMS WITH CMOS COMPATIBLE LOGIC INPUT INPUT 720 720 660 660 600 600 T) 540 T) 540 PU 480 PU 480 ED IN 432600 tON ED IN 432600 tON NE 300 tOFF NE 300 ( 240 ( 240 tOFF 180 180 120 120 60 60 2.4 3.0 3.6 4.2 4.8 0 0.5 1.0 1.5 DIGITAL “HIGH” (V) DIGITAL “LOW” (V) FIGURE 7E. SWITCHING TIMES vs POSITIVE DIGITAL VOLTAGE FIGURE 7F. SWITCHING TIMES vs NEGATIVE DIGITAL VOLTAGE FIGURE 7. SWITCH tON AND tOFF FN3127 Rev 7.00 Page 9 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE June 16, 2016 FN3127.7 Updated Ordering Information table on page2. Added Revision History and About Intersil sections. Updated POD M16.15 to the latest revision changes are as follows: Remove "u" symbol from drawing (overlaps the "a" on Side View). Multiple changes were made to table. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN3127 Rev 7.00 Page 10 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.735 0.775 18.66 19.68 5 B e D1 0.005 - 0.13 - 5 B 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of eB - 0.430 - 10.92 7 Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated in JE- DEC seating plane gauge GS-3. N 16 16 9 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Rev. 0 12/93 Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendic- ular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3127 Rev 7.00 Page 11 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Small Outline Plastic Packages (SOIC) N M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES MILLIMETERS E SYMBOL MIN MAX MIN MAX NOTES -B- A 0.0532 0.0688 1.35 1.75 - 1 2 3 A1 0.0040 0.0098 0.10 0.25 - L B 0.013 0.020 0.33 0.51 9 SEATING PLANE C 0.0075 0.0098 0.19 0.25 - -A- D A h x 45° D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 -C- e 0.050 BSC 1.27 BSC -  e H 0.2284 0.2440 5.80 6.20 - A1 C h 0.0099 0.0196 0.25 0.50 5 B 0.10(0.004) L 0.016 0.050 0.40 1.27 6 0.25(0.010) M C A M B S N 16 16 7 NOTES:  0° 8° 0° 8° - 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Rev. 1 6/05 Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. FN3127 Rev 7.00 Page 12 of 13 June 16, 2016

HI-5042, HI-5043, HI-5047, HI-5049, HI-5051 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -A- -D- INCHES MILLIMETERS BASE (c) METAL SYMBOL MIN MAX MIN MAX NOTES E b1 A - 0.200 - 5.08 - M M -B- (b) b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 SECTION A-A bbb S C A - B S D S b2 0.045 0.065 1.14 1.65 - D BASE b3 0.023 0.045 0.58 1.14 4 PLANE Q -C- A c 0.008 0.018 0.20 0.46 2 SEATING PLANE L  c1 0.008 0.015 0.20 0.38 3 D - 0.840 - 21.34 5 S1 A A eA b2 E 0.220 0.310 5.59 7.87 5 b e eA/2 c e 0.100 BSC 2.54 BSC - ccc M C A - B S D S aaaM C A - B S D S eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 - ed adjacent to pin one and shall be located within the shaded Q 0.015 0.060 0.38 1.52 6 area shown. The manufacturer’s identification shall not be used S1 0.005 - 0.13 - 7 as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be  90o 105o 90o 105o - measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 - solder dip or tin plate lead finish is applied. bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3 partial lead paddle. For this configuration dimension b3 replaces N 16 16 8 dimension b2. Rev. 0 4/94 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. © Copyright Intersil Americas LLC 2001-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3127 Rev 7.00 Page 13 of 13 June 16, 2016