HEF4526B Programmable 4-bit binary down counter Rev. 5 — 22 November 2011 Product data sheet 1. General description The HEF4526B is a synchronous programmable 4-bit binary down counter with active HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL), four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master reset input (MR) and a decoded TC output that can be used for divide-by-n applications. In single stage applications the TC output is connected to PL. CFallows cascade divide-by-n operation with no additional gates required. Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is highly tolerant of slower clock rise and fall times due to Schmitt trigger action. It operates over a recommended V power supply range of 3V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +85 C  Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering info rmation All types operate from 40C to +85C. Type number Package Name Description Version HEF4526BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4526BT SO16 plastic small outline package; 16 leads; body width 3.9mm SOT109-1

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 4. Functional diagram 3 5 11 14 2 PL A0 A1 A2 A3 PARALLEL LOAD CIRCUITRY 6 CP0 CD/SD BINARY CP DOWN 4 CP1 COUNTER CD Q3 1 Q2 15 Q1 9 10 MR Q0 7 ZERO TC 12 13 CF DETECTOR 001aae719 Fig 1. Functional diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP0 input CP1 input MR input Q0 Q1 Q2 Q3 001aak014 Fig 2. Timing diagram HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 2 of 19

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx P H N roduct d EF4526B XP S a e ta m sh ic ee A0 Q0 A1 Q1 A2 Q2 A3 Q3 o t n d u c t o r s PL All inform MR Rev. 5 — 22 No ation provided in this docum TCD1SF1DFCDOO2 TCD1SF2DFCDOO2 TCD1SF3DFCDOO2 TCD1SF4DFCDOO2 vember 2011 ent is subject to legal disclaim CP1 Pro ers. CP0 gra m m CF a b le TC 4 - b it b H in © a E NXP B 001aae722 ry d F 3 of 19 .V. 2011. All rights reserved. Fig 3. Logic diagram own counter 4526B

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 5. Pinning information 5.1 Pinning HEF4526B Q3 1 16 VDD A3 2 15 Q2 PL 3 14 A2 CP1 4 13 CF A0 5 12 TC CP0 6 11 A1 Q0 7 10 MR VSS 8 9 Q1 001aae720 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin descripti on Symbol Pin Description A0 to A3 5, 11, 14, 2 parallel input PL 3 parallel load input CP0 6 clock input (LOW-to-HIGH, triggered) CP1 4 clock input (HIGH-to-LOW, triggered) CF 13 cascade feedback input MR 10 asynchronous master reset input TC 12 terminal count output Q0 to Q3 7, 9, 15, 1 buffered parallel output V 16 supply voltage DD V 8 ground (0 V) SS HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 4 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 6. Functional description Table 3. Function tab le[1] MR PL CP0 CP1 Mode H X X X reset (asynchronous) L H X X preset (asynchronous) L L  H no change L L L  no change L L  X no change L L X  no change L L  L counter advances L L H  counter advances [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition. Table 4. Counting mo de CF = HIGH; PL = LOW; MR = LOW. Count Outputs Q3 Q2 Q1 Q0 15 H H H H 14 H H H L 13 H H L H 12 H H L L 11 H L H H 10 H L H L 9 H L L H 8 H L L L 7 L H H H 6 L H H L 5 L H L H 4 L H L L 3 L L H H 2 L L H L 1 L L L H 0 L L L L HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 5 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 5. Single stage operation Divide-by-n; MR = LOW; CF = HIGH; CP1 = LOW. PL A3 A2 A1 A0 Divide by TC output pulse width L X X X X 16 one clock period TC H H H H 15 clock pulse HIGH TC H H H L 14 TC H H L H 13 TC H H L L 12 TC H L H H 11 TC H L H L 10 TC H L L H 9 TC H L L L 8 TC L H H H 7 TC L H H L 6 TC L H L H 5 TC L H L L 4 TC L L H H 3 TC L L H L 2 TC L L L H 1 TC L L L L no operation 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 001aae721 Fig 5. State diagram HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 6 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 7. Limiting values Table 6. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V supply voltage 0.5 +18 V DD I input clamping current V <0.5V or V >V + 0.5 V - 10 mA IK I I DD V input voltage 0.5 V + 0.5 V I DD I output clamping current V <0.5V or V >V + 0.5 V - 10 mA OK O O DD I input/output current - 10 mA I/O I supply current to any supply terminal - 100 mA DD T storage temperature 65 +150 C stg T ambient temperature 40 +85 C amb P total power dissipation DIP16 package [1] - 750 mW tot SO16 package [2] - 500 mW P power dissipation per output - 100 mW [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. 8. Recommended operating conditions Table 7. Recommend ed operating conditions Symbol Parameter Conditions Min Typ Max Unit V supply voltage 3 - 15 V DD V input voltage 0 - V V I DD T ambient temperature in free air 40 - +85 C amb t/V input transition rise and fall rate V = 5 V - - 3.75 s/V CC V = 10 V - - 0.5 s/V CC V = 15 V - - 0.08 s/V CC HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 7 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 9. Static characteristics Table 8. Static charac teristics V = 0 V; V = V or V unless otherwise specified. SS I SS DD Symbol Parameter Conditions V T = 40 C T = 25 C T = 85 C Unit DD amb amb amb Min Max Min Max Min Max V HIGH-level input voltage I  < 1 A 5 V 3.5 - 3.5 - 3.5 - V IH O 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V V LOW-level input voltage I  < 1 A 5 V - 1.5 - 1.5 - 1.5 V IL O 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V V HIGH-level output voltage I  < 1 A 5 V 4.95 - 4.95 - 4.95 - V OH O 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V V LOW-level output voltage I  < 1 A 5 V - 0.05 - 0.05 - 0.05 V OL O 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V I LOW-level output current V = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA OL O V = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA O V = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA O I HIGH-level output current V = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA OH O V = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA O V = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA O V = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA O I input leakage current 15 V - 0.3 - 0.3 - 1.0 A I I supply current I = 0A 5 V - 20 - 20 - 150 A DD O 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A C input capacitance - - - - 7.5 - - pF I HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 8 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 10. Dynamic characteristics Table 9. Dynamic cha racteristics V = 0 V; T = 25 C; for test circuit see Figure7; unless otherwise specified. SS amb Symbol Parameter Conditions V Extrapolation formula Min Typ Max Unit DD t HIGH to LOW CP0, CP1 to Qn; 5 V [1] 123 ns + (0.55 ns/pF)C - 150 300 ns PHL L propagationdelay seeFigure6 10 V 54 ns + (0.23 ns/pF)C - 65 130 ns L 15 V 42 ns + (0.16 ns/pF)C - 50 100 ns L CP0, CP1 to TC; 5 V 183 ns + (0.55 ns/pF)C - 210 420 ns L seeFigure6 10 V 79 ns + (0.23 ns/pF)C - 90 180 ns L 15 V 62 ns + (0.16 ns/pF)C - 70 140 ns L PL to Qn; 5 V 173 ns + (0.55 ns/pF)C - 200 400 ns L seeFigure6 10 V 69 ns + (0.23 ns/pF)C - 80 160 ns L 15 V 52 ns + (0.16 ns/pF)C - 60 120 ns L MR to Qn 5 V 113 ns + (0.55 ns/pF)C - 140 280 ns L 10 V 44 ns + (0.23 ns/pF)C - 55 110 ns L 15 V 32 ns + (0.16 ns/pF)C - 40 80 ns L t LOW to HIGH CP0, CP1 to Qn; 5 V [1] 123 ns + (0.55 ns/pF)C - 150 300 ns PLH L propagationdelay seeFigure6 10 V 54 ns + (0.23 ns/pF)C - 65 130 ns L 15 V 42 ns + (0.16 ns/pF)C - 50 100 ns L CP0, CP1 to TC; 5 V 183 ns + (0.55 ns/pF)C - 210 420 ns L seeFigure6 10 V 79 ns + (0.23 ns/pF)C - 90 180 ns L 15 V 62 ns + (0.16 ns/pF)C - 70 140 ns L PL to Qn; 5 V 153 ns + (0.55 ns/pF)C - 180 360 ns L seeFigure6 10 V 59 ns + (0.23 ns/pF)C - 70 140 ns L 15 V 42 ns + (0.16 ns/pF)C - 50 100 ns L t transition time seeFigure6 5 V [1] 10 ns + (1.00 ns/pF)C - 60 120 ns t L 10 V 9 ns + (0.42 ns/pF)C - 30 60 ns L 15 V 6 ns + (0.28 ns/pF)C - 20 40 ns L t set-up time An to PL; 5 V 30 0 - ns su seeFigure6 10 V 20 0 - ns 15 V 15 0 - ns t hold time An to PL; 5 V 30 5 - ns h seeFigure6 10 V 20 5 - ns 15 V 15 5 - ns HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 9 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Table 9. Dynamic characteristics …continued V = 0 V; T = 25 C; for test circuit see Figure7; unless otherwise specified. SS amb Symbol Parameter Conditions V Extrapolation formula Min Typ Max Unit DD t pulsewidth CP0 input; LOW; 5 V 80 40 - ns W seeFigure6 10 V 40 20 - ns 15 V 30 15 - ns CP1 input; HIGH; 5 V 80 40 - ns seeFigure6 10 V 40 20 - ns 15 V 30 15 - ns PL input; HIGH; 5 V 100 50 - ns seeFigure6 10 V 40 20 - ns 15 V 32 16 - ns MR input; LOW 5 V 130 65 - ns 10 V 50 25 - ns 15 V 40 20 - ns f maximum frequency PL=LOW; 5 V [2] 6 12 - MHz max seeFigure6 10 V 12 25 - MHz 15 V 16 32 - MHz [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C in pF). L [2] In the divide-by-n mode (PL connected to TC), the CP0 or CP1 pulse width must be greater than the maximum HIGH to LOW propagation delay for CP0 or CP1 to TC. Table 10. Dynamic pow er dissipation P D P can be calculated from the formulas shown. V = 0 V; t = t  20 ns; T = 25 C. D SS r f amb Symbol Parameter V Typical formula for P (W) where: DD D P dynamic power 5 V P = 1000  f + (f  C )  V 2 f = input frequency in MHz, D D i o L DD i dissipation 10 V PD = 4000  fi + (fo  CL)  VDD2 fo = output frequency in MHz, 15 V PD = 10000  fi + (fo  CL)  VDD2 CL = output load capacitance in pF, V = supply voltage in V, DD (f  C ) = sum of the outputs. o L HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 10 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 11. Waveforms 1/fmax Vl CP0 input VM 0 V tW Vl CP1 input VM 0 V tW VOH Qn output VM VOL tPLH tPHL tPLH VOH TC output VM VOL tPLH tPHL 001aae724 a. Propagation delays for CP0, CP1 to Qn, and TC, minimum CP0 and CP1 pulse widths and maximum frequency Vl PL input VM 0 V tsu tW th Vl An input VM 0 V tPLH tPHL VOH 90% Qn output 10% VOL tt tt 001aae723 b. Propagation delays for PL and An to Qn, setup and holdtimes for PLtoAn, Qn transitiontimes and minimum PL pulsewidth Measurement points are given in Table11. The logic levels VOH and VOL are typical output voltage levels that occur with the output load. Fig 6. Waveforms showing switching times HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 11 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter tW VI 90 % 90 % negative pulse VM VM 10 % 10 % 0 V tf tr tr tf VI 90 % 90 % positive pulse VM VM 10 % 10 % 0 V tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table11; Definitions for test circuit: DUT = Device Under Test; CL = Load capacitance, including jig and probe capacitance; RL = Load resistance; R = Termination resistance, should be equal to the output impedance Z of the pulse generator. T o Fig 7. Test circuit for switching times Table 11. Measuremen t points and test data Supply voltage Input Load V V t, t C R I M r f L L 5Vto15V V 0.5V  20 ns 50pF 1 k DD I 12. Application information Some examples of HEF4526B applications are: • Divide-by-n counter • Programmable frequency divider HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 12 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter cycle inhibit VDD Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 PL PL CF VDD CF HEF4526B HEF4526B MR TC MR TC (L.S.D.) (M.S.D.) CP1 CP1 clock CP0 CP0 A0 A1 A2 A3 A0 A1 A2 A3 Counting cycle: 15 10 kΩ 10 kΩ 14 (4x) (4x) . . . n0 n1 . . S n0 S n1 . . 1 1 stop at 0 0 LOW L.S.D. counter M.S.D. counter VDD VDD master reset 001aae725 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 8. Typical 2-stage programmable down counter (one cycle) application. f0 = fi/n Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 PL PL CF VDD CF HEF4526B HEF4526B MR TC MR TC (L.S.D.) (M.S.D.) CP1 CP1 clock CP0 CP0 A0 A1 A2 A3 A0 A1 A2 A3 Counting cycle: 15 10 kΩ 10 kΩ 14 (4x) (4x) . . . . . S n0 S n1 n0 n1 . . . . 2 2 VDD VDD 1 1 master 0 0 reset L.S.D. counter M.S.D. counter 001aae726 L.S.D. = Least Significant Digit; M.S.D. = Most Significant Digit. Fig 9. Typical 2-stage programmable frequency divider application HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 13 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D ME e n a pl g n eati A2 A s L A1 c Z e w M b1 (e ) 1 b b2 16 9 MH pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. mAi n1 . mAa 2x . b b1 b2 c D(1) E(1) e e1 L ME MH w mZa(1x). 1.73 0.53 1.25 0.36 19.50 6.48 3.60 8.25 10.0 mm 4.2 0.51 3.2 2.54 7.62 0.254 0.76 1.30 0.38 0.85 0.23 18.55 6.20 3.05 7.80 8.3 inches 0.17 0.02 0.13 0.068 0.021 0.049 0.014 0.77 0.26 0.1 0.3 0.14 0.32 0.39 0.01 0.03 0.051 0.015 0.033 0.009 0.73 0.24 0.12 0.31 0.33 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 95-01-14 SOT38-4 03-02-13 Fig 10. Package outline SOT38-4 (DIP16) HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 14 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A1 (A 3 ) A pin 1 index θ Lp 1 8 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT109-1 076E07 MS-012 03-02-19 Fig 11. Package outline SOT109-1 (SO16) HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 15 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4526B v.5 20111122 Product data sheet - HEF4526B v.4 Modifications: • Section Applications removed • Table8: I minimum values changed to maximum OH HEF4526B v.4 20090921 Product data sheet - HEF4526B_CNV v.3 HEF4526B_CNV v.3 19950101 Product specification - HEF4526B_CNV v.2 HEF4526B_CNV v.2 19950101 Product specification - - HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 16 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or to the publication hereof. other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior safety-critical systems or equipment, nor in applications where failure or authorization from competent authorities. HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 17 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’ Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 15.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 22 November 2011 18 of 19

HEF4526B NXP Semiconductors Programmable 4-bit binary down counter 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 Recommended operating conditions. . . . . . . . 7 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8 10 Dynamic characteristics. . . . . . . . . . . . . . . . . . 9 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 Application information. . . . . . . . . . . . . . . . . . 12 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 Contact information. . . . . . . . . . . . . . . . . . . . . 18 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 November 2011 Document identifier: HEF4526B