1 HCPL-5120, HCPL-5121, and 5962-04204 2.0 Amp Output Current IGBT Gate Drive Hermetically Sealed Optocoupler Data Sheet Description Features The HCPL-512x contains a GaAsP LED optically coupled to an  Performance guaranteed over full military temperature integrated circuit with a power output stage. The device is range: –55°C to +125°C ideally suited for driving power IGBTs and MOSFETs used in  Manufactured and tested on a MIL-PRF-38534 certified line motor control inverter applications. The high operating voltage  Hermetically sealed packages range of the output stage provides the drive voltages required  Dual marked with device part number and DLA Standard by gate-controlled devices. The voltage and current supplied Microcircuit Drawing (SMD) by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200V/100A. For IGBTs with higher  HCPL-3120 function compatibility ratings, the HCPL-512x can be used to drive a discrete power  QML-38534, Class H stage, which drives the IGBT gate.  2.0A minimum peak output current The products are capable of operation and storage over the full  0.5V maximum low level output voltage (VOL): eliminates need for negative gate drive military temperature range and can be purchased as either commercial products or with full MIL-PRF-38534 Class H  10 kV/μs minimum common-mode rejection (CMR) at testing, or from the DLA Standard Microcircuit Drawing (SMD) VCM=1000V 5962-04204. All devices are manufactured and tested on a  ICC = 5 mA maximum supply current MIL-PRF-38534 certified line, and the Class H device is included  Undervoltage lock-out protection (UVLO) with hysteresis in the DLA Qualified Manufacturers List, QML-38534 for Hybrid  Wide operating VCC Range: 15V to 30V Microcircuits.  500 ns maximum propagation delay  ±0.35μs maximum delay between devices Applications CAUTION It is advised that normal static precautions be taken in handling and assembly of this  Industrial and military environments component to prevent damage and/or  High reliability systems degradation which may be induced by ESD.  Harsh industrial environments  Transportation, medical, and life critical systems  Uninterruptible power supplies (UPS)  Isolated IGBT/MOSFET gate drive  AC and brushless DC motor drives  Industrial inverters  Switch mode power supplies (SMPS) 1. See Selection Guide– Lead Configuration Options for available extensions. Broadcom - 1 -

HCPL-5120, HCPL-5121, and 5962-04204 Schematic Diagram Data Sheet Schematic Diagram Truth Table V – V V – V CC EE CC EE N/C 1 8 V CC LED Positive Negative VO ANODE 2 7 VO Going Going (i.e., Turn-On) (i.e., Turn-Off) CATHODE 3 6 V O OFF 0V to 30V 0V to 30V LOW ON 0V to 11V 0V to 9.5V LOW N/C 4 5 V SHIELD EE ON 11V to 13.5V 9.5V to 12V TRANSITION ON 13.5V to 30V 12V to 30V HIGH NOTE A 0.1 μF bypass capacitor must be connected between pins 5 and 8. Selection Guide– Lead Configuration Options Part Number and Options Commercial HCPL-5120 MIL-PRF-38534, Class H HCPL-5121 Standard Lead Finisha Gold Plate Solder Dippedb Option - 200 Butt Cut/Gold Platea Option - 100 Gull Wing/Solderedb Option - 300 SMD Part Number Prescript for all below 5962- Gold Platea 0420401HPC Solder Dippedb 0420401HPA Butt Cut/Gold Platea 0420401HYC Butt Cut/Solderedb 0420401HYA Gull Wing/Solderedb 0420401HXA a. Gold plate lead finish: Maximum gold thickness of leads is <100 micro-inches. Typical is 60 to 90 micro-inches. b. Solder lead finish: Sn63/Pb37. Device Marking AVAGO DESIGNATOR A QYYWWZ COMPLIANCE INDICATOR,[1] AVAGO P/N HCPL-512x DATE CODE, SUFFIX (IF NEEDED) DLA SMD[1] 5962-04204 DLA SMD[1] 01Hxx XXX COUNTRY OF MFR. PIN ONE/ 50434 AVAGO CAGE CODE[1] ESD IDENT [1] QML PARTS ONLY Broadcom - 2 -

HCPL-5120, HCPL-5121, and 5962-04204 Outline Drawing Data Sheet Outline Drawing 8-Pin DIP Through Hole, 1 Channel 10.03 (0.395) 8.13 (0.320) 10.29 (0.405) MAX. 1.02 (0.040) 7.16 (0.282) 1.52 (0.060) 7.57 (0.298) 4.32 (0.170) MAX. 0.51 (0.020) 3.81 (0.150) MIN. MIN. 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 2.29 (0.090) 0.51 (0.020) 7.87 (0.310) 2.79 (0.110) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Hermetic Optocoupler Options Option Description 100 Surface-mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on Commercial and Class H product. 4.32 (0.170) MAX. 0.51 (0.020) 1.14 (0.045) MIN. 1.40 (0.055) 0.20 (0.008) 0.33 (0.013) 2.29 (0.090) 0.51 (0.020) 2.79 (0.110) MAX. 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 200 Lead finish is solder-dipped rather than gold plated. This option is available on Commercial and Class H product. DLA Drawing (SMD) part numbers contain provisions for lead finish. 300 Surface-mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on Commercial and Class H product. This option has solder-dipped leads. 4.57 (0.180) 4.57 (0.180) MAX. MAX. 0.20 (0.008) 0.51 (0.020) 1.40 (0.055) 5° MAX. 0.33 (0.013) MIN. 1.65 (0.065) 1.07 (0.042) 2.29 (0.090) 0.51 (0.020) 9.65 (0.380) 1.32 (0.052) 2.79 (0.110) MAX. 9.91 (0.390) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Broadcom - 3 -

HCPL-5120, HCPL-5121, and 5962-04204 Absolute Maximum Ratings Data Sheet Absolute Maximum Ratings Parameter Symbol Min Max Unit Notes Storage Temperature T –65 +150 °C S Operating Temperature T –55 +125 °C A Case Temperature T — +145 °C C Junction Temperature T — +150 °C J Lead Solder Temperature — 260 for 10s °C Average Input Current I — 25 mA a F AVG Peak Transient Input Current I — 1.0 A F PK (<1-μs pulse width, 300 pps) Reverse Input Voltage V — 5 V R High Peak Output Current I — 2.5 A b OH (PEAK) Low Peak Output Current I — 2.5 A b OL (PEAK) Supply Voltage (V – V ) 0 35 V CC EE Output Voltage V 0 V V O (PEAK) CC Emitter Power Dissipation P — 45 mW a E Output Power Dissipation P — 250 mW c O Total Power Dissipation P — 295 mW d T a. No derating required for typical case-to-ambient thermal resistance (Θ = 140°C/W). See Figure35. CA b. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I peak minimum = O 2.0A. See the Application Information section for additional details on limiting I peak. OH c. Derate linearly above 102°C free air temperature at a rate of 6 mW/°C for typical case-to-ambient thermal resistance (Θ = 140°C/W). See Figure36. CA d. Derate linearly above 102°C free air temperature at a rate of 6 mW/°C for typical case-to-ambient thermal resistance (Θ = 140°C/W). See Figure35 and CA Figure36. ESD Classification MIL-STD-883, Method 3015 , Class 1 Recommended Operating Conditions Parameter Symbol Min Max Unit Power Supply Voltage (V – V ) 15 30 V CC EE Input Current (ON) I 10 18 mA F (ON) Input Voltage (OFF) V –3.0 0.8 V F (OFF) Operating Temperature T –55 125 °C A Broadcom - 4 -

HCPL-5120, HCPL-5121, and 5962-04204 Electrical Specifications (DC) Data Sheet Electrical Specifications (DC) Over recommended operating conditions (T = –55°C to +125°C, I = 10 mA to 18 mA, V = –3.0V to 0.8V, V = 15V to 30V, A F(ON) F(OFF) CC V = Ground), unless otherwise specified. EE Limits Group A Parameter Symbol Test Conditions Unit Fig Notes Subgroupsa Min Typb Max High Level Output Current I V = (V – 4V) 1, 2, 3 0.5 1.5 — A 2, 3, 17 c OH O CC V = (V – 15V) 2.0 — — A d O CC Low Level Output Current I V = (V + 2.5V) 1, 2, 3 0.5 2.0 — A 5, 6, 18 c OL O EE V = (V + 15V) 2.0 — — A d O EE High Level Output Voltage V I = –100 mA 1, 2, 3 (V – 4) (V – 3) — V 1, 3, 19 e, f OH O CC CC Low Level Output Voltage V I = 100 mA 1, 2, 3 — 0.1 0.5 V 4, 6, 20 OL O High Level Supply Current I Output Open, 1, 2, 3 — 2.5 5.0 mA 7, 8 CCH I = 10 mA to 18 mA F Low Level Supply Current I Output Open, 1, 2, 3 — 2.5 5.0 mA CCL V = –3.0V to +0.8V F Threshold Input Current Low to High I I = 0 mA, 1, 2, 3 — 3.5 9.0 mA 9, 15, 21 FLH O V > 5V Threshold Input Voltage High to Low V O 1, 2, 3 0.8 — — V FHL Input Forward Voltage V I = 10 mA 1, 2, 3 1.2 1.5 1.8 V 16 F F Temperature Coefficient of Forward ΔV /ΔT I = 10 mA — –1.6 — mV/°C F A F Voltage Input Reverse Breakdown Voltage BV I = 10 μA 1, 2, 3 5 — — V R R Input Capacitance C f = 1 MHz, V = 0V — 80 — pF IN F UVLO Threshold V V > 5V, 1, 2, 3 11.0 12.3 13.5 V 22, 37 UVLO+ O I = 10 mA V F 1, 2, 3 9.5 10.7 12.0 UVLO– UVLO Hysteresis UVLO — 1.6 — HYS a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typical values at T = 25°C and V – V = 30V, unless otherwise noted. A CC EE c. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%. d. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with I peak minimum = O 2.0A. See the Application Information section for additional details on limiting I peak. OH e. In this test, V is measured with a dc load current. When driving capacitive loads, V approaches V as I approaches zero amps. OH OH CC OH f. Maximum pulse width = 1 ms, maximum duty cycle = 20%. Broadcom - 5 -

HCPL-5120, HCPL-5121, and 5962-04204 Switching Specifications (AC) Data Sheet Switching Specifications (AC) Over recommended operating conditions (T = –55°C to +125°C, I = 10 mA to 18 mA, V = –3.0V to 0.8V, V = 15V to 30V, A F(ON) F(OFF) CC V = Ground), unless otherwise specified. EE Limits Group A Parameter Symbol Test Conditions Unit Fig Notes Subgroupsa Min Typb Max Propagation Delay Time to High Output t Rg = 10Ω, 9, 10, 11 0.10 0.30 0.50 μs 10, 11, c PLH Level Cg = 10 nF, f = 10 kHz, 12, 13, Duty Cycle = 50% 14, 23 Propagation Delay Time to Low Output t 9, 10, 11 0.10 0.30 0.50 μs PHL Level Pulse Width Distortion PWD 9, 10, 11 — — 0.3 μs d Propagation Delay Difference Between PDD 9, 10, 11 –0.35 — 0.35 μs 33, 34 e Any Two Parts (t – t ) PHL PLH Rise Time t — 0.1 — μs 23 r Fall Time t — 0.1 — μs f UVLO Turn On Delay t V > 5V, I = 10 mA — 0.8 — μs 22 UVLO ON O F UVLO Turn Off Delay t V < 5V, I = 10 mA — 0.6 — UVLO OFF O F Output High Level Common-Mode |CMH| IF = 10 mA, 9 10 — — kV/μs 24 f, g, h Transient Immunity V = 1000V, CM V = 30V, T = 25°C CC A Output Low Level Common-Mode |CML| VCM = 1000V, VF = 0V, 9 10 — — kV/μs f, i, h Transient Immunity V = 30V, T = 25°C CC A a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. All typical values at T = 25°C and V – V = 30V, unless otherwise noted. A CC EE c. This load condition approximates the gate load of a 1200V/75A IGBT. d. Pulse Width Distortion (PWD) is defined as |t – t | for any given device. PHL PLH e. The difference between t and t between any two HCPL-512x parts under the same test condition. PHL PLH f. Pins 1 and 4 need to be connected to LED common. g. Common-mode transient immunity in the high state is the maximum tolerable dV /dt of the common-mode pulse, V , to assure that the output remains CM CM in the high state (i.e., V > 15.0V). O h. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. i. Common-mode transient immunity in a low state is the maximum tolerable dV /dt of the common-mode pulse, V , to assure that the output remains in CM CM a low state (i.e., V < 1.0V). O Broadcom - 6 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Package Characteristics Over recommended operating conditions (T = –55°C to +125°C) unless otherwise specified. A Limits Group A Parameter Symbol Test Conditions Unit Fig Notes Subgroupsa Min Typb Max Input-Output Leakage Current I V = 1500 Vdc, RH ≤ 65%, 1 — — 1.0 μA c, d I-O I-O t = 5 sec., T = 25°C A Resistance (Input-Output) RI-O VI-O = 500 VDC — 1010 — Ω d Capacitance (Input-Output) C f = 1 MHz — 2.5 — pF d I-O a. Commercial parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25°C, 125°C, and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). b. Typicals at T = 25°C. A c. This is a momentary withstand test, not an operating condition. d. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. Broadcom - 7 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Figure1 V vs. Temperature Figure2 I vs. Temperature OH OH 0 2.4 V LTAGE DROP - 1 VIIVFO CEU=ECT =1== 0 01-m1V50A t0o tm o3 A01V8mA RENT - A 2.2 IVVVF OCE=ECU T=1= = 0 01 mV(5VA tCo tC o 3- 01 4V8Vm)A O R UT V H CU 2.0 UTP 2 HIG H O UT 1.8 G P HI UT V) - CC 3 - OOH 1.6 - OH I V ( 4 1.4 -55 -35 -15 5 25 45 65 85 105 125 -55 -35 -15 5 25 45 65 85 105 125 TA - TEMPERATURE - oC TA - TEMPERATURE - oC Figure3 V vs. I Figure4 V vs. Temperature OH OH OL -1 0.30 V P - 125 oC VF(OFF) = -3.0 to 0.8V DRO -2 2-55 ooCC E - V 0.25 IVOUT == 1150 0tom 3A0V VOLTAGE -3 W VOLTAG 0.20 VCEEC = 0V GH LO 0.15 PUT HI -4 UTPUT 0.10 ) - OUTCC -5 IVF C=C =1 01 5to t o1 83m0VA - OVOL 0.05 - VH VEE = 0V (VO -6 0.00-55 -35 -15 5 25 45 65 85 105 125 0.0 0.5 1.0 1.5 2.0 2.5 T - TEMPERATURE - oC I - OUTPUT HIGH CURRENT - A A OH Figure5 I vs. Temperature Figure6 V vs. I OL OL OL 4 8 - OUTPUT LOW CURRENT - AW231 VVVVFOCE(ECUO T=F= F= 0)1 =V25 . -5t3oV. 03 0toV 0.8V - OUTPUT LOW VOLTAGE - VOL 234567 VVVFCE (EC O = =F F 0)1 = V 512- 5 25- t35 oooC Co.C0 3 t0oV 0.8V ILO V 1 0 0 -55 -35 -15 5 25 45 65 85 105 125 0.0 0.5 1.0 1.5 2.0 2.5 TA - TEMPERATURE - oC IOL - OUTPUT LOW CURRENT - A Broadcom - 8 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Figure7 I vs. Temperature Figure8 I vs. V CC CC CC 4.0 4.0 IICCCCHL IICCCCHL I - SUPPLY CURRENT - mACC 2233....0505 VVIF CE=EC =1= 0 03mV0AV for ICCH - SUPPLY CURRENT - mAICC 2233....0505 IITFFA == = 10 20m5mA oA Cf ofor r ICICCLCH IF = 0mA for ICCL VEE = 0V 1.5 1.5 -55 -35 -15 5 25 45 65 85 105 125 15 20 25 30 T - TEMPERATURE - oC V - SUPPLY VOLTAGE - V A CC Figure9 I vs. Temperature Figure10 Propagation Delay vs. V FLH CC 5.0 500 A VCC = 15 to 30V IF = 10mA THRESHOLD - m 344...505 VOEUE T=P 0UVT = OPEN N DELAY - ns 400 RDTVACgu C t==y = 2C1 350y0 coV(cid:58)lCe, , , = VCf E=5gE0 1==%0 01kV0h znF NT TIO 300 E 3.0 A R G R A U P C O O HIGH 22..05 - PRTP 200 T T LOW 1.5 TPPLHHL - H -55 -35 -15 5 25 45 65 85 105 125 100 IFL 15 20 25 30 T - TEMPERATURE - oC V - SUPPLY VOLTAGE - V A CC Figure11 Propagation Delay vs. I Figure12 Propagation Delay vs. Temperature F 500 500 RVCgC = = 1 300 V(cid:58), , VCEgE == 01V0 nF IVF C=C 1=0 3m0VA, VEE = 0V T - PROPAGATION DELAY - nsP 234000000 TDf =Au t=1y 0 2Ck5hy czolCe = 50% TTPPLHHL T - PROPAGATION DELAY- ns P 234000000 RDf =gu t1=y0 C1k0hy cz(cid:58)le, =C 5g0 =% 10 nF TTPPLHHL 100 100 -55 -35 -15 5 25 45 65 85 105 125 6 8 10 12 14 16 18 20 22 24 26 T - TEMPERATURE - oC I - FORWARD LED CURRENT - mA A F Broadcom - 9 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Figure13 Propagation Delay vs. R Figure14 Propagation Delay vs. C g g 500 500 V = 30V, V = 0V V = 30V, V = 0V CC EE TC C= 25 oC, IE E= 10mA TA = 25 oC, IF = 10mA A F Rg = 10 (cid:58) Cg = 10 nF Y -ns 400 Duty Cycle = 50% ns 400 Df =u t1y0 Ckhyczle = 50% ELA f = 10khz AY - N D DEL GATIO 300 TION 300 A A P G O A R P P O P - 200 PR 200 T TPLH T - P TPLH TPHL TPHL 100 100 0 10 20 30 40 50 0 20 40 60 80 100 Rg - SERIES LOAD RESISTANCE - (cid:58) Cg - LOAD CAPACITANCE - nF Figure15 Transfer Characteristics Figure16 Input Current vs. Forward Voltage 30 1000 TA = 25 oC T = 25oC 25 100 A AGE - V 20 NT - mA 10 T E PUT VOL 15 D CURR 1 T R U A O W V - O 10 FOR 0.1 5 - IF 0.01 0.001 0 0 1 2 3 4 5 1.10 1.20 1.30 1.40 1.50 1.60 IF - FORWARD LED CURRENT - mA VF - FORWARD VOLTAGE - V Figure17 I Test Circuit Figure18 I Test Circuit OH OL 1 8 1 8 0.1 μF 0.1 μF 2 7 +_ 4 V IOL 1IF8 = m 1A0 to +_ tVoC 3C 0= V15 2 7 +_ VtoC 3C 0= V15 3 6 IOH 3 6 2.5 V +_ 4 5 4 5 Broadcom - 10 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Figure19 V Test Circuit Figure20 V Test Circuit OH OL 1 8 1 8 0.1 μF 0.1 μF IF = 10 to 2 7 VOH 2 7 100 mA 18 mA +_ tVoC 3C 0= V15 +_ VtoC 3C 0= V15 3 6 3 6 100 mA VOL 4 5 4 5 Figure21 I Test Circuit Figure22 UVLO Test Circuit FLH 1 8 1 8 0.1 μF 0.1 μF 2 7 IF = 10 mA 2 7 IF 3 6 VO > 5 V +_ VtoC 3C 0= V15 3 6 VO > 5 V +_ VCC 4 5 4 5 Broadcom - 11 -

HCPL-5120, HCPL-5121, and 5962-04204 Package Characteristics Data Sheet Figure23 t , t , and t Test Circuit and Waveforms PLH PHL f 1 8 IF = 10 to 18 mA 2 7 0.1 μF +_ VtCo C3 0= V 15 IF 500 (cid:58) tr tf 10 KHz +_ VO 90% 50% DUTY 3 6 10 (cid:58) CYCLE 50% 10 nF VOUT 10% 4 5 Tr = Tf <_ 10 ns tPLH tPHL Figure24 CMR Test Circuit and Waveforms VCM IF 1 8 0.1 μF (cid:71)(cid:71)Vt =V(cid:39)CtM A B 2 7 0 V 5 V +_ VO +_ (cid:39)t 3 6 VCC = 30 V VO VOH 4 5 SWITCH AT A: IF = 10 mA VO VOL + _ SWITCH AT B: IF = 0 m A VCM = 1000 V Broadcom - 12 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet Application Information Step 2: Check the HCPL-512x Power Dissipation and Increase R if Necessary g Eliminating Negative IGBT Gate Drive The HCPL-512x total power dissipation (PT) is equal to the sum of the emitter power (P ) and the output power (P ): E O To keep the IGBT firmly off, the HCPL-512x has a very low P = P + P maximum V specification of 0.5V. The HCPL-512x realizes this T E O OL very low VOL by using a DMOS transistor with 1Ω (typical) on PE = IF × VF × Duty Cycle resistance in its pull-down circuit. When the HCPL-512x is in the P = P + P O O(BIAS) O(SWITCHING) low state, the IGBT gate is shorted to the emitter by R + 1Ω. g = I × (V – V ) + E (R , Q ) × f Minimizing R and the lead inductance from the HCPL-512x to CC CC EE SW g g g the IGBT gate and emitter (possibly by mounting the For the circuit in Figure26 with IF (worst case) = 18 mA, Rg = 8Ω, HCPL-512x on a small PC board directly above the IGBT) can Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz, and TA max = eliminate the need for negative IGBT gate drive in many 125°C: applications as shown in Figure25. Care should be taken with P = 18 mA × 1.8V × 0.8 = 26 mW E such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-512x input as this can result in PO = 4.25 mA × 20V + 1.0 μJ × 20 kHz unwanted coupling of transient signals into the HCPL-512x and = 85 mW + 20 mW degrade performance. (If the IGBT drain must be routed near the HCPL-512x input, then the LED should be reverse-biased = 105 mW when in the off state, to prevent the transient signals coupled < 112 mW (P at 125°C = 250 mW – 23°C × 6 mW/°C) O(MAX) from the IGBT drain from turning on the HCPL-512x.) The value of 4.25 mA for I in the previous equation was CC obtained by derating the I max of 5 mA (which occurs at Selecting the Gate Resistor (R ) to Minimize IGBT CC g –55°C) to I max at 125°C. CC Switching Losses Since P for this case is less than P , R of 8Ω is O O(MAX) g appropriate. Step 1: Calculate R Minimum from the I Peak g OL Specification The IGBT and R in Figure26 can be analyzed as a simple RC g circuit with a voltage supplied by the HCPL-512x. (V –V –V ) R = ------C---C-------------E--E------------O---L---- g I OLPEAK (V –V –2V) = ------C---C-------------E--E---------------- I OLPEAK (15V+5V–2V) = --------------------------------------- 2.5A = 7.2Ω≈8Ω The V value of 2V in the previous equation is a conservative OL value of V at the peak current of 2.5A (see Figure6). At lower OL R values the voltage supplied by the HCPL-512x is not an ideal g voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used, V in the previous equation is equal to zero volts. EE Broadcom - 13 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet Figure25 Recommended LED Drive and Application Circuit +5 V 1 8 270 W 0.1 μF + VCC = 18 V + HVDC _ 2 7 Rg CONINTPRUOTL 3 6 Q1 3-PHAACSE 74XXX 4 5 OPEN COLLECTOR Q2 - HVDC Figure26 Typical Application Circuit with Negative IGBT Gate Drive +5 V 1 8 270 W 0.1 μF + VCC = 15 V + HVDC _ 2 7 Rg CONTROL Q1 3-PHASE INPUT 3 6 _ VEE = -5 V AC + 74XXX 4 5 OPEN COLLECTOR Q2 - HVDC Figure27 Energy Dissipated in the HCPL-512x for Each IGBT Switching Cycle PE Parameter Description 7 I LED Current F μJ Qg = 100 nC VF LED On Voltage CYCLE - 65 QQgg == 255000 nnCC Duty Cycle Maximum LED G N Duty Cycle CHI 4 VCC = 19 V WIT VEE = -9 V S R 3 E P PO Parameter Description RGY 2 E N ICC Supply Current w - E 1 Es V Positive Supply Voltage CC 0 0 20 40 60 80 100 V Negative Supply Voltage EE Rg - GATE RESISTANCE - (cid:58) E (R , Q ) Energy Dissipation in the HCPL-512x for SW g g each IGBT Switching Cycle (See Figure27.) f Switching Frequency Broadcom - 14 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet LED Drive Circuit Considerations for Ultra High CMR with the LED On (CMR ) H CMR Performance A high CMR LED drive circuit must keep the LED on during Without a detector shield, the dominant cause of optocoupler common-mode transients. This is achieved by overdriving the CMR failure is capacitive coupling from the input side of the LED current beyond the input threshold so that it is not pulled optocoupler, through the package, to the detector IC as shown below the threshold during a transient. A minimum LED in Figure28. The HCPL-512x improves CMR performance by current of 10 mA provides adequate margin over the maximum using a detector IC with an optically transparent Faraday shield, I of 7 mA to achieve 10 kV/μs CMR. FLH which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate CMR with the LED Off (CMR ) L the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure29. This capacitive coupling causes A high CMR LED drive circuit must keep the LED off (V ≤ F perturbations in the LED current during common-mode V ) during common-mode transients. For example, during F(OFF) transients and becomes the major source of CMR failures for a a –dV /dt transient in Figure30, the current flowing through cm shielded optocoupler. The main design objective of a high CMR C also flows through the R and V of the logic gate. As LEDP SAT SAT LED drive circuit becomes keeping the LED in the proper state long as the low state voltage developed across the logic gate is (on or off) during common-mode transients. For example, the less than V , the LED remains off and no common-mode F(OFF) recommended application circuit (Figure25), can achieve failure occurs. 10kV/μs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in The open collector drive circuit, shown in Figure31, cannot the next two sections. keep the LED off during a +dVcm/dt transient, since all the current flowing through C must be supplied by the LED, LEDN Figure28 Optocoupler Input to Output Capacitance Model for and it is not recommended for applications requiring ultra high Unshielded Optocouplers CMR performance. Figure32 is an alternative drive circuit L which, like the recommended application circuit (Figure25), does achieve ultra high CMR performance by shunting the LED 1 8 in the off state. CLEDP 2 7 3 6 CLEDN 4 5 Figure29 Optocoupler Input to Output Capacitance Model for Shielded Optocouplers 1 CLEDO1 8 CLEDP 2 7 CLEDO2 3 6 CLEDN 4 5 SHIELD Broadcom - 15 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet Figure30 Equivalent Circuit for Figure 25 During Common-Mode Transient +5 V 1 8 0.1 CLEDP μF +_ VCC = 18 V 2 7 + V_SAT ILEDP 3 CLEDN 6 Rg * * * 4 5 * * * SHIELD * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING (cid:39)dVCM/dt _ + VCM Figure31 Not Recommended Open Collector Drive Circuit Figure32 Recommended LED Drive Circuit for Ultra-High CMR 1 8 1 8 +5 V +5 V CLEDP CLEDP 2 7 2 7 3 6 3 6 Q1 CLEDN CLEDN ILEDN 4 5 4 5 SHIELD SHIELD Broadcom - 16 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet IPM Dead Time and Propagation Delay Figure34 Waveforms for Dead Time Calculations Specifications ILED1 The HCPL-512x includes a Propagation Delay Difference (PDD) *PDD = PROPAGATION specification intended to help designers minimize dead time in VOUT1 Q1 ON DELAY DIFFERENCE Q1 OFF NOTE: their power inverter designs. Dead time is the time period FOR DEAD TIME AND PDD CALCULATIONS ALL during which both the high and low side power transistors (Q1 Q2 ON PROPAGATION DELAYS ARE and Q2 in Figure25) are off. Any overlap in Q1 and Q2 VOUT2 Q2 OFF TTAEMKEPNE RAATT TUHREE S AANMDE T EST CONDITIONS. conduction results in large currents flowing through the power ILED2 devices between the high and low voltage motor rail. tPHL MIN tPHL MAX To minimize dead time in a given design, the turn on of LED2 tPLH MIN should be delayed (relative to the turn off of LED1) so that tPLH MAX under worst-case conditions, transistor Q1 has just turned off (=t PPHDL D- *t PMLHA) XMAX when transistor Q2 turns on, as shown in Figure33. The MAXIMUM DEAD TIM E (DUE TO OPTOCOUPLER) amount of delay necessary to achieve this conditions is equal = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) - (tPHL MIN - tPLH MAX) to the maximum value of the propagation delay difference = PDD* MAX - PDD* MI N specification, PDD , which is specified to be 350 ns over the MAX operating temperature range of –55°C to 125°C. Figure35 Input Thermal Derating Curve, Dependence of Case-to-Ambient Thermal Resistance Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it 50 does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference 40 between the maximum and minimum propagation delay W m difference specifications as shown in Figure34. The maximum ER - 30 W dead time for the HCPL-512x is 700 ns (= 350 ns – (–350 ns)) O P T over an operating temperature range of –55°C to 125°C. U NP 20 Note that the propagation delays used to calculate PDD and P - IE case-to-ambient thermal resistance 10 = 70 oC/W dead time are taken at equal temperatures and test conditions = 140 oC/W = 210 oC/W since the optocouplers under consideration are typically 0 mounted in close proximity to each other and are switching -55 -25 5 35 65 95 125 identical IGBTs. TA - AMBIENT TEMPERATURE - oC Figure33 Minimum LED Skew for Zero Dead Time Figure36 Output Thermal Derating Curve, Dependence of Case-to-Ambient Thermal Resistance ILED1 300 *PDD = PROPAGATION VOUT1 DELAY DIFFERENCE Q1 ON 250 Q1 OFF NOTE: W FOR PDD CALCULATIONS m Q2 ON TAHREE PTRAOKEPNA GAATT TIOHNE SDAEMLAEYS ER - 200 VOUT2 Q2 OFF TCEOMNPDEITRIOATNUSR.E AND TEST T POW 150 U P ILED2 tPHL MAX tPLH MIN P - OUTO100 case-to-ambient the==r m1704a0 l o rCeoCs/Wi/sWtance PDD* MAX = (tPHL - tPLH)MAX = tPHL MAX - tPLH MIN 50 = 210 oC/W 0 -55 -25 5 35 65 95 125 TA - AMBIENT TEMPERATURE - oC Broadcom - 17 -

HCPL-5120, HCPL-5121, and 5962-04204 Application Information Data Sheet Undervoltage Lockout Feature Figure37 Undervoltage Lockout The HCPL-512x contains an under voltage lockout (UVLO) 14 feature that is designed to protect the IGBT under fault 12 conditions which cause the HCPL-512x supply voltage V (equivalent to the fully charged IGBT gate voltage) to drop GE - 10 (12.3, 10.8) A (10.7, 9.2) below a level necessary to keep the IGBT in a low resistance OLT 8 V state. When the HCPL-512x output is in the high state and the UT supply voltage drops below the HCPL-512x V threshold UTP 6 UVLO– O (9.5 < VUVLO– < 12.0), the optocoupler output goes into the low V - O 4 state with a typical delay, UVLO Turn Off Delay, of 0.6 μs. 2 When the HCPL-512x output is in the low state and the supply (10.7, 0.1) (12.3, 0.1) 0 voltage rises above the HCPL-512x V threshold (11.0 < 0 5 10 15 20 V < 13.5), the optocoupler outpUuVtL gOo+es into the high state (VCC - VEE) - SUPPLY VOLTAGE - V UVLO+ (assuming LED is ON) with a typical delay, UVLO Turn On Delay, of 0.8 μs. Broadcom - 18 -

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: B roadcom Limited: 5962-0420401HPA 5962-0420401HPC 5962-0420401HXA 5962-0420401HYA 5962-0420401HYC HCPL-5120 HCPL-5120-100 HCPL-5120-200 HCPL-5120-300 HCPL-5121 HCPL-5121-100 HCPL-5121-200 HCPL-5121-300