HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N HCMOS Compatible, High CMR, 10 MBd Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-261A family of optically coupled gates shown • HCMOS/LSTTL/TTL performance compatible on this data sheet provide all the benefits of the in- • 1000 V/µs minimum Common Mode Rejection (CMR) dustry standard 6N137 family with the added benefit at V = 50 V (HCPL-261A family) and 15 kV/µs of HCMOS compatible input cur rent. This allows direct CM minimum CMR at V = 1000 V (HCPL-261N family) interface to all common circuit topologies without CM • High speed: 10 MBd typical additional LED buffer or drive components. The Al- GaAs LED used allows lower drive currents and reduc- • AC and DC performance specified over industrial es degradation by using the latest LED tech nol ogy. On temperature range -40°C to +85°C the single channel parts, an enable output allows the de- • Available in 8 pin DIP, SOIC-8 packages tector to be strobed. The output of the detector IC is an • Safety approval: open collector schottky-clamped transistor. The internal shield provides a mini mum common mode transient im- – UL recognized per UL1577 3750 V rms for 1 minute munity of 1000 V/µs for the HCPL-261A family and 15000 and 5000 V for 1 minute (Option 020) rms V/µs for the HCPL-261N family. – CSA Approved – IEC/EN/DIN EN 60747-5-5 approved Functional Diagram Applications HCPL-261A/261N HCPL-263A/263N HCPL-061A/061N HCPL-063A/063N • Low input current (3.0 mA) HCMOS compatible NC 1 8 VCC ANODE 1 1 8 VCC version of 6N137 optocoupler ANODE 2 7 VE CATHODE 1 2 7 VO1 • Isolated line receiver CATHODE 3 6 VO CATHODE 2 3 6 VO2 • Simplex/multiplex data transmission NC 4 5 GND ANODE 2 4 5 GND • Computer-peripheral interface SHIELD SHIELD • Digital isolation for A/D, D/A conversion TRUTH TABLE TRUTH TABLE • Switching power supplies (POSITIVE LOGIC) (POSITIVE LOGIC) LED ENABLE OUTPUT LED OUTPUT • Instrumentation input/output isolation ON H L ON L OFF H H OFF H • Ground loop elimination ON L H OFF L H • Pulse transformer replacement ON NC L OFF NC H The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is required. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Selection Guide Widebody Minimum CMR Inpu t 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic On- Single Dual Single Dual Single Single and dV/dt V Current Output Channel Channel Channel Channel Channel Dual Channel CM (V/µs) (V) (mA) Enable Package Package Package Package Package Packages NA NA 5 YES 6N137[1] HCPL-0600[1] HCNW137[1] NO HCPL-2630[1] HCPL-0630[1] 5,000 50 YES HCPL-2601[1] HCPL-0601[1] HCNW2601[1] NO HCPL-2631[1] HCPL-0631[1] 10,000 1,000 YES HCPL-2611[1] HCPL-0611[1] HCNW2611[1] NO HCPL-4661[1] HCPL-0661[1] 1,000 50 YES HCPL-2602[1] 3,500 300 YES HCPL-2612[1] 1,000 50 3 YES HCPL-261A HCPL-061A NO HCPL-263A HCPL-063A 1,000[2] 1,000 YES HCPL-261N HCPL-061N NO HCPL-263N HCPL-063N 1,000 50 12.5 [3] HCPL-193x[1] HCPL-56xx[1] HCPL-66xx[1] Notes: 1. Technical data are on separate Avago publications. 2. 15 kV/µs with V = 1 kV can be achieved using Avago application circuit. CM 3. Enable is available for single channel products only, except for HCPL-193x devices. Schematic HCPL-261A/261N HCPL-263A/263N HCPL-061A/061N HCPL-063A/063N IF ICC VCC ICC 8VCC 2+ 8 1 IF1 IO VO + IO1 7VO1 6 VF1 – VF 2 – GND SHIELD 3 SHIELD 5 IE 7 3 IF2 VE IO2 – VO2 6 USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED VF2 BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16). + 4 GND SHIELD 5 2

Ordering Information HCPL-xxxx is UL Recognized with 3750 V for 1 minute per UL1577. rms Option UL 5000 RoHS Non RoHS Surface Gull Tape Vrms/1 IEC/EN/DIN EN Part number Compliant Compliant Package Mount Wing & Reel Minute rating 60747-5-5 Quantity -000E No option 50 per tube -300E #300 X X 50 per tube -500E #500 X X X 1000 per reel -020E #020 300mil X 50 per tube HCPL-261A -320E -320 DIP-8 X X X 50 per tube -520E -520 X X X X 1000 per reel -060E #060 X 50 per tube -560E #560 X X X X 1000 per reel -000E No option 50 per tube -300E #300 X X 50 per tube -500E #500 X X X 1000 per reel -020E #020 X 50 per tube HCPL- 300mil -320E #320 X X X 50 per tube 261N DIP-8 -520E -520 X X X X 1000 per reel -060E #060 X 50 per tube -360E #360 X X X 50 per tube -560E - X X X X 1000 per reel -000E No option 50 per tube -300E #300 X X 50 per tube -500E #500 300mil X X X 1000 per reel HCPL-263A -020E #020 DIP-8 X 50 per tube -320E #320 X X X 50 per tube -520E -520 X X X X 1000 per reel -000E No option 50 per tube -300E #300 X X 50 per tube HCPL- -500E #500 300mil X X X 1000 per reel 263N -020E #020 DIP-8 X 50 per tube -320E #320 X X X 50 per tube -520E #520 X X X X 1000 per reel -000E No option X 100 per tube HCPL-061A -500E #500 X X 1500 per reel HCPL- SO-8 -060E #060 X X 100 per tube 061N -560E #560 X X X 1500 per reel HCPL-063A -000E No option X 100 per tube HCPL- SO-8 -500E #500 X X 1500 per reel 063N To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-261A-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: HCPL-263N to order product of 300mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE‘. 3

HCPL-261A/261N/263A/263N Outline Drawing Pin Location (for reference only) 9.40 (0.370) 9.90 (0.390) 8 7 6 5 TYPE NUMBER OPTION CODE* 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) A XXXXZ DATE CODE 6.60 (0.260) YYWW 7.36 (0.290) 7.88 (0.310) 5 TYP. PIN ONE 1 2 3 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES). 3.56 ± 0.13 4.70 (0.185) MAX. (0.140 ± 0.005) * MARKING CODE LETTER FOR OPTION NUMBERS. "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. 0.51 (0.020) MIN. 2.92 (0.115) MIN. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 0.76 (0.030) 0.65 (0.025) MAX. 1.40 (0.056) 2.28 (0.090) 2.80 (0.110) Figure 1. 8-Pin dual in-line package device outline drawing. LAND PATTERN RECOMMENDATION 9.65 ± 0.25 1.02 (0.040) (0.380 ± 0.010) 8 7 6 5 6.350 ± 0.25 10.9 (0.430) (0.250 ± 0.010) 1 2 3 4 2.0 (0.080) 1.27 (0.050) 1.780 9.65 ± 0.25 (0.070) (0.380 ± 0.010) 1.19 MAX. (0.047) 7.62 ± 0.25 MAX. (0.300 ± 0.010) 0.20 (0.008) 3.56 ± 0.13 (0.140 ± 0.005) 0.33 (0.013) 1.080 ± 0.320 (0.043 ± 0.013) 0.635 ± 0.25 (0.025 ± 0.010) 12 NOM. 2.540 0.635 ± 0.130 (0.100) (0.025 ± 0.005) BSC DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Figure 2. Gull wing surface mount option #300. 4

HCPL-061A/061N/063A/063N Outline Drawing LAND PATTERN RECOMMENDATION 8 7 6 5 5.994 ± 0.203 (0.236 ± 0.008) XXX 3.937 ± 0.127 YWW TYPE NUMBER 7.49 (0.295) (0.155 ± 0.005) (LAST 3 DIGITS) DATE CODE 1 2 3 4 1.9 (0.075) 0.406 ± 0.076 (0.016 ± 0.003) (10..207500)BSC 0.64 (0.025) * 5.080 ± 0.127 7 0.432 45 X (0.200 ± 0.005) (0.017) 3.175 ± 0.127 (0.125 ± 0.005) 0.228 ± 0.025 1.524 (0.009 ± 0.001) (0.060) 0.203 ± 0.102 (0.008 ± 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 0.305MIN. 5.207 ± 0.254 (0.205 ± 0.010) (0.012) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Figure 3. 8-Pin Small Outline Package Device Drawing. Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-261A and HCPL-261N families have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-5 5

Insulation and Safety Related Specifications 8-Pin DIP (300 Mil) SO-8 Parameter Symbol Value Value Units Conditions Minimum External Air L(101) 7.1 4.9 mm Measured from input terminals to Gap (External output terminals, shortest distance Clearance) through air. Minimum External L(102) 7.4 4.8 mm Measured from input terminals to Tracking (External output terminals, shortest distance Creepage) path along body. Minimum Internal Plastic 0.08 0.08 mm Through insulation distance, conductor Gap (Internal Clearance) to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance CTI 200 200 Volts DIN IEC 112/ VDE 0303 Part 1 (Comparative Tracking Index) Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 – surface mount classification is Class A in accordance with CECC 00802. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description Symbol PDIP Option 060 SO-8 Option 060 Unit Installation classification per DIN VDE 0110, Table 1 for rated mains voltage ≤ 150 V I – IV I – IV rms for rated mains voltage ≤ 300 V I – IV I – IV rms for rated mains voltage ≤ 600 V I – III I – III rms Climatic Classification 40/85/21 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 2 Maximum Working Insulation Voltage V 630 567 V IORM peak Input to Output Test Voltage, Method b* V 1181 1063 V PR peak V x 1.875 = V , 100% Production Test with t =1 sec, IORM PR m Partial discharge < 5 pC Input to Output Test Voltage, Method a* V 1008 907 V PR peak V x 1.6 = V , Type and Sample Test, t =10 sec, IORM PR m Partial discharge < 5 pC Highest Allowable Overvoltage V 6000 6000 V IOTM peak (Transient Overvoltage t = 60 sec) ini Safety-limiting values – maximum values allowed in the event of a failure Case Temperature T 175 150 °C S Input Current I 230 150 mA S, INPUT Output Power P 600 600 mW S, OUTPUT Insulation Resistance at T, V = 500 V R ≥109 ≥109 W S IO S * Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a detailed description. 6

Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T -55 125 °C S Operating Temperature T -40 +85 °C A Average Input Current I 10 mA 1 F(AVG) Reverse Input Voltage V 3 Volts R Supply Voltage V -0.5 7 Volts 2 CC Enable Input Voltage V -0.5 5.5 Volts E Output Collector Current (Each Channel) I 50 mA O Output Power Dissipation (Each Channel) P 60 mW 3 O Output Voltage (Each channel) V -0.5 7 Volts O Lead Solder Temperature 260°C for 10 s, 1.6 mm Below Seating Plane (Through Hole Parts Only) Solder Reflow Temperature Profile See Package Outline Drawings section (Surface Mount Parts Only) Recommended Operating Conditions Parameter Symbol Min. Max. Units Input Voltage, Low Level V -3 0.8 V FL Input Current, High Level I 3.0 10 mA FH Power Supply Voltage V 4.5 5.5 Volts CC High Level Enable Voltage V 2.0 V Volts EH CC Low Level Enable Voltage V 0 0.8 Volts EL Fan Out (at R = 1 kΩ) N 5 TTL Loads L Output Pull-up Resistor R 330 4k Ω L Operating Temperature T -40 85 °C A 7

Electrical Specifications Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified. A Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note High Level Output I 3.1 100 µA V = 5.5 V, V = 5.5 V, 4 18 OH CC O Current V = 0.8 V, V = 2.0 V F E Low Level Output V 0.4 0.6 V V = 5.5 V, I = 13 mA 5, 8 4, 18 OL CC OL Voltage (sinking), I = 3.0 mA, F V = 2.0 V E High Level Supply I 7 10 mA V = 0.5 V** V = 5.5 V 4 CCH E CC Current 9 15 Dual Channel I = 0 mA F Products*** Low Level Supply I 8 13 mA V = 0.5 V** V = 5.5 V CCL E CC Current 12 21 Dual Channel IF = 3.0 mA Products*** High Level Enable I -0.6 -1.6 mA V = 5.5 V, V = 2.0 V EH CC E Current** Low Level Enable I -0.9 -1.6 mA V = 5.5 V, V = 0.5 V EL CC E Current** Input Forward V 1.0 1.3 1.6 V I = 4 mA 6 4 F F Voltage Temperature Co- ∆V/∆T -1.25 mV/°C I = 4 mA 4 F A F efficient of Forward Voltage Input Reverse BV 3 5 V I = 100 µA 4 R R Breakdown Voltage Input Capacitance C 60 pF f = 1 MHz, V = 0 V IN F *All typical values at T = 25°C, V = 5 V A CC **Single Channel Products only (HCPL-261A/261N/061A/061N) ***Dual Channel Products only (HCPL-263A/263N/063A/063N) 8

Switching Specifications Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified. A Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input Current Threshold I 1.5 3.0 mA V = 5.5 V, V = 0.6 V, 7, 10 18 THL CC O High to Low I >13 mA (Sinking) O Propagation Delay t 52 100 ns I = 3.5 mA 9, 11, 4, 9, PLH F Time to High Output V = 5.0 V, 12 18 CC Level V = Open, E C = 15 pF, Propagation Delay t 53 100 ns L 9, 11, 4, 10, PHL R = 350 Ω Time to Low Output L 12 18 Level Pulse Width Distortion PWD 11 45 ns 9, 13 17, 18 |t - t | PHL PLH Propagation Delay Skew t 60 ns 24 11, 18 PSK Output Rise Time t 42 ns 9, 14 4, 18 R Output Fall Time t 12 ns 9, 14 4, 18 F Propagation Delay t 19 ns I = 3.5 mA 15, 12 EHL F Time of Enable V = 5.0 V, 16 CC from V to V V = 0 V, V = 3 V, EH EL EL EH Propagation Delay t 30 ns C = 15 pF, 15, 12 ELH L Time of Enable R = 350 Ω 16 L from V to V EL EH *All typical values at T = 25°C, V = 5 V. A CC Common Mode Transient Immunity Specifications, All values at T = 25°C A Parameter Device Symbol Min. Typ. Max. Units Test Conditions Fig. Note Output High HCPL-261A |CM | 1 5 kV/µs V = 50 V V = 5.0 V, 17 4, 13, H CM CC Level Common HCPL-061A R = 350 Ω, 15, 18 L Mode Transient HCPL-263A I = 0 mA, F Immunity HCPL-063A T = 25°C A V = 2 V HCPL-261N 1 5 kV/µs V = 1000 V O(MIN) CM HCPL-061N HCPL-263N 15 25 kV/µs Using Avago 20 4, 13, HCPL-063N App Circuit 15 Output Low HCPL-261A |CM| 1 5 kV/µs V = 50 V V = 5.0 V, 17 4, 14, L CM CC Level Common HCPL-061A R = 350 Ω, 15, 18 L Mode Transient HCPL-263A I = 3.5 mA, F Immunity HCPL-063A V = 0.8 V O(MAX) HCPL-261N 1 5 kV/µs V = 1000 V T = 25°C CM A HCPL-061N HCPL-263N 15 25 kV/µs Using Avago 20 4, 14, HCPL-063N App Circuit 15 9

Package Characteristics All Typicals at T = 25°C A Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Note Input-Output V 3750 V rms RH ≤ 50%, 5, 6 ISO Momentary With- t = 1 min., stand Voltage** OPT 0 20† 5000 T = 25°C 5, 7 A Input-Output R 1012 Ω V = 500 Vdc 4, 8 I-O I-O Resistance Input-Output C 0.6 pF f = 1 MHz, 4, 8 I-O Capacitance T = 25°C A Input-Input I Dual Channel 0.005 µA RH ≤ 45%, 19 I-I Insulation t = 5 s, Leakage Current V = 500 V I-I Resistance R Dual Channel 1011 Ω 19 I-I (Input-Input) Capacitance C Dual 8-pin DIP 0.03 pF f = 1 MHz 19 I-I (Input-Input) Dual SO-8 0.25 *Ratings apply to all devices except otherwise noted in the Package column. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equip- ment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” †For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only. Notes: 1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average cur- rent does not exceed 10 mA. 2. 1 minute maximum. 3. Derate linearly above 80 °C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package. 4. Each channel. 5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V for 1 second (leakage detec- RMS tion current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in the IEC/EN/ I-O DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V for 1 second (leakage detec- RMS tion current limit, I ≤ 5 µA). I-O 8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. 9. The t propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of PLH the output pulse. 10. The t propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of PHL the output pulse. 11. Propagation delay skew (t ) is equal to the worst case difference in t and/or t that will be seen between any two units under the same PSK PLH PHL test conditions and operating temperature. 12. Single channel products only (HCPL-261A/261N/061A/061N). 13. Common mode transient immunity in a Logic High level is the maximum tolerable |dV /dt| of the common mode pulse, V , to assure that CM CM the output will remain in a Logic High state (i.e., V > 2.0 V). o 14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dV /dt| of the common mode pulse, V , to assure that CM CM the output will remain in a Logic Low state (i.e., V < 0.8 V). O 15. For sinusoidal voltages (|dV /dt|)max = πf V . CM CM CM(P-P) 16. Bypassing of the power supply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoup ler as shown in Figure 19. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 17. Pulse Width Distortion (PWD) is defined as the difference between t and t for any given device. PLH PHL 18. No external pull up is required for a high logic state on the enable input of a single channel product. If the V pin is not used, tying V to V E E CC will result in improved CMR performance. 19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only. 10

A A – HIGH LEVEL OUTPUT CURRENT – µOH 110550-60 -40 -20 0 20 40VVVVCOEF6 C ===0 =025 . .58V85. 0 5VV V100 – LOW LEVEL OUTPUT CURRENT – mOL 682400000-60 -40 -20 0 20 40VIVVFCEO 6= CL=0 3 ==2. 5 05V8 .m 06V AV100 I– INPUT FORWARD CURRENT – mAF 1010.00010....110001.0TA =1 .815 C 1.2 1.3 VTT+–IFFAA1 ==.4 4205 CC1.5 I I TA – TEMPERATURE – C TA – TEMPERATURE – C VF – FORWARD VOLTAGE – V Figure 4. Typical high level output current vs. Figure 5. Low level output current vs. temper- Figure 6. Typical diode input forward current temperature. ature. characteristic. V 5.0 – 0.6 GE VCC = 5.5 V V A VE = 2 V AGE – 4.0 RL = 350 Ω T VOLT 0.5 IO = 16 mA IF = 3.0 mA OLT 3.0 RL = 1 kΩ TPU IO = 12.8 mA T V OU 0.4 – OUTPUO 21..00 RL = 4 kW OW LEVEL 0.3 IO = 9.6 mA V L – IO = 6.4 mA 0 OL 0.2 0 0.5 1.0 1.5 2.0 V -60 -40 -20 0 20 40 60 80 100 IF – FORWARD INPUT CURRENT – mA TA – TEMPERATURE – C Figure 7. Typical output voltage vs. forward Figure 8. Typical low level output voltage vs. input current. temperature. HCPL-261A/261N +5 V PULSE GEN. IF 1 VCC 8 Z O = 50 Ω t f = t r = 5 ns 0.1 µF 2 7 BYPASS RL INPUT OUTPUT VO MONITORING 3 6 MONITORING NODE *CL NODE RM 4 5 GND *C L IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. INPUT I F = 3.5 mA 90% 90% VOH IF I F = 1.75 mA tPHL tPLH 10% 10% VOL OUTPUT VO 1.5 V trise tfall Figure 9. Test circuit for t and t . PHL PLH 11

mA 2.0 120 120 SHOLD CURRENT – 11..05 RRLL == 315 k0Ω Ω ATION DELAY – ns1806000 TRTRPPLLLL ==HH 41 kkΩΩ ATION DELAY – ns1068000 TRPLL =H 4 kΩ TRPLL =H 1 kΩ E G G TPLH T THR 0.5 RL = 4 kΩ ROPA 40 TRPLH =L 350 Ω, 1 kΩ, 4 kΩ ROPA 40 TRPLH =L 350 Ω, 1 kΩ, 4 kRΩL = 350 Ω U P TPLH P – INP VVCOC = =0 .56 VV t– p 20 RL = 350 kΩ IVFC =C 3 =.5 5 m VA t– p 20 TVAC C= =2 55 VC H 0 0 0 T -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 I TA – TEMPERATURE – C TA – TEMPERATURE – C IF – PULSE INPUT CURRENT – mA Figure 10. Typical input threshold current vs. Figure 11. Typical propagation delay vs. tem- Figure 12. Typical propagation delay vs. pulse temperature. perature. input current. 60 160 VCC = 5 V trise 50 RL = 4 kΩ ns140 IF = 3.5 mA tfall – ns 40 VIFC =C 3 =.5 5 m VA L TIME 120 RL = 4 kΩ D – 30 FAL 60 PW SE, RL = 1 kΩ 20 RI 40 10 RL = 1 kΩ RL = 350 Ω t, t – rf 20 RL = 350 Ω 0 0 RL = 350 Ω, 1 kΩ, 4 kΩ -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – C TA – TEMPERATURE – C Figure 13. Typical pulse width distortion vs. Figure 14. Typical rise and fall time vs. temperature. temperature. 12

PULSE GEN. Z O = 50 Ω t f = t r = 5 ns INPUT VE MONITORING NODE HCPL-261A/261N +5 V 1 VCC 8 3.5I FmA 2 7 0B.Y1P µAFSS RL OUTPUT VO 3 6 MONITORING *CL NODE – ns120 VCC = 5 V 4 GND 5 LAY VVEEHL == 03 VV DE 90 IF = 3.5 mA ON tELH, RL = 4 kΩ * C L IPSR AOPBPER AONXDIM SATTREALYY W15IR pIFN GW CHAICPHA ICNICTALUNDCEES. AGATI 60 3.0 V ROP tELH, RL = 1 kΩ INPUT P VE 1.5 V LE 30 tELH, RL = 350 Ω B tEHL tELH ENA tEHL, RL = 350 Ω, 1k Ω, 4 kΩ OUTPUVOT 1.5 V t– E 0-60 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – C Figure 15. Test circuit for t and t . Figure 16. Typical enable propaga tion delay vs. temperature. EHL ELH HCPL-261A/-261N/-061A/-061N Only. HCPL-261A/261N 1 VCC 8 +5 V VCM 2 7 0B.Y1P µAFSS 350 Ω A B IF 3 6 OMUOTNPITUOTR VION G NT – IS 800 HCPL-261AP/2S6 (1mNW O)PTION 060 ONLY NODE RE 700 IS (mA) VFF 4 GND 5 UR 600 C T U 500 P PULSE GEN. + _ , INS 400 O Z = 50 Ω P R – 300 VC M (PEAK) WE 200 VCM O 0 V P SWITCH AT A: I F = 0 mA T 100 VO 5 V VO (min.) CMH UTPU 00 25 50 75 100 125 150 175 200 SWITCH AT B: I F = 3.5 mA O VO VO (max.) TS – CASE TEMPERATURE – C 0.5 V CML Figure 17. Test circuit for common mode transient immunity and typical waveforms. Figure 18. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-5. 13

SINGLE CHANNEL PRODUCTS Application Information GND BUS (BACK) Common-Mode Rejection for HCPL- 261A/HCPL-261N Families: VC C BUS (FRONT) Figure 20 shows the recomm ended N.C. drive circuit for the HCPL-261N/- 261A for optimal common-mode ENABLE (IF USED) rejection performance. Two main 0.1µF points to note are: N.C. OUTPUT 1 1. The enable pin is tied to V rather CC than floating (this applies to N.C. single-channel parts only). ENABLE 0.1µF (IF USED) 2. Two LED-current setting resistors are used instead of one. This is to balance I variation during N.C. OUTPUT 2 LED common-mode transients. If the enable pin is left floating, it is possible for common-mode tran- 10 mm MAX. (SEE NOTE 16) sients to couple to the enable pin, resulting in common-mode failure. This failure mechanism only occurs DUAL CHANNEL PRODUCTS when the LED is on and the output GND BUS (BACK) is in the Low State. It is identified as occurring when the transient output VC C BUS (FRONT) voltage rises above 0.8 V. Therefore, the enable pin should be connected to either V or logic-level high for CC OUTPUT 1 best common-mode performance 0.1µF with the output low (CMR). This OUTPUT 2 L failure mechanism is only present in single-channel parts (HCPL-261N, -261A, -061N, -061A) which have the 10 mm MAX. (SEE NOTE 16) enable function. Figure 19. Recommended printed circuit board layout. Also, common-mode transients can capacitively couple from the LED an- ode (or cathode) to the output-side ground causing current to be shunt- ed away from the LED (which can be * HCPL-261A/261N bad if the LED is on) or conversely VCC 1 8 VCC+ 357 Ω 0.01 µF cause current to be injected into the (MAX.) LED (bad if the LED is meant to be 2 7 350 Ω off). Figure 21 shows the parasitic 357 Ω (MAX.) capacitances which exists between 3 6 VO LED anode/cathode and output 74LS04 ground (C and C ). Also shown in OR ANY TOTEM-POLE 4 5 GND LA LC OUTPUT LOGIC GATE SHIELD Figure 21 on the input side is an AC- * equivalent circuit. GND1 GND2 * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1). *Higher CMR may be obtainable by connecting pins 1, 4 to input ground (Gnd1). Figure 20. Recommended drive circuit for HCPL-261A/-261N families for high-CMR (similar for HCPL-263A/-263N). 14

Table 1 indicates the directions of I and I flow depend- CMR with Other Drive Circuits LP LN ing on the direction of the common-mode transient. CMR performance with drive circuits other than that For transients occurring when the LED is on, common- shown in Figure 20 may be enhanced by following these mode rejec tion (CMR, since the output is in the “low” guidelines: L state) depends upon the amount of LED current drive (I). F 1. Use of drive circuits where current is shunted from For conditions where I is close to the switching thresh- F the LED in the LED “off” state (as shown in Figures 22 old (I ), CMR also depends on the extent which I and I TH L LP LN and 23). This is beneficial for good CMR . balance each other. In other words, any condition where H common-mode transients cause a momentary decrease 2. Use of I > 3.5 mA. This is good for high CMR. FH L in I (i.e. when dV /dt>0 and |I | > |I |, referring to Table F CM FP FN Using any one of the drive circuits in Figures 22-24 with 1) will cause common-mode failure for transients which I = 10 mA will result in a typical CMR of 8 kV/µs for the are fast enough. F HCPL-261N family, as long as the PC board layout prac- Likewise for common-mode transients which occur tices are followed. Figure 22 shows a circuit which can when the LED is off (i.e. CMR , since the output is “high”), be used with any totem-pole-output TTL/LSTTL/HCMOS H if an imbalance between I and I results in a transient logic gate. The buffer PNP transistor allows the circuit to LP LN I equal to or greater than the switching threshold of the be used with logic devices which have low current-sink- F optocoupler, the transient “signal” may cause the output ing capability. It also helps maintain the driving-gate to spike below 2 V (which consti tutes a CMR failure). power-supply current at a constant level to minimize H ground shifting for other devices connected to the in- By using the recommended circuit in Figure 20, good put-supply ground. CMR can be achieved. (In the case of the -261N families, a minimum CMR of 15 kV/µs is guaranteed using this cir- When using an open-collector TTL or open-drain CMOS cuit.) The balanced I -setting resistors help equalize I logic gate, the circuit in Figure 23 may be used. When LED LP and I to reduce the amount by which I is modulated using a CMOS gate to drive the optocoupler, the circuit LN LED from transient coupling through C and C . shown in Figure 24 may be used. The diode in parallel LA LC with the R speeds the turn-off of the optocoupler LED LED. VCC 1 8 VCC+ HCPL-261X 420 Ω 1 1/2 RLED 0.01 µF (MAX) 2 7 350 Ω ILP 2N3906 2 1/2 RLED 3 ILN CLA 6 VO 74(LA5N0Y4 (ANY PNP) LED TTL/CMOS 3 15 pF GATE) CLC 4 5 GND SHIELD 4 + – VCM Figure 21. AC equivalent circuit for HCPL-261X. Figure 22. TTL interface circuit for the HCPL-261A/-261N families. 15

VCC HCPL-261X VCC HCPL-261A/261N 1 1N4148 1 820 Ω 2 2 74HC00 74HC04 750 Ω (OR ANY LED (OR ANY LED OPEN-COLLECTOR/ 3 TOTEM-POLE 3 OPEN-DRAIN OUTPUT LOGIC LOGIC GATE) GATE) 4 4 Figure 23. TTL open-collector/open drain gate drive circuit for Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families. HCPL-261A/-261N families. Table 1. Effects of Common Mode Pulse Direction on Transient I LED If |I | < |I |, If |I | > |I |, LP LN LP LN LED I Current LED I Current F F If dV /dt Is: then I Flows: and I Flows: Is Momentarily: Is Momentarily: CM LP LN positive (>0) away from LED away from LED increased decreased anode through C cathode through C LA LC negative (<0) toward LED toward LED decreased increased anode through C cathode through C LA LC Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes coup lers, differences in propaga tion delays will cause how quickly a logic signal propagates through a sys- the data to arrive at the outputs of the opto couplers at tem. The propaga tion delay from low to high (t ) is the different times. If this difference in propagation delay PLH amount of time required for an input signal to propa- is large enough it will determine the maximum rate at gate to the output, causing the output to change from which parallel data can be sent through the optocou- low to high. Similarly, the propagation delay from high plers. to low (t ) is the amount of time required for the input PHL Propagation delay skew is defined as the difference be- signal to propagate to the output, causing the output to tween the minimum and maximum propaga tion delays, change from high to low (see Figure 9). either t or t , for any given group of optocouplers PLH PHL Pulse-width distortion (PWD) results when t and t which are operating under the same conditions (i.e., the PLH PHL differ in value. PWD is defined as the difference between same drive current, supply voltage, output load, and op- t and t and often determines the maximum data erating temperature). As illustrated in Figure 25, if the in- PLH PHL rate capability of a transmission system. PWD can be ex- puts of a group of optocouplers are switched either ON pressed in percent by dividing the PWD (in ns) by the or OFF at the same time, t is the differ ence between PSK minimum pulse width (in ns) being transmitted. Typical- the shortest propagation delay, either t or t , and the PLH PHL ly, PWD on the order of 20-30% of the minimum pulse longest propagation delay, either t or t . PLH PHL width is tolerable; the exact figure depends on the par- As mentioned earlier, t can determine the maximum ticular appli cation (RS232, RS422, T-1, etc.). PSK parallel data transmission rate. Figure 26 is the timing Propagation delay skew, t , is an important parameter diagram of a typical parallel data application with both PSK to con sider in parallel data applications where synchro- the clock and the data lines being sent through opto- nization of signals on parallel data lines is a con cern. If couplers. the parallel data is being sent through a group of opto- 16

The figure shows data and clock signals at the inputs and to change before the clock signal has arrived. From these outputs of the optocouplers. To obtain the maximum considera tions, the absolute minimum pulse width that data transmission rate, both edges of the clock signal are can be sent through optocouplers in a parallel applica- being used to clock the data; if only one edge were used, tion is twice t . A cautious design should use a slightly PSK the clock signal would need to be twice as fast. longer pulse width to ensure that any additional uncer- tainty in the rest of the circuit does not cause a prob- Propagation delay skew repre sents the uncertainty of lem. where an edge might be after being sent through an op- tocoupler. Figure 26 shows that there will be uncertainty The t specified optocouplers offer the advantages of PSK in both the data and the clock lines. It is important that guaran teed specifications for propaga tion delays, pulse- these two areas of uncer tainty not overlap, otherwise width distortion, and propagation delay skew over the the clock signal might arrive before all of the data out- recommended temperature, input current, and power puts have settled, or some of the data outputs may start supply ranges. IF 50% VO 1.5 V TPHL IF 50% TPLH VO 1.5 V tPSK Figure 25. Illustration of propagation delay skew – t . PSK DATA INPUTS CLOCK DATA OUTPUTS tPSK CLOCK tPSK Figure 26. Parallel data transmission example. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0561EN AV02-0391EN - April 30, 2013

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: B roadcom Limited: HCPL-063A-500E HCPL-261A HCPL-261A#020 HCPL-261A#060 HCPL-261A#300 HCPL-261A#500 HCPL- 261A#560 HCPL-261A-000E HCPL-261A-020E HCPL-261A-060E HCPL-261A-300E HCPL-261A-320E HCPL- 261A-500E HCPL-261A-520 HCPL-261A-520E HCPL-261A-560E HCPL-261N HCPL-261N#020 HCPL-261N#060 HCPL-261N#300 HCPL-261N#320 HCPL-261N#360 HCPL-261N#500 HCPL-261N-000E HCPL-261N-020E HCPL- 261N-060E HCPL-261N-300E HCPL-261N-320E HCPL-261N-360E HCPL-261N-500E HCPL-261N-520E HCPL- 263A#300 HCPL-263A#320 HCPL-263A#500 HCPL-263A-300E HCPL-263A-320E HCPL-263A-500E HCPL-263A- 520 HCPL-263A-520E HCPL-263N#300 HCPL-263N#320 HCPL-263N#500 HCPL-263N#520 HCPL-263N-300E HCPL-263N-320E HCPL-263N-500E HCPL-263N-520E HCPL-261N-520 HCPL-261A-320