Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

F S U S B July 2015 4 2 — L FSUSB42 — Low-Power, Two-Port, High-Speed, o w - USB2.0 (480Mbps) UART Switch P o w e r , Features T Description w  Low On Capacitance: 3.7 pF Typical The FSUSB42 is a bi-directional, low-power, two-port, o- P  Low On Resistance: 3.9 Ω Typical high-speed, USB2.0 switch. Configured as a double- o  Low Power Consumption: 1 μA Maximum pole, double-throw switch (DPDT) switch, it is optimized rt , - 15 μA Maximum I over an Expanded Voltage for switching between any combination of high-speed H CCT Range (VIN=1.8 V, VCC=4.4 V) (480 Mbps) or Full-Speed (12 Mbps) sources. ig  Wide -3 db Bandwidth: > 720 MHz The FSUSB42 is compatible with the requirements of h-  Packaged in: USB2.0 and features an extremely low on capacitance S p - 10-Lead UMLP (1.4 x 1.8 mm) (CON) of 3.7 pF. The wide bandwidth of this device e - 10-Lead MSOP (720 MHz) exceeds the bandwidth needed to pass the ed  8 kV ESD Rating, >16 kV Power / GND ESD Rating tahnirdd hpahramsoen icd, isretosrutilotinng. inS uspigenriaolrs wcihtha nmnienli-mtou-cmh aendngeel , U  Over-Voltage Tolerance (OVT) on all USB Ports crosstalk also minimizes interference. S B Up to 5.25 V without External Components 2 The FSUSB42 contains special circuitry on the switch . 0 Applications I/O pins for applications where the VCC supply is ( powered-off (V =0 V), which allows the device to 4 CC 8  Cell phone, PDA, Digital Camera, and Notebook withstand an over-voltage condition. This device is 0 designed to minimize current consumption even when M  LCD Monitor, TV, and Set-Top Box the control voltage applied to the SEL pin is lower than b p the supply voltage (VCC). This feature is especially s valuable to ultra-portable applications, such as cell ) U phones, allowing for direct interface with the general- A purpose I/Os of the baseband processor. Other R applications include switching and connector sharing in T portable cell phones, PDAs, digital cameras, printers, S and notebook computers. w i t c Ordering Information h Operating Temperature Part Number Top Mark Package Range 10-Lead, Quad, Ultrathin Molded Leadless Package FSUSB42UMX HE -40 to +85°C (UMLP), 1.4 x 1.8 mm 10-Lead, Molded Small-Outline Package (MSOP) FSUSB42MUX FSUSB42 -40 to +85°C JEDEC MO-187, 3.0 mm Wide HSD1+ D+ HSD2+ HSD1- D- HSD2- Sel Control /OE Figure 1. Analog Symbol © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25

F S Pin Assignments U S B 4 VCC 1 10 /OE 2 — L D- D+ Sel 2 9 HSD2+ o w 2 1 GND 3 10 Sel -P o HSD1- 4 9 Vcc D+ 3 8 HSD2- w e r HSD1+ 5 6 7 8 /OE , T D- 4 7 HSD1+ w HSD2- HSD2+ o - P GND 5 6 HSD1- o r t , H i Figure 2. 10-Lead UMLP (Top-Through View) Figure 3. 10-Lead MSOP (Top-Through View) g h - S p e e d Pin Definitions , U S UMLP Pin# MSOP Pin# Name Description B 2 . 1 3 D+ Common USB Data Bus 0 ( 2 4 D- Common USB Data Bus 4 8 3 5 GND Ground 0 M 4 6 HSD1- Multiplexed Source Input 1 b p 5 7 HSD1+ Multiplexed Source Input 1 s ) 6 8 HSD2- Multiplexed Source Input 2 U A 7 9 HSD2+ Multiplexed Source Input 2 R T 8 10 /OE Switch Enable S 9 1 V Supply Voltage w CC i t 10 2 Sel Switch Select c h Truth Table SEL /OE Function X HIGH Disconnect LOW LOW D+= HSD1+, D-= HSD1- HIGH LOW D+= HSD2+, D-= HSD2- Notes: 1. LOW ≤V . IL 2. HIGH ≥V . IH 3. X=Don’t Care. © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 2

Absolute Maximum Ratings F S U Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be S operable above the recommended operating conditions and stressing the parts to these levels is not recommended. B In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. 4 2 The absolute maximum ratings are stress ratings only. — Symbol Parameter Min. Max. Unit L o V Supply Voltage -0.5 5.6 V w CC - P VCNTRL DC Input Voltage (S, /OE)(4) -0.5 VCC V o w VSW DC Switch I/O Voltage(4) (VCC=0V) -0.50 5.25 V e r IIK DC Input Diode Current -50 mA , T w I DC Output Current 100 mA OUT o - T Storage Temperature -65 +150 °C P STG o r MSL Moisture Sensitivity Level (JEDEC J-STD-020A) 1 Level t , H All Pins 7 i g I/O to GND 8 h - Human Body Model, JEDEC: JESD22-A114 S Power to GND 16 p e ESD D+/D- 9 kV e d , IEC 61000-4-2 System on USB Connector Air Discharge 15 U S Pins D+ & D- Contact 8 B 2 Charged Device Model, JEDEC: JESD22-C101 2 .0 Note: (4 4. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. 8 0 M b p s ) U A R Recommended Operating Conditions T S The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended w operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not it c recommend exceeding them or designing to Absolute Maximum Ratings. h Symbol Parameter Min. Max. Unit V Supply Voltage 2.4 4.4 V CC V Control Input Voltage (S, /OE)(5) 0 V V CNTRL CC V Switch I/O Voltage -0.5 4.5 V SW T Operating Temperature -40 +85 °C A Note: 5. The control input must be held HIGH or LOW and it must not float. © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 3

DC Electrical Characteristics F S U All typical value are at T =25°C unless otherwise specified. A S B T =- 40°C to +85°C 4 A Symbol Parameter Condition V (V) Unit 2 CC Min. Typ. Max. — L V Clamp Diode Voltage I =-18mA 3.0 -1.2 V IK IN o w 2.4 to 3.6 1.3 - V Input Voltage High V P IH 4.3 1.7 o w 2.4 to 3.6 0.5 e VIL Input Voltage Low V r, 4.3 0.7 T w I Control Input Leakage V =0 to V 0 to 4.3 -1 1 µA o IN SW CC - P 0 Dn, HSD1n, HSD2n o I Off State Leakage 4.3 -2 2 µA OZ 3.6 V rt , H Power-Off Leakage Current V =0 V to 4.3 V, V =0 V I SW CC 0 -2 2 µA i OFF (All I/O Ports) Figure 5 g h - 2.4 4.5 7.5 S R HS Switch On Resistance(6) VSW=0.4 V, ION=-8 mA  p ON Figure 4 3.0 3.9 6.5 e e d ∆RON HS Delta RON(7) VSW=0.4 V, ION=-8 mA 3.0 0.65  , U I Quiescent Supply Current V =0 or V , I =0 4.3 1 µA S CC CNTRL CC OUT B V =2.6 V, V =4.3 V 4.3 10 µA 2 Increase in I Current per CNTRL CC ICCT Control VoltaCgCe and VCC VCNTRL=1.8 V, VCC=4.3 V 4.3 15 µA .0 ( 4 Notes: 8 0 6. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch. M On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports). b 7. Guaranteed by characterization. p s ) U A R T S w i t c h © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 4

F S AC Electrical Characteristics U S All typical value are for V =3.3 V at T =25°C unless otherwise specified. B CC A 4 2 TA=- 40°C to +85°C — Symbol Parameter Condition V (V) Unit CC Min. Typ. Max. L o Turn-On Time R =50 Ω, C =5 pF, V =0.8 V, 2.4 24 40 w tON S, /OE to Output FiLgure 6, FigLure 7 SW 3.0 to 3.6 13 30 ns -P o Turn-Off Time R =50 Ω, C =5 pF, V =0.8 V, 2.4 15 35 w tOFF S, /OE to Output FiLgure 6, FigLure 7 SW 3.0 to 3.6 12 25 ns er , t Propagation Delay8 CL=5 pF, RL=50 Ω, Figure 6, 3.3 0.25 ns Tw PD Figure 8 o - R =50 Ω, C =5 pF, 2.4 2.0 10 P tBBM Break-Before-Make VSLW1=VSW2=L0.8 V, Figure 10 3.0 to 3.6 2.0 6.5 ns or t , OIRR Off Isolation RL=50 Ω, f=240 MHz, Figure 12 3.0 to 3.6 -30 dB H i Non-Adjacent Channel g Xtalk R =50 Ω, f=240 MHz, Figure 13 3.0 to 3.6 -45 dB h Crosstalk L - S R =50 Ω, C =0 pF, Figure 11 720 MHz p L L BW -3db Bandwidth 3.0 to 3.6 e R =50 Ω, C =5 pF, Figure 11 550 MHz e L L d Note: , U 8. Guaranteed by characterization. S B 2 . 0 ( 4 USB High-Speed-Related AC Electrical Characteristics 8 0 M All typical value are for V =3.3 V at T =25°C unless otherwise specified. CC A b p T =- 40ºC to +85ºC s Symbol Parameter Condition VCC (V) A Unit ) U Min. Typ. Max. A R Skew of Opposite Transitions of tSK(P) the Same Output(9) CL=5 pF, RL=50 Ω, Figure 9 20 ps T S R =50 Ω, C =5 pF, w L L tJ Total Jitter(9) tR=tF=500 ps (10-90%) at 200 ps itc 480 Mbps (PRBS=215 – 1) h Note: 9. Guaranteed by characterization. Capacitance T =- 40°C to +85°C A Symbol Parameter Condition Unit Min. Typ. Max. C Control Pin Input Capacitance V =0 V 1.5 IN CC V =3.3 V, /OE=0 V, f=240 MHz, C D+/D- On Capacitance CC 3.7 pF ON Figure 15 C D1n, D2n Off Capacitance V and /OE=3.3 V, Figure 14 2.0 OFF CC © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 5

Test Diagrams F S U S B 4 2 V ON — NC IDn(OFF) L A o w HSDn - Dn VSW P o VSSWW Select w I GND e GND Select ON VVSel= 0 orVVcccc r, GND T w VSel= 0 orVcc **Eachswitchportistestedseparately o RON= VON/ ION -P o r Figure 4. On Resistance Figure 5. Off Leakage t, H i g h - HSD S n Dn tRISE=2.5ns tFALL=2.5ns p e V e GNSDWRS CL RL VVOOUUTT InVVVpCCut–––VV ,V 90% 90% d, U /OE Sel S GND 10% VCC/2 VCC/2 10% B GND 2 . VSel VOH 0 90% 90% (4 GND Output-V 8 OUT 0 RL,RS,andCLarefunctionsoftheapplication VOL t t Mb environment (seeACTablesforspecificvalues) ON OFF p CLincludestestfixtureandstraycapacitance. s) U A Figure 6. AC Test Circuit Load Figure 7. Turn-On / Turn-Off Waveforms R T S w tRISE=500ps tFALL=500ps i t c h +400mV 90% 90% 0V 10% 10% -400mV Output tPHL tPLH Figure 8. Propagation Delay (t t – 500 ps) Figure 9. Intra-Pair Skew Test t RF SK(P) © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 6

Test Diagrams (Continued) F S tRISE=2.5ns U S B Vcc 4 HSDn 90% 2 VSW1 Dn Input---VS1e0l% Vcc/2 — GND VSW2 CL RL VOUT VO0UVT Lo GND w RSGND 0.9*Vout t 0.9*Vout -Po BBM w e VSel RL,RS,andCLarefunctionsoftheapplication r, T GND environment (seeACTablesforspecificvalues) w CLincludestestfixtureandstraycapacitance. o - Figure 10. Break-Before-Make Interval Timing P o r t , NetworkAnalyzer NetworkAnalyzer H RS RS ig h GND VIN VS RT GND VIN VS -Sp VSel GND VSel GND GND ee GND GND RT VOUT R andGNRDarefunctionsoftheapplication GND RRTTVOUT d, U R andR arefunctionsoftheapplication GND enSvironmTent (seeACTablesforspecificvalues). GND SB enSvironmTent (seeACTablesforspecificvalues). Off isolation = 20 Log (VOUT / VIN) 2. 0 Figure 11. Bandwidth Figure 12. Channel Off Isolation ( 4 8 NetworkAnalyzer 0 NC RS M b p GND VIN VS s ) VSel GND U A GND RT R T GND S w GND RT VOUT itc RSandRTarefunctionsoftheapplicationenvironment h (seeACTablesforspecificvalues). GND Crosstalk=20Log(VOUT / VIN) Figure 13. Non-Adjacent Channel-to-Channel Crosstalk Capacitance Capacitance Meter HSDn Meter HSDn S=LOW or HIGH S=LOW or HIGH OE=HIGH OE=LOW Dn Dn Figure 14. Channel Off Capacitance Figure 15. Channel On Capacitance © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 7

F S Physical Dimensions U S B 4 2 0.05 C 1.40 A B — 2X L o w 1.80 -P 1.70 (9X) o PIN#1 IDENT w 0.663 0.563 e 0.05 C r TOP VIEW , 2X T 1 w 2.10 o - 0.10 C 0.50±.05 0.15±.05 0.40 P o r t (10X)0.225 , 0.08 C H 0.025±.025 SEATING C RECOMMENDED ig PLANE LAND PATTERN h - SIDE VIEW 1.45 9X Sp 0.55 0.45 e e 1.40±.05 d , 0.40±.05 (0.20)4X U (9X) 3 0.40 1.85 S B 0.40 2 DETAIL A 6 .0 1 1.80±.05 (10X)0.225 ( 4 PIN#1 IDENT (0.60)4X OPTIONAL MINIMIAL 8 0 10 TOE LAND PATTERN M b 0.20±.05(10X) NOTES: p s 0.10 C A B ) BOTTOM VIEW 0.05 C A . APNAYC KJAEGDEEC D SOTEASN NDOATR DC.ONFORM TO U A B. DIMENSIONS ARE IN MILLIMETERS. R 1.00±.05 C. DIMENSIONS AND TOLERANCES PER T ASME Y14.5M, 2009. S D. LAND PATTERN RECOMMENDATION IS w 45° EXISTING INDUSTRY LAND PATTERN. it 0.40±.05 c E. DRAWING FILENAME: MKT-UMLP10Arev6. h DETAIL A SCALE : 2X PACKAGE EDGE LEAD LEAD OPTION 1 OPTION 2 SCALE : 2X SCALE : 2X Figure 16. 10-Lead, Ultrathin Molded Leadless Package (UMLP) © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 8

F S Physical Dimensions (Continued) U S B 4 2 — L o w - P o w e r , T w o - P o r t , H i g h - S p e e d , U S B 2 . 0 ( 4 8 0 M b p s ) U A R T S w i t c h Figure 17. 10-Lead, Molded Small Outline Package (MSOP) © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 9

F S U S B 4 2 — L o w - P o w e r , T w o - P o r t , H i g h - S p e e d , U S B 2 . 0 ( 4 8 0 M b p s ) U A R T S w i t c h © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com FSUSB42 • Rev. 1.25 10

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