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F S Q 0 7 April 2009 6 5 R Q FSQ0765RQ (cid:151) Green-Mode Fairchild Power Switch (FPS(cid:153)) for G r Quasi-Resonant Operation - e Low EMI and High Efficiency e n - M Features Description o d e ! Optimized for Quasi-Resonant Converter (QRC) A Quasi-Resonant Converter (QRC) generally shows F ! Low EMI through Variable Frequency Control and AVS lower EMI and higher power conversion efficiency than a a (Alternating Valley Switching) conventional hard-switched converter with a fixed ri c ! High-Efficiency through Minimum Voltage Switching switching frequency. The FSQ-series is an integrated h ! Narrow Frequency Variation Range over Wide Load Pulse-Width Modulation (PWM) controller and ild and Input Voltage Variation SenseFET specifically designed for quasi-resonant P ! Advanced Burst-Mode Operation for Low Standby operation and Alternating Valley Switching (AVS). The o Power Consumption PWM controller includes an integrated fixed-frequency w e ! Simple Scheme for Sync Voltage Detection oscillator, Under-Voltage Lockout (UVLO), Leading- r ! Pulse-by-Pulse Current Limit Edge Blanking (LEB), optimized gate driver, internal soft- S w start, temperature-compensated precise current sources ! Various Protection functions: Overload Protection i (OLP), Over-Voltage Protection (OVP), Abnormal for a loop compensation, and self-protection circuitry. tc Over-Current Protection (AOCP), Internal Thermal Compared with a discrete MOSFET and PWM controller h Shutdown (TSD) with Hysteresis, Output Short solution, the FSQ-series can reduce total cost, (F Protection (OSP) component count, size, and weight; while simultaneously P S ! Under-Voltage Lockout (UVLO) with Hysteresis increasing efficiency, productivity, and system reliability. (cid:153) ! Internal Startup Circuit This device provides a basic platform that is well suited ) ! Internal High-Voltage Sense FET (650V) for cost-effective designs of quasi-resonant switching fo flyback converters. r ! Built-in Soft-Start (17.5ms) Q Applications u a s ! Power Supply for LCD TV and Monitor, VCR, SVR, i - STB, and DVD & DVD Recorder R e ! Adapter s o Related Resources n a Visit http://www.fairchildsemi.com/apnotes/ for: n t O ! AN-4134: Design Guidelines for Offline Forward Converters Using Fairchild Power Switch (FPS(cid:153)) pe ! AN-4137: Design Guidelines for Offline Flyback ra Converters Using Fairchild Power Switch (FPS(cid:153)) ti o ! AN-4140: Transformer Design Consideration for n Offline Flyback Converters Using Fairchild Power Switch (FPS(cid:153)) ! AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPS(cid:153)) Flyback Applications ! AN-4145: Electromagnetic Compatibility for Power Converters ! AN-4147: Design Guidelines for RCD Snubber of Flyback ! AN-4148: Audible Noise Reduction Techniques for Fairchild Power Switch Fairchild Power Switch(FPS(cid:153)) Applications ! AN-4150: Design Guidelines for Flyback Converters Using FSQ-Series Fairchild Power Switch (FPS(cid:153)) ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1

F S Ordering Information Q 0 Maximum Output Power(1) 7 6 Product Operating Current R 230V –15%(2) 85-265V Replaces 5 PKG.(5) DS(ON) AC AC R Number Temp. Limit Max. Open Open Devices Q Adapter(3) Frame(4) Adapter(3) Frame(4) (cid:151) FSQ0765RQWDTU TO-220F-6L -25 to +85(cid:176)C 3.5A 1.6Ω 80W 90W 48W 70W FSCM0765R G FSDM0765RB r e Notes: e 1. The junction temperature can limit the maximum output power. n - 2. 230V or 100/115V with doubler. M AC AC 3. Typical continuous power in a non-ventilated enclosed adapter measured at 50(cid:176)C ambient temperature. o d 4. Maximum practical continuous power in an open-frame design at 50(cid:176)C ambient. e F 5. For Fairchild(cid:146)s definition of (cid:147)green(cid:148) Eco Status, please visit: ar http://www.fairchildsemi.com/company/green/rohs_green.html. Eco Status: RoHS. ic h i l d P o w e r S w i t c h ( F P S (cid:153) ) f o r Q u a s i - R e s o n a n t O p e r a t i o n ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 2

F S Application Diagram Q 0 7 6 5 VO R Q (cid:151) G AC r IN e e V n str Drain - M o PWM d Sync GND e F FB V a CC r i c h i l d P o w e r S w FSQ0765R Rev.00 i t c h Figure 1. Typical Flyback Application (F P S (cid:153) Internal Block Diagram ) f o r Q Sync V V Drain u str CC a 5 6 3 1 s i - R AVS OSC e s o V n 0.35/0.55 ref V good a VCC Vref VBurst CC 8V/12V nt I I O FB delay FB 3R PWM p 4 S Q e R SStoafrt-t 2L5E0nBs R Q dGriavteer rat i tON < tOSP o after SS n VOSP LPF AOCP 2 VSD TSD S Q VOCP GND (1.1V) LPF R Q VOVP V good CC FSQ0765R Rev.00 Figure 2. Internal Block Diagram ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 3

F S Pin Configuration Q 0 7 6 5 R Q 6. V (cid:151) str 5. Sync G 4. FB r e 3. V e CC n 2. GND - M 1. Drain o d FSQ0765R Rev.00 e F a Figure 3. Pin Configuration (Top View) r i c h i l d Pin Definitions P o Pin # Name Description w e 1 Drain SenseFET drain. High-voltage power SenseFET drain connection. r S 2 GND Ground. This pin is the control ground and the SenseFET source. w i Power Supply. This pin is the positive supply input. This pin provides internal operating current for tc 3 V CC both startup and steady-state operation. h ( Feedback. This pin is internally connected to the inverting input of the PWM comparator. The F P collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be S 4 FB placed between this pin and GND. If the voltage of this pin reaches 6V, the overload protection (cid:153) triggers, which shuts down the FPS. ) f o Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switching. 5 Sync In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V. r Q u Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At a start-up, the internal high-voltage current source supplies internal bias and charges the external s 6 Vstr capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is disabled. i-R It is not recommended to connect V and Drain together. e str s o n a n t O p e r a t i o n ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 4

F S Absolute Maximum Ratings Q 0 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera- 7 6 ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi- 5 tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The R absolute maximum ratings are stress ratings only. T = 25(cid:176)C, unless otherwise specified. Q A (cid:151) Symbol Parameter Min. Max. Unit G Vstr Vstr Pin Voltage 500 V re V Drain Pin Voltage 650 V e DS n VCC Supply Voltage 20 V -M o V Feedback Voltage Range -0.3 13.0 V FB d e VSync Sync Pin Voltage -0.3 13.0 V F I Drain Current Pulsed 14.4 A a DM r i T = 25(cid:176)C 3.6 c I Continuous Drain Current(6) C A h D i T = 100(cid:176)C 2.28 l C d E Single Pulsed Avalanche Energy(7) 570 mJ P AS o P Total Power Dissipation(Tc=25(cid:176)C) 45 W w D e T Operating Junction Temperature Internally limited (cid:176)C r J S TA Operating Ambient Temperature -25 +85 (cid:176)C w i T Storage Temperature -55 +150 (cid:176)C t STG c h Human Body Model 2 ESD Electrostatic Discharge Capability kV (F Charged Device Model 2 P S Notes: (cid:153) 6. Repetitive rating: Pulse width limited by maximum junction temperature. ) 7. L=81mH, starting TJ=25(cid:176)C. fo r Q u a Thermal Impedance s i T = 25(cid:176)C unless otherwise specified. -R A e Symbol Parameter Value Unit s o θJA Junction-to-Ambient Thermal Resistance(8) 50 (cid:176)C/W na n θJC Junction-to-Case Thermal Resistance(9) 2.8 (cid:176)C/W t O Notes: p e 8. Free standing with no heat-sink under natural convection. r a 9. Infinite cooling condition - refer to the SEMI G30-88. t i o n ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 5

F S Electrical Characteristics Q 0 7 TA = 25°C unless otherwise specified. 6 5 R Symbol Parameter Condition Min. Typ. Max. Unit Q SENSEFET SECTION (cid:151) BVDSS Drain Source Breakdown Voltage VCC = 0V, ID = 100(cid:181)A 650 V G I Zero-Gate-Voltage Drain Current V = 520V, V = 0V 300 (cid:181)A r DSS DS GS e e RDS(ON) Drain-Source On-State Resistance TJ = 25(cid:176)C, ID = 1.8A 1.3 1.6 Ω n - C Output Capacitance V = 0V, V = 25V, f = 1MHz 125 pF M OSS GS DS o td(on) Turn-On Delay Time 27 ns d e t Rise Time 102 ns r F V = 325V, I = 6.5A DD D a td(off) Turn-Off Delay Time 63 ns r i c tf Fall Time 65 ns h i CONTROL SECTION ld P t Maximum On Time T = 25(cid:176)C 8.8 10.0 11.2 (cid:181)s ON.MAX J o t Blanking Time T = 25(cid:176)C, V = 5V 13.5 15.0 16.5 (cid:181)s w B J sync e tW Detection Time Window TJ = 25(cid:176)C, Vsync = 0V 6.0 (cid:181)s r S f Initial Switching Frequency 59.6 66.7 75.8 kHz w S i ΔfS Switching Frequency Variation(11) -25(cid:176)C < TJ < 85(cid:176)C –5 –10 % tc h tAVS AVS Triggering On Time at VIN = 240VDC, Lm = 360μH 4.0 (cid:181)s (F VAVS Threshold(11) FVeoeltadgbeack (&A tVASVS t<risgpgeecre.)d when VAVS>spec 1.2 V PS(cid:153) t Switching Time Variance by AVS(11) Sync = 500kHz sine input 13.5 20.5 (cid:181)s ) SW VFB = 1.2V, tON = 4.0(cid:181)s fo r IFB Feedback Source Current VFB = 0V 700 900 1100 (cid:181)A Q u D Minimum Duty Cycle V = 0V 0 % MIN FB a s VSTART UVLO Threshold Voltage 11 12 13 V i-R V After turn-on 7 8 9 V STOP e s tS/S Internal Soft-Start Time With free-running frequency 17.5 ms o n BURST-MODE SECTION a n V 0.45 0.55 0.65 V t BURH O VBURL Burst-Mode Voltages TJ = 25(cid:176)C, tPD = 200ns(10) 0.25 0.35 0.45 V p e Hysteresis 200 mV r a t Note: io 10. Propagation delay in the control IC. n Continued on the following page... ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 6

F S Electrical Characteristics (Continued) Q 0 7 TA = 25°C unless otherwise specified. 6 5 R Symbol Parameter Condition Min. Typ. Max. Unit Q PROTECTION SECTION (cid:151) ILIMIT Peak Current Limit TJ = 25(cid:176)C, di/dt = 460mA/(cid:181)s 3.08 3.50 3.92 A G V Shutdown Feedback Voltage V = 15V 5.5 6.0 6.5 V r SD CC e e IDELAY Shutdown Delay Current VFB = 5V 4 5 6 (cid:181)A n - t Leading-Edge Blanking Time(11) 250 ns M LEB o tOSP Threshold Time T = 25(cid:176)C 1.2 1.4 (cid:181)s d J e Output Short Threshold Feedback OSP triggered when t <t , V ON OSP 1.8 2.0 V F OSP Protection(11) Voltage V >V & lasts longer than a FB OSP r t i t Feedback Blanking Time OSP_FB 2.0 2.5 3.0 (cid:181)s c OSP_FB h TSD Thermal Shutdown Temperature 125 140 155 (cid:176)C ild Hys Shutdown(11) Hysteresis 60 P o SYNC SECTION w e VSH1 1.0 1.2 1.4 r Sync Threshold Voltage 1 VCC = 15V, VFB = 2V V S V 0.8 1.0 1.2 SL1 w tsync Sync Delay Time(11)(12) 230 ns itc h V 4.3 4.7 5.1 SH2 Sync Threshold Voltage 2 V = 15V, V = 2V V ( CC FB F V 4.0 4.4 4.8 SL2 P S I = 800(cid:181)A V Low Clamp Voltage SYNC_MAX 0.0 0.4 0.8 V (cid:153) CLAMP I = 50(cid:181)A SYNC_MIN ) VOVP Over-Voltage Threshold Voltage VCC = 15V, VFB=2V 7.4 8.0 8.6 V fo r tOVP Protection Blanking Time(11) 1.0 1.7 2.4 (cid:181)s Q u TOTAL DEVICE SECTION a s Operating Supply Current i I V = 13V, V =0V 1 3 5 mA - OP (Control Part Only) CC FB R e V = 10V s I Start Current CC 350 450 550 (cid:181)A o START (before VCC reaches VSTART) n a ICH Startup Charging Current VCC = 0V, VSTR = minimum 50V 0.65 0.85 1.00 mA n t V Minimum V Supply Voltage 26 V O STR STR p Notes: e r 11. Guaranteed by design, but not tested in production. a t 12. Includes gate turn-on time. io n ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 7

F S Comparison Between FSDM0x65RNB and FSQ-Series Q 0 7 6 5 Function FSDM0x65RE FSQ-Series FSQ-Series Advantages R Q ! Improved efficiency by valley switching Constant Quasi-Resonant Operation Method ! Reduced EMI noise (cid:151) Frequency PWM Operation ! Reduced components to detect valley point G r ! Valley switching e Frequency e EMI Reduction Reduce EMI Noise ! Inherent frequency modulation n Modulation ! Alternate valley switching -M o CCM or AVS d Hybrid Control Based on Load ! Improves efficiency by introducing hybrid control e and Input Condition F a Advanced ri Burst-Mode Burst-Mode c Burst-Mode ! Improved standby power by AVS in burst-mode h Operation Operation Operation il d OLP, OVP, ! Improved reliability through precise AOCP P Strong Protections OLP, OVP o AOCP, OSP ! Improved reliability through precise OSP w 145(cid:176)C without 140(cid:176)C with 60(cid:176)C ! Stable and reliable TSD operation e TSD r Hysteresis Hysteresis ! Converter temperature range S w i t c h ( F P S (cid:153) ) f o r Q u a s i - R e s o n a n t O p e r a t i o n ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 8

F S Typical Performance Characteristics Q 0 These characteristic graphs are normalized at T = 25(cid:176)C. 7 A 6 5 R Q ed 1.2 ed 1.2 (cid:151) z z ali 1.0 ali 1.0 G m m r r r e o 0.8 o 0.8 N N e n 0.6 0.6 -M o 0.4 0.4 d e 0.2 0.2 F a r 0.0 0.0 ic -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 h i Temperature [(cid:176)C] Temperature [(cid:176)C] ld P o Figure 4. Operating Supply Current (I ) vs. T Figure 5. UVLO Start Threshold Voltage OP A w (VSTART) vs. TA e r S w i t 1.2 1.2 c d h e d maliz 1.0 alize 1.0 (FP r m S No 0.8 or 0.8 (cid:153) N ) 0.6 0.6 f o r 0.4 0.4 Q u 0.2 0.2 a s i 0.0 0.0 -R -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 e Temperature [(cid:176)C] Temperature [(cid:176)C] s o n a Figure 6. UVLO Stop Threshold Voltage Figure 7. Startup Charging Current (ICH) vs. TA n (VSTOP) vs. TA t O p e r a d 1.2 1.2 ti e d o maliz 1.0 alize 1.0 n r m o 0.8 r 0.8 N o N 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature [(cid:176)C] Temperature [(cid:176)C] Figure 8. Initial Switching Frequency (f ) vs. T Figure 9. Maximum On Time (t ) vs. T SW A ON.MAX A ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 9

F S Typical Performance Characteristics (Continued) Q 0 These characteristic graphs are normalized at T = 25(cid:176)C. 7 A 6 5 R Q ed 1.2 d 1.2 (cid:151) z e mali 1.0 aliz 1.0 G r m re No 0.8 or 0.8 e N n 0.6 0.6 -M o 0.4 0.4 d e 0.2 0.2 F a r 0.0 0.0 ic -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 h i Temperature [(cid:176)C] Temperature [(cid:176)C] ld P o Figure 10. Blanking Time (t ) vs. T Figure 11. Feedback Source Current (I ) vs. T B A FB A w e r S w 1.2 1.2 ed d it z e c rmali 1.0 maliz 1.0 h (F No 0.8 or 0.8 P N S 0.6 0.6 (cid:153) ) 0.4 0.4 f o r 0.2 0.2 Q u 0.0 0.0 a s -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 i - Temperature [(cid:176)C] Temperature [(cid:176)C] R e s o Figure 12. Shutdown Delay Current (I ) vs. T Figure 13. Burst-Mode High Threshold Voltage DELAY A n (V ) vs. T a burh A n t O p e d 1.2 1.2 r e d a z e t mali 1.0 aliz 1.0 ion r m No 0.8 or 0.8 N 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature [(cid:176)C] Temperature [(cid:176)C] Figure 14. Burst-Mode Low Threshold Voltage Figure 15. Peak Current Limit (I ) vs. T LIM A (V ) vs. T burl A ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 10

F S Typical Performance Characteristics (Continued) Q 0 These characteristic graphs are normalized at T = 25(cid:176)C. 7 A 6 5 R Q ed 1.2 d 1.2 (cid:151) z e mali 1.0 aliz 1.0 G r m re No 0.8 or 0.8 e N n 0.6 0.6 -M o 0.4 0.4 d e 0.2 0.2 F a r 0.0 0.0 ic -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 h i Temperature [(cid:176)C] Temperature [(cid:176)C] ld P o Figure 16. Sync High Threshold Voltage 1 Figure 17. Sync Low Threshold Voltage 1 w (VSH1) vs. TA (VSL1) vs. TA e r S w i d 1.2 1.2 tc e d h z e ormali 01..80 rmaliz 01..80 (FPS N No (cid:153) 0.6 0.6 ) fo 0.4 0.4 r Q 0.2 0.2 u a s 0.0 0.0 i- R -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 e Temperature [(cid:176)C] Temperature [(cid:176)C] s o n Figure 18. Shutdown Feedback Voltage (V ) vs. T Figure 19. Over-Voltage Protection (V ) vs. T a SD A OV A n t O p e d 1.2 1.2 ra malize 1.0 alized 1.0 tion r m No 0.8 or 0.8 N 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature [(cid:176)C] Temperature [(cid:176)C] Figure 20. Sync High Threshold Voltage 2 Figure 21. Sync Low Threshold Voltage 2 (V ) vs. T (V ) vs. T SH2 A SL2 A ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 11

F S Functional Description 2.2 Leading-Edge Blanking (LEB): At the instant the Q internal SenseFET is turned on, a high-current spike 0 1. Startup: At startup, an internal high-voltage current 7 usually occurs through the SenseFET, caused by 6 source supplies the internal bias and charges the 5 external capacitor (C ) connected to the V pin, as primary-side capacitance and secondary-side rectifier R a CC reverse recovery. Excessive voltage across the R Q illustrated in Figure 22. When VCC reaches 12V, the resistor would lead to incorrect feedback operation inse tnhsee (cid:151) FPS(cid:153) begins switching and the internal high-voltage current-mode PWM control. To counter this effect, the current source is disabled. The FPS continues its normal G FPS employs a leading-edge blanking (LEB) circuit. This r switching operation and the power is supplied from the e circuit inhibits the PWM comparator for a short time e auxiliary transformer winding unless V goes below the CC (t ) after the SenseFET is turned on. n stop voltage of 8V. LEB -M o V VCC Vref de DC Idelay IFB F VO VFB 4 OSC SenseFET ar C FOD817A D1 D2 ic a CB 3R h + Gate il VFB* R driver d 3 VCC 6 Vstr KA431 - Po w OLP R e I V sense r CH SD S FSQ0765RRev. 00 w V ref i 8V/12V VCC good Figure 23. Pulse-Width-Modulation (PWM) Circuit tc h Internal (F Bias 3. Synchronization: The FSQ-series employs a quasi- P FSQ0765R Rev.00 S resonant switching technique to minimize the switching (cid:153) noise and loss. The basic waveforms of the quasi- Figure 22. Startup Circuit ) resonant converter are shown in Figure 24. To minimize f o the MOSFET’s switching loss, the MOSFET should be r 2. Feedback Control: FPS employs current-mode turned on when the drain voltage reaches its minimum Q control, as shown in Figure 23. An opto-coupler (such as value, which is indirectly detected by monitoring the V u CC a the FOD817A) and shunt regulator (such as the KA431) winding voltage, as shown in Figure 24. s i are typically used to implement the feedback network. - R Comparing the feedback voltage with the voltage across Vds e the R resistor makes it possible to control the s sense o switching duty cycle. When the reference pin voltage of VRO n a the shunt regulator exceeds the internal reference n voltage of 2.5V, the opto-coupler LED current increases, V VRO t DC O pulling down the feedback voltage and reducing the duty p cycle. This typically happens when the input voltage is e increased or the output load is decreased. Vsync tF ra t V (8V) i ovp o n 2.1 Pulse-by-Pulse Current Limit: Because current- mode control is employed, the peak current through the 1.2V SenseFET is limited by the inverting input of PWM 1.0V comparator (V *), as shown in Figure 23. Assuming FB 230ns Delay that the 0.9mA current source flows only through the MOSFET Gate internal resistor (3R + R = 2.8k), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (V ) exceeds 2.5V, the maximum FB ON ON voltage of the cathode of D2 is clamped at this voltage, clamping VFB*. Therefore, the peak value of the current FSQ0765R Rev.00 through the SenseFET is limited. Figure 24. Quasi-Resonant Switching Waveforms ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 12

F S The switching frequency is the combination of blank time Q (t ) and detection time window (t ). In case of a heavy tB=15μs tX 0 B W 7 load, the sync voltage remains flat after t and waits for 6 B 5 valley detection during t . This leads to a low switching R W Q frequency not suitable for heavy loads. To correct this I I DS DS (cid:151) drawback, additional timing is used. The timing conditions are described in Figures 25, 26, and 27. When G the V remains flat higher than 4.4V at the end of t r sync B V e that is t , the next switching cycle starts after internal DS e X n delay time from t . In the second case, the next switching - X M ingnore occurs on the valley when the Vsync goes below 4.4V o 4.4V d within tB. Once Vsync detects the first valley within tB, the V e other switching cycle follows classical QRC operation. sync 1.2V F 1.0V a r i c tB=15μs tX internal delay FSQ0765R Rev. 00 hil d Figure 27. After V Finds First Valley sync P o w I I 4. Protection Circuits: The FSQ-series has several e DS DS r self-protective functions, such as Overload Protection S (OLP), Abnormal Over-Current Protection (AOCP), w Over-Voltage Protection (OVP), and Thermal Shutdown i V t DS c (TSD). All the protections are implemented as auto- h restart mode. Once the fault condition is detected, ( F switching is terminated and the SenseFET remains off. P 4.4V This causes VCC to fall. When VCC falls down to the S (cid:153) V Under-Voltage Lockout (UVLO) stop voltage of 8V, the sync 1.2V ) 1.0V protection is reset and the startup circuit charges the f o V capacitor. When the V reaches the start voltage CC CC r internal delay FSQ0765R Rev. 00 of 12V, normal operation resumes. If the fault condition is Q not removed, the SenseFET remains off and V drops u CC a Figure 25. Vsync > 4.4V at tX to stop voltage again. In this manner, the auto-restart can s i alternately enable and disable the switching of the power -R SenseFET until the fault condition is eliminated. e tB=15μs tX Because these protection circuits are fully integrated into so the IC without external components, the reliability is n a improved without increasing cost. n t IDS IDS VDS Poowner oFcacuulrts reFmaouvlted Op e r a t i o V n DS V CC 4.4V 12V V sync 1.2V 8V 1.0V internal delay FSQ0765R Rev. 00 Normal Fault Normal t FSQ0765R Rev. 00 operation situation operation Figure 26. V < 4.4V at t sync X Figure 28. Auto Restart Protection Waveforms ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 13

F S 4.1 Overload Protection (OLP): Overload is defined as Q the load current exceeding its normal level due to an 0 7 unexpected abnormal event. In this situation, the 3R 6 OSC 5 protection circuit should trigger to protect the SMPS. PWM S Q R However, even when the SMPS is in the normal LEB Gate Q operation, the overload protection circuit can be 250ns R Q driver (cid:151) R triggered during the load transition. To avoid this G undesired operation, the overload protection circuit is R r designed to trigger only after a specified time to + sense 2 e AOCP GND e determine whether it is a transient situation or a true - V n overload situation. Because of the pulse-by-pulse FSQ0765R Rev.00 OCP -M current limit capability, the maximum peak current o Figure 30. Abnormal Over-Current Protection d through the SenseFET is limited, and therefore the e maximum input power is restricted with a given input F voltage. If the output consumes more than this maximum a 4.3 Output-Short Protection (OSP): If the output is r power, the output voltage (VO) decreases below the set shorted, steep current with extremely high di/dt can flow ic h voltage. This reduces the current through the opto- through the SenseFET during the LEB time. Such a i l coupler LED, which also reduces the opto-coupler steep current brings high voltage stress on the drain of d transistor current, thus increasing the feedback voltage SenseFET when turned off. To protect the device from P o (VFB). If VFB exceeds 2.5V, D1 is blocked and the 5(cid:181)A such an abnormal condition, OSP is included in the FSQ- w current source starts to charge CB slowly up to VCC. In series. It is comprised of detecting VFB and SenseFET er this condition, VFB continues increasing until it reaches turn-on time. When the VFB is higher than 2V and the S 6V, when the switching operation is terminated, as SenseFET turn-on time is lower than 1.2(cid:181)s, the FPS w i shown in Figure 29. The delay time for shutdown is the recognizes this condition as an abnormal error and shuts tc time required to charge CFB from 2.5V to 6V with 5(cid:181)A. A down PWM switching until VCC reaches Vstart again. An h ( 20 ~ 50ms delay time is typical for most applications. abnormal condition output short is shown in Figure 31. F P VFB FSQ0765R Rev.00 MDOrSaFinET DioRdeec Ctifuirerrent Turn-off delay S(cid:153) Overload protection Current ILIM ) f 6.0V V o FB r Q u 0 Minimum turn-on time a 2.5V V D s o 1.2us i - R t = C *(6.0-2.5)/I output short occurs 12 FB delay e 0 s t t t o 1 2 I n o a n Figure 29. Overload Protection FSQ0765R Rev. 00 0 t O p Figure 31. Output Short Waveforms e 4.2 Abnormal Over-Current Protection (AOCP): When r the secondary rectifier diodes or the transformer pins are a t i shorted, a steep current with extremely high di/dt can 4.4 Over-Voltage Protection (OVP): If the secondary- o n flow through the SenseFET during the LEB time. Even side feedback circuit malfunctions or a solder defect though the FSQ-series has overload protection, it is not causes an opening in the feedback path, the current enough to protect the FSQ-series in that abnormal case, through the opto-coupler transistor becomes almost since severe current stress is imposed on the SenseFET zero. Then, V climbs up in a similar manner to the FB until OLP triggers. The FSQ-series has an internal overload situation, forcing the preset maximum current AOCP circuit shown in Figure 30. When the gate turn-on to be supplied to the SMPS until the overload protection signal is applied to the power SenseFET, the AOCP triggers. Because more energy than required is provided block is enabled and monitors the current through the to the output, the output voltage may exceed the rated sensing resistor. The voltage across the resistor is voltage before the overload protection triggers, resulting compared with a preset AOCP level. If the sensing in the breakdown of the devices in the secondary side. resistor voltage is greater than the AOCP level, the set To prevent this situation, an OVP circuit is employed. In signal is applied to the latch, resulting in the shutdown of general, the peak voltage of the sync signal is the SMPS. proportional to the output voltage and the FSQ-series ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 14

F S uses a sync signal instead of directly monitoring the 6. Burst Operation: To minimize power dissipation in Q output voltage. If the sync signal exceeds 8V, an OVP is standby mode, the FPS enters burst-mode operation. As 0 7 triggered, shutting down the SMPS. To avoid undesired the load decreases, the feedback voltage decreases. As 6 5 triggering of OVP during normal operation, there are two shown in Figure 33, the device automatically enters R points to be considered, which are depicted in Figure 32. burst-mode when the feedback voltage drops below Q One is at the peak voltage of the sync signal should be VBURL (350mV). At this point, switching stops and the (cid:151) designed below 6V and the other is that the spike of the output voltages start to drop at a rate dependent on G sync pin should be as low as possible; not to get longer standby current load. This causes the feedback voltage r than tOVP by decreasing the leakage inductance shown to rise. Once it passes VBURH (550mV), switching ee at VCC winding coil. resumes. The feedback voltage then falls and the n- process repeats. Burst-mode operation alternately M VVcc_coil &VCC FSQ0765R Rev.00 enables and disables switching of the power SenseFET, o d Absolue max V (20V) thereby reducing switching loss in standby mode. e CC V V F CC Vcc_coil V a O r VOset ic h i l d V P N FB o VDC Npri w Vcc 0.55V e r Improper OVP triggering 0.35V S V sync w VOVP(8V) I it DS c tOVP VSH2(4.8V) tOVP h (F P S (cid:153) V CLAMP VDS ) f o Figure 32. OVP Triggering r Q u time a s 4S.e5n sTehFeErmT aaln dS hthuetd coownntr owl IiCth aHrey sbtueilrte isni so n(eT SpDac):k aTghee. FSQ0765R Rev.00 t1 Sdwisiatcbhleindg t2 t3 Sdwisiatcbhleindg t4 i-Re s This allows the control IC to detect abnormally high Figure 33. Waveforms of Burst Operation o temperature of the SenseFET. If the temperature n 7. Switching Frequency Limit: To minimize switching a exceeds approximately 140(cid:176)C, the thermal shutdown n loss and Electromagnetic Interference (EMI), the t triggers IC shutdown. The IC recovers its operation when O MOSFET turns on when the drain voltage reaches its the junction temperature decreases 60(cid:176)C from TSD p temperature and V reaches startup voltage (V ). minimum value in quasi-resonant operation. However, e CC start this causes switching frequency to increases at light load ra conditions. As the load decreases or input voltage ti o 5. Soft-Start: The FPS has an internal soft-start circuit increases, the peak drain current diminishes and the n switching frequency increases. This results in severe that increases PWM comparator inverting input voltage switching losses at light-load condition, as well as with the SenseFET current slowly after it starts up. The intermittent switching and audible noise. These problems typical soft-start time is 17.5ms. The pulse width to the create limitations for the quasi-resonant converter power switching device is progressively increased to topology in a wide range of applications. establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output To overcome these problems, FSQ-series employs a capacitors is progressively increased with the intention of frequency-limit function, as shown in Figures 34 and 35. smoothly establishing the required output voltage. This Once the SenseFET is turned on, the next turn-on is mode helps prevent transformer saturation and reduces prohibited during the blanking time (t ). After the B stress on the secondary diode during startup. blanking time, the controller finds the valley within the detection time window (t ) and turns on the MOSFET, as W shown in Figures 34 and Figure 35 (Cases A, B, and C). ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 15

F S If no valley is found during t , the internal SenseFET is 8. AVS (Alternating Valley Switching): Due to the Q W forced to turn on at the end of tW (Case D). Therefore, quasi-resonant operation with limited frequency, the 07 switching frequency varies depending on input voltage, 6 the devices have a minimum switching frequency of 5 48kHz and a maximum switching frequency of 67kHz. load transition, and so on. At high input voltage, the R switching on time is relatively small compared to low Q tmax=21μs input voltage. The input voltage variance is small and the (cid:151) IDS s IDS simwpitrcohvineg t fhree qEueMnIc yp emrfoodrmulaatniocne ,w AidVthS biesc oemnaebsl esdm awllh. eTon G r input voltage is high and the switching on time is small. e e A n t =15μs Internally, quasi-resonant operation is divided into two - B M categories; one is first-valley switching and the other is o ts second-valley switching after blanking time. In AVS, two d successive occurrences of first-valley switching and the e IDS IDS other two successive occurrences of second-valley Fa switching is alternatively selected to maximize frequency r i modulation. As depicted in Figure 35, the switching c B h frequency hops when the input voltage is high. The i l t =15μs internal timing diagram of AVS is described in Figure 36. d B P o ts f w s Assume the resonant period is 2us 1 e 15μs r 67kHz 1 S 59kHz 17μs w I I DS DS 53kHz 1 it 48kHz c 19μs h C AVS trigger point ( F Constant 1 tB=15μs frequency Variable frequency within limited range 21μs PS CCM DCM (cid:153) t AVS region s ) f o r D C B A Q I I DS DS u V a in FSQ0765R Rev.00 s i - D R tB=15μs t =6μs Figure 35. Switching Frequency Range e W s o n tmax=21μs FSQ0765R Rev. 00 a s n t Figure 34. QRC Operation with Limited Frequency O p e r a t Vgate io n S GateX2 ynchronize Synchronize Vga t e c o 1nstitn vuaeldle 2y pswulistcehsing V g a te c o n t i n 2unedd vaanloletyh esrw 2it cphuilnsge s 1st valley swVitcgahteincgo ntinued 2 pulses One-shot fixed fixed fixed fixed fixed fixed AVS triggering 1st or 2nd is depend on GateX2 de-triggering triggering 1st or 2nd is dependent on GateX2 VDS tB tB tB tB tB tB GateX2: Counting Vgate every 2 pulses independent on other signals. 1st valley- 2nd valley frequency modulation. Modulation frequency is approximately 17kHz. FSQ0765R Rev. 00 Figure 36. Alternating Valley Switching (AVS) ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 16

F S PCB Layout Guide Q 0 Due to the combined scheme, FPS shows better noise 7 6 immunity than conventional PWM controller and 5 MOSFET discrete solution. Further more are internal R Q drain current sense eliminates the possibility of noise (cid:151) generation caused by a sensing resistor. There are some recommendations for PCB layout to enhance noise G immunity and suppress natural noise inevitable in power- r e handling components. e n There are typically two grounds in the conventional -M SMPS: power ground and signal ground. The power o ground is the ground for primary input voltage and d e power, while the signal ground is ground for PWM F controller. In FPS, those two grounds share the same a r pin, GND. Normally the separate grounds do not share i c the same trace and meet only at one point, the GND pin. h i More, wider patterns for both grounds are good for large ld currents by decreasing resistance. P o Capacitors at the VCC and FB pins should be as close w as possible to the corresponding pins to avoid noise from e r the switching device. Sometimes Mylarfi or ceramic S capacitors with electrolytic for V are better for smooth w CC i operation. The ground of these capacitors needs to t c connect to the signal ground (not power ground). Figure 37. Recommended PCB Layout h ( The cathode of the snubber diode should be close to the F P drain pin to minimize stray inductance. The Y-capacitor S between primary and secondary should be directly (cid:153) connected to the power ground of DC link to maximize ) surge immunity. fo r Because the voltage range of feedback and sync line is Q small, it is affected by the noise of the drain pin. Those u a traces should not draw across or close to the drain line. s i - When the heat sink is connected to the ground, it should R be connected to the power ground. If possible, avoid e s using jumper wires for power ground and drain. o n a n t O p e r a t i o n Mylarfi is a registered trademark of DuPont Teijin Films. ' 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FSQ0765RQ Rev. 1.0.1 17

2.74 2.34 10.36 (0.70) B A 9.96 6.88 C 5.18 6.48 4.98 3.40 3.20 3.28 Ø 3.08 16.08 15.68 (17.83) (21.01) (1.13) R1.00 1.30 0.85 5PLCS #2,4,6 1.05 0.75 0.65 R1.00 6PLCS 0.55 #1 #6 #1,3,5 4.90 6PLCS 4.70 0.61 2.19 1.75 3.18 0.46 0.05 C 1.27 0.20 A B 3.81 5° 5° NOTES: A) NO PACKAGE STANDARD APPLIES. B) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. C) DIMENSIONS ARE IN MILLIMETERS. D) DRAWING FILENAME : MKT-TO220E06REV2 4.80 4.40 APPROVALS DATE DRAWN: J.U. COMPARATIVO JR. 03MAR2010 CHECKED: L. STA CRUZ APPROVED: 6LD,TO220,FULLPACK M.R. GESTOLE L-FORMING C.N. TANGPUZ SCALE SIZE DRAWING NUMBER REV 1:1 N/A MKT-T0220E06 2 [MM] FORMERLY: N/A SHEET : 1 OF1

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