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F S G M 0 March 2010 5 6 5 R B FSGM0565RB — G Green-Mode Fairchild Power Switch (FPS™) r e e n - M Features Description o d (cid:131) Soft Burst-Mode Operation for Low Standby Power The FSGM0565RB is an integrated Pulse Width e Consumption and Low Noise Modulation (PWM) controller and SenseFET specifically Fa designed for offline Switch-Mode Power Supplies i (cid:131) Precision Fixed Operating Frequency: 66kHz (SMPS) with minimal external components. The PWM rc h (cid:131) Pulse-by-Pulse Current Limit controller includes an integrated fixed-frequency i l oscillator, Under-Voltage Lockout (UVLO), Leading- d (cid:131) Various Protection Functions: Overload Protection Edge Blanking (LEB), optimized gate driver, internal P (OLP), Over-Voltage Protection (OVP), Abnormal soft-start, temperature-compensated precise current o w Over-Current Protection (AOCP), Internal Thermal sources for loop compensation, and self-protection e Shutdown (TSD) with Hysteresis, Output-Short circuitry. Compared with a discrete MOSFET and PWM r Protection (OSP), and Under-Voltage Lockout controller solution, the FSGM series can reduce total S (UVLO) with Hysteresis cost, component count, size, and weight; while w i (cid:131) Auto-Restart Mode simultaneously increasing efficiency, productivity, and tc system reliability. This device provides a basic platform h (cid:131) Internal Startup Circuit suited for cost-effective design of a flyback converter. ( F (cid:131) Internal High-Voltage SenseFET: 650V P S (cid:131) Built-in Soft-Start: 15ms ™ ) Applications (cid:131) Power Supply for LCD TV and Monitor, STB and DVD Combination Ordering Information Output Power Table(2) Operating Part Number Package Junction Current RDS(ON) 230VAC ± 15%(3) 85-265VAC Replaces Limit (Max.) Open Open Device Temperature Adapter(4) Adapter(4) Frame(5) Frame(5) TO-220F 6-Lead(1) -40°C ~ FSGM0565RBWDTU 3.00A 2.2Ω 70W 80W 41W 60W FSDM0565RE W- +125°C Forming TO-220F FSGM0565RBUDTU 6-Lead(1) -40°C ~ 3.00A 2.2Ω 70W 80W 41W 60W FSDM0565RE +125°C U-Forming TO-220F FSGM0565RBLDTU 6-Lead(1) -40°C ~ 3.00A 2.2Ω 70W 80W 41W 60W FSDM0565RE +125°C L-Forming Notes: 1. Pb-free package per JEDEC J-STD-020B. 2. The junction temperature can limit the maximum output power. 3. 230V or 100/115V with voltage doubler. AC AC 4. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature. 5. Maximum practical continuous power in an open-frame design at 50°C ambient temperature. © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0

F Application Circuit S G M 0 5 6 5 R B — G r e e n - M o d e F a i r c h i l d P o w e Figure 1. Typical Application Circuit r S Internal Block Diagram w i t c h ( F P S ™ ) Figure 2. Internal Block Diagram © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 2

F Pin Configuration S G M 0 5 6 6. VSTR 5 R 5. N.C. B 4. FB — 3. V G CC r 2. GND e e n - 1. Drain M o d FSGM0565RB e Figure 3. Pin Configuration (Top View) F a i r c h i ld P o Pin Definitions w e Pin # Name Description r S 1 Drain SenseFET Drain. High-voltage power SenseFET drain connection. w i t 2 GND Ground. This pin is the control ground and the SenseFET source. c h Power Supply. This pin is the positive supply input, which provides the internal operating (F 3 V CC current for both startup and steady-state operation. P S ™ Feedback. This pin is internally connected to the inverting input of the PWM comparator. 4 FB The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor ) should be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload protection triggers, which shuts down the FPS. 5 N.C. No Connection. Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At startup, the internal high-voltage current source supplies internal bias and charges the 6 V STR external capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source (I ) is disabled. CH © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 3

F Absolute Maximum Ratings S G Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be M operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 0 In addition, extended exposure to stresses above the recommended operating conditions may affect device 5 6 reliability. The absolute maximum ratings are stress ratings only. 5 R B Symbol Parameter Min. Max. Unit — VSTR VSTR Pin Voltage 650 V G VDS Drain Pin Voltage 650 V re e VCC VCC Pin Voltage 26 V n- M V Feedback Pin Voltage -0.3 12.0 V FB o d IDM Drain Current Pulsed 11 A e F IDS Continuous Switching Drain Current(6) TTCC==21500°C°C 53..64 AA airc h EAS Single Pulsed Avalanche Energy(7) 295 mJ il d PD Total Power Dissipation (TC=25°C)(8) 45 W P o Maximum Junction Temperature 150 °C w TJ Operating Junction Temperature(9) -40 +125 °C er S TSTG Storage Temperature -55 +150 °C w i VISO Minimum Isolation Voltage(10) 2.5 kV tc h Electrostatic Human Body Model, JESD22-A114 2 (F ESD kV Discharge Capability P Charged Device Model, JESD22-C101 2 S ™ Notes: 6. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX=0.75) ) and junction temperature (see Figure 4). 7. L=45mH, starting T=25°C. J 8. Infinite cooling condition (refer to the SEMI G30-88). 9. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics. 10. The voltage between the package back side and the lead is guaranteed. I DS D MAX f SW Figure 4. Repetitive Peak Switching Current Thermal Impedance T =25°C unless otherwise specified. A Symbol Parameter Value Unit θ Junction-to-Ambient Thermal Impedance(11) 62.5 °C/W JA θ Junction-to-Case Thermal Impedance(12) 3 °C/W JC Notes: 11. Infinite cooling condition (refer to the SEMI G30-88). 12. Free standing with no heat-sink under natural convection. © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 4

F Electrical Characteristics S G TJ = 25°C unless otherwise specified. M 0 Symbol Parameter Conditions Min. Typ. Max. Unit 5 6 5 SenseFET Section R B BVDSS Drain-Source Breakdown Voltage VCC = 0V, ID = 250μA 650 V — IDSS Zero-Gate-Voltage Drain Current VDS = 520V, TA = 125°C 250 μA G Drain-Source On-State re R V = 10V, I =1A 1.8 2.2 Ω DS(ON) Resistance GS D e n C Input Capacitance(13) V = 25V, V = 0V, f=1MHz 515 pF -M ISS DS GS o C Output Capacitance(13) V = 25V, V = 0V, f=1MHz 75 pF d OSS DS GS e tr Rise Time VDS = 325V, ID = 4A, RG=25Ω 26 ns F a tf Fall Time VDS = 325V, ID = 4A, RG=25Ω 25 ns irc h t Turn-On Delay Time V = 325V, I = 4A, R =25Ω 14 ns d(on) DS D G i l d td(off) Turn-Off Delay Time VDS = 325V, ID = 4A, RG=25Ω 32 ns P o Control Section w e fS Switching Frequency VCC = 14V, VFB = 4V 60 66 72 kHz r S ΔfS Switching Frequency Variation(13) -25°C < TJ < 125°C ±5 ±10 % w i t DMAX Maximum Duty Ratio VCC = 14V, VFB = 4V 65 70 75 % ch DMIN Minimum Duty Ratio VCC = 14V, VFB = 0V 0 % (F P IFB Feedback Source Current VFB = 0 160 210 260 μA S ™ V V = 0V, V Sweep 11 12 13 V START UVLO Threshold Voltage FB CC ) V After Turn-on, V = 0V 7.0 7.5 8.0 V STOP FB V V Operating Range 13 23 V OP CC t Internal Soft-Start Time V = 40V, V Sweep 15 ms S/S STR CC Burst-Mode Section V 0.5 0.6 0.7 V BURH V Burst-Mode Voltage V = 14V, V Sweep 0.3 0.4 0.5 V BURL CC FB Hys 200 mV Protection Section ILIM Peak Drain Current Limit di/dt = 300mA/μs 2.75 3.00 3.25 A V Shutdown Feedback Voltage V = 14V,V Sweep 5.5 6.0 6.5 V SD CC FB IDELAY Shutdown Delay Current VCC = 14V, VFB = 4V 2.5 3.3 4.1 μA t Leading-Edge Blanking Time(13)(14) 300 ns LEB V Over-Voltage Protection V Sweep 23.0 24.5 26.0 V OVP CC tOSP Threshold Time 1.0 1.2 1.4 μs OSP Triggered when V Output Short Threshold V 1.8 2.0 2.2 V OSP Protection(13) FB tON<tOSP & VFB>VOSP tOSP_FB VTiFmB eB lanking (Lasts Longer than tOSP_FB) 2.0 2.5 3.0 μs TSD Thermal Shutdown Shutdown Temperature 130 140 150 °C Temperature(13) Hys Hysteresis 30 °C Continued on the following page… © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 5

F Electrical Characteristics (Continued) S G TJ = 25°C unless otherwise specified. M 0 5 Symbol Parameter Conditions Min. Typ. Max. Unit 6 5 Total Device Section R B I Operating Supply Current, V = 14V, V = 0V 1.2 1.6 2.0 mA — OP (Control Part in Burst Mode) CC FB G Operating Switching Current, r I V = 14V, V = 4V 2.0 2.5 3.0 mA e OPS (Control Part and SenseFET Part) CC FB e n V = 11V (Before V - I Start Current CC CC 0.5 0.6 0.7 mA M START Reaches V ) START o d ICH Startup Charging Current VCC = VFB = 0V, VSTR = 40V 1.00 1.15 1.30 mA e F V Minimum V Supply Voltage V = V = 0V, V Sweep 26 V STR STR CC FB STR a i Notes: rc 13. Although these parameters are guaranteed, they are not 100% tested in production. h i 14. tLEB includes gate turn-on time. ld P o w e r S Comparison of FSDM0565RE and FSGM0565RB w i t c Function FSDM0565RE FSGM0565RB Advantages of FSGM0565RB h ( Burst Mode Advanced Burst Advanced Soft Burst Low noise and low standby power F P S Enhanced SenseFET and controller against Lightning Surge Strong ™ lightning surge ) Soft-Start 10ms (Built-in) 15ms (Built-in) Longer soft-start time OLP OLP OVP Protections OVP OSP Enhanced protections and high reliability TSD AOCP TSD with Hysteresis The difference of input power between the low Power Balance Long T Very Short T CLD CLD and high input voltage is quite small © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 6

F Typical Performance Characteristics S G Characteristic graphs are normalized at TA=25°C. M 0 5 6 1.20 1.20 5 R 1.15 1.15 B 1.10 1.10 — Normalized 011...900505 Normalized 011...900505 Gree n 0.90 0.90 -M 0.85 0.85 o d 0.80 0.80 e -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ F Temperature [°C] Temperature [°C] a i r c Figure 5. Operating Supply Current (IOP) vs. TA Figure 6. Operating Switching Current (IOPS) vs. TA h i l d P o w 1.40 1.20 e r 1.30 1.15 S 1.20 1.10 w zed 1.10 zed 1.05 itc mali 1.00 mali 1.00 h Nor 0.90 Nor 0.95 (F P 0.80 0.90 S ™ 0.70 0.85 ) 0.60 0.80 -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ Temperature [°C] Temperature [°C] Figure 7. Startup Charging Current (I ) vs. T Figure 8. Peak Drain Current Limit (I ) vs. T CH A LIM A 1.20 1.20 1.15 1.15 1.10 1.10 malized 11..0005 malized 11..0005 Nor 0.95 Nor 0.95 0.90 0.90 0.85 0.85 0.80 0.80 -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ Temperature [°C] Temperature [°C] Figure 9. Feedback Source Current (I ) vs. T Figure 10. Shutdown Delay Current (I ) vs. T FB A DELAY A © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 7

F Typical Performance Characteristics S G Characteristic graphs are normalized at TA=25°C. M 0 5 6 5 R 1.20 1.20 B 1.15 1.15 — 1.10 1.10 G d d e 1.05 e 1.05 r maliz 1.00 maliz 1.00 ee Nor 0.95 Nor 0.95 n-M 0.90 0.90 o d 0.85 0.85 e 0.80 0.80 F a -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ i r Temperature [°C] Temperature [°C] c h i Figure 11. UVLO Threshold Voltage (VSTART) vs. TA Figure 12. UVLO Threshold Voltage (VSTOP) vs. TA ld P o w e r 1.20 1.20 S 1.15 1.15 w i 1.10 1.10 tc d d h malize 11..0005 malize 11..0005 (FP Nor 0.95 Nor 0.95 S ™ 0.90 0.90 ) 0.85 0.85 0.80 0.80 -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ Temperature [°C] Temperature [°C] Figure 13. Shutdown Feedback Voltage (V ) vs. T Figure 14. Over-Voltage Protection (V ) vs. T SD A OVP A 1.20 1.20 1.15 1.15 1.10 1.10 d d e 1.05 e 1.05 z z mali 1.00 mali 1.00 Nor 0.95 Nor 0.95 0.90 0.90 0.85 0.85 0.80 0.80 -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ -40℃ -25℃ 0℃ 25℃ 50℃ 75℃ 100℃ 125℃ Temperature [°C] Temperature [°C] Figure 15. Switching Frequency (f ) vs. T Figure 16. Maximim Duty Ratio (D ) vs. T S A MAX A © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 8

F Functional Description S G 1. Startup: At startup, an internal high-voltage current 3. Feedback Control: This device employs current- M source supplies the internal bias and charges the mode control, as shown in Figure 18. An opto-coupler 0 5 external capacitor (C ) connected to the V pin, as (such as the FOD817) and shunt regulator (such as the Vcc CC 6 illustrated in Figure 17. When V reaches 12V, the KA431) are typically used to implement the feedback 5 CC R FSGM0565RB begins switching and the internal high- network. Comparing the feedback voltage with the B voltage current source is disabled. The FSGM0565RB voltage across the R resistor makes it possible to SENSE — continues normal switching operation and the power is control the switching duty cycle. When the reference pin supplied from the auxiliary transformer winding unless voltage of the shunt regulator exceeds the internal G VCC goes below the stop voltage of 7.5V. reference voltage of 2.5V, the opto-coupler LED current re increases, pulling down the feedback voltage and e reducing drain current. This typically occurs when the n - input voltage is increased or the output load is decreased. M o d 3.1 Pulse-by-Pulse Current Limit: Because current- e mode control is employed, the peak current through F the SenseFET is limited by the inverting input of PWM a comparator (VFB*), as shown in Figure 18. Assuming irc that the 210μA current source flows only through the h internal resistor (3R + R =11.6kΩ), the cathode il d voltage of diode D2 is about 2.4V. Since D1 is P blocked when the feedback voltage (V ) exceeds FB o 2.4V, the maximum voltage of the cathode of D2 is w clamped at this voltage. Therefore, the peak value of e r the current through the SenseFET is limited. S w 3.2 Leading-Edge Blanking (LEB): At the instant the i t internal SenseFET is turned on, a high-current spike c Figure 17. Startup Block h usually occurs through the SenseFET, caused by ( primary-side capacitance and secondary-side rectifier F 2. Soft-Start: The FSGM0565RB has an internal soft- reverse recovery. Excessive voltage across the P S start circuit that increases PWM comparator inverting RSENSE resistor leads to incorrect feedback operation ™ input voltage, together with the SenseFET current, in the current mode PWM control. To counter this ) slowly after it starts. The typical soft-start time is 15ms. effect, the FSGM0565RB employs a leading-edge The pulse width to the power switching device is blanking (LEB) circuit. This circuit inhibits the PWM progressively increased to establish the correct working comparator for t (300ns) after the SenseFET is LEB conditions for transformers, inductors, and capacitors. turned on. The voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. This helps prevent transformer saturation and reduces stress on the secondary diode during startup. Figure 18. Pulse Width Modulation Circuit © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 9

F S 4. Protection Circuits: The FSGM0565RB has several increasing until it reaches 6.0V, when the switching G self-protective functions, such as Overload Protection operation is terminated, as shown in Figure 20. The M (OLP), Abnormal Over-Current Protection (AOCP), delay time for shutdown is the time required to charge 0 5 Output-Short Protection (OSP), Over-Voltage Protection CFB from 2.4V to 6.0V with 3.3µA. A 25 ~ 50ms delay 6 (OVP), and Thermal Shutdown (TSD). All the is typical for most applications. This protection is 5 R protections are implemented as auto-restart. Once the implemented in auto-restart mode. B fault condition is detected, switching is terminated and — the SenseFET remains off. This causes V to fall. CC When VBCCB falls to the Under-Voltage Lockout (UVLO) G stop voltage of 7.5V, the protection is reset and the r e startup circuit charges the VCC capacitor. When VCC e reaches the start voltage of 12.0V, the FSGM0565RB n - resumes normal operation. If the fault condition is not M removed, the SenseFET remains off and V drops to o CC d stop voltage again. In this manner, the auto-restart can e alternately enable and disable the switching of the F power SenseFET until the fault condition is eliminated. a i Because these protection circuits are fully integrated r c into the IC without external components, the reliability is h improved without increasing cost. ild P Figure 20. Overload Protection o w 4.2 Abnormal Over-Current Protection (AOCP): e r When the secondary rectifier diodes or the S transformer pins are shorted, a steep current with w extremely high di/dt can flow through the SenseFET i t during the minimum turn-on time. Even though the c h FSGM0565RB has overload protection, it is not ( enough to protect the FSGM0565RB in that abnormal F P case; since severe current stress is imposed on the S SenseFET until OLP is triggered. The FSGM0565RB ™ internal AOCP circuit is shown in Figure 21. When ) the gate turn-on signal is applied to the power SenseFET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the S-R latch, resulting in the shutdown of the SMPS. Figure 19. Auto-Restart Protection Waveforms 4.1 Overload Protection (OLP): Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in normal operation, the overload protection circuit can be triggered during the load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the SenseFET is limited and, therefore, the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (V ) decreases OUT Figure 21. Abnormal Over-Current Protection below the set voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (V ). If V exceeds 2.4V, D1 is FB FB blocked and the 3.3µA current source starts to charge C slowly up In this condition, V continues FB . FB © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 10

F 4.3. Output-Short Protection (OSP): If the output is 4.5 Thermal Shutdown (TSD): The SenseFET and S shorted, steep current with extremely high di/dt can the control IC on a die in one package makes it G M flow through the SenseFET during the minimum turn- easier for the control IC to detect the over 0 on time. Such a steep current brings high-voltage temperature of the SenseFET. If the temperature 5 stress on the drain of the SenseFET when turned off. exceeds ~140°C, the thermal shutdown is triggered 6 5 To protect the device from this abnormal condition, and the FSGM0565RB stops operation. The R OSP is included. It is comprised of detecting VFB and FSGM0565RB operates in auto-restart mode until the B SenseFET turn-on time. When the VFB is higher than temperature decreases to around 110°C, when — 2V and the SenseFET turn-on time is lower than normal operation resumes. 1.2μs, the FSGM0565RB recognizes this condition as G r an abnormal error and shuts down PWM switching 5. Soft Burst-Mode Operation: To minimize power e until VCC reaches VSTART again. An abnormal dissipation in standby mode, the FSGM0565RB enters en condition output short is shown in Figure 22. burst-mode operation. As the load decreases, the - M feedback voltage decreases. As shown in Figure 23, o the device automatically enters burst mode when the d feedback voltage drops below V (400mV). At this e BURL point, switching stops and the output voltages start to F a drop at a rate dependent on standby current load. This i r causes the feedback voltage to rise. Once it passes c h V (600mV), switching resumes. At this point, the BURH i l drain current peak increases gradually. This soft burst- d mode can reduce audible noise during burst-mode P operation. The feedback voltage then falls and the o w process repeats. Burst-mode operation alternately e enables and disables switching of the SenseFET, r thereby reducing switching loss in standby mode. S w i V t O c h ( F P t S Figure 22. Output-Short Protection ™ V FB ) 4.4 Over-Voltage Protection (OVP): If the 0.60V secondary-side feedback circuit malfunctions or a 0.40V solder defect causes an opening in the feedback t path, the current through the opto-coupler transistor IDS becomes almost zero. Then V climbs up in a similar Soft Burst FB manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is triggered. Because more t energy than required is provided to the output, the output voltage may exceed the rated voltage before V DS the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. In general, the V is proportional to the output voltage CC t and the FSGM0565RB uses V instead of directly CC monitoring the output voltage. If VCC exceeds 24.5V, Switching Switching an OVP circuit is triggered, resulting in the t1 disabled t2 t3 disabled t4 termination of the switching operation. To avoid Figure 23. Burst-Mode Operation undesired activation of OVP during normal operation, VCC should be designed to be below 24.5V. © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 11

F Typical Application Circuit S G M Application Input Voltage Rated Output Rated Power 0 5 LCD TV, Monitor 390V 5.0V(4A) 68W 65 Power Supply DC 12.0V(4A) R B — Key Design Notes: G 1. The delay time for overload protection is designed to be about 25ms with C105 (22nF). OLP time between 25ms r (22nF) and 50ms (43nF) is recommended. e e n 2. The SMD-type capacitor (C106) must be placed as close as possible to the VCC pin to avoid malfunction by -M abrupt pulsating noises and to improve ESD and surge immunity. Capacitance between 100nF and 220nF is o recommended. d e F 1. Schematic a i r c T101 D201 L201 h EER3019 MBR20150CT 5µH i 1 12 C201 C202 C203 C208 12V, 4A ld R103 C104 1000µF 1000µF 1000µF 100nF P R751k02 313Wk 36.330nVF 2 10,11 25V 25V 25V SMD ow D101 e 1C0100µ3F RGP15M 3 r 2 400V S GB3SDB1A0160 FSGM0565RB C301 w 1 3 6VSTR Drain1 4.Y72nF itc N5TDC-11011 4 54 NFBC VCC3 R06.1250W4 2CS21M00nD6F C45710µ0VF7 6 7,8F,Y9PDF2200026DN L52µ0H2 5V, 4A h (F 217C5510V0nA2FC C21201n00VF5 GND2 UFD 1400204 2C2102000Vµ4F 1C0102000Vµ5F 1C0102000Vµ6F 1CS02M00nD9F PS™ 5 10,11 ZD101 ) 1N4749A LF101 20mH R201 330 R101 R204 1.5M 8k 0.5W R202 R203 C207 1.2k 18k 47nF IC301 2C2100n1F FFU10S1E FOD817B KAIC423011LZ R205 275VAC 250V 8k 3.15A Figure 24. Schematic of Demonstration Board © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 12

F 2. Transformer S G M 0 5 6 5 R B — G r e e n - M o d e F Figure 25. Schematic of Transformer a i r 3. Winding Specification c h i l Barrier Tape d Pin (S → F) Wire Turns Winding Method P TOP BOT Ts o w N /2 3 → 2 0.33φ×1 22 Solenoid Winding 2.0mm 1 e p r S Insulation: Polyester Tape t = 0.025mm, 2 Layers w i N12V 12 → 9 0.4φ×3 (TIW) 4 Solenoid Winding 2.0mm 1 tc h Insulation: Polyester Tape t = 0.025mm, 2 Layers ( F P N5V 7 → 10 0.4φ×4 (TIW) 3 Solenoid Winding 2.0mm 1 S ™ Insulation : Polyester Tape t = 0.025mm, 2 Layers ) N 6 → 5 0.2φ×1 7 Solenoid Winding 4.0mm 4.0mm 1 a Insulation: Polyester Tape t = 0.025mm, 2 Layers N 8 → 11 0.4φ×4 (TIW) 3 Solenoid Winding 2.0mm 1 5V Insulation: Polyester Tape t = 0.025mm, 2 Layers N /2 2 → 1 0.33φ×1 21 Solenoid Winding 2.0mm 1 p Insulation: Polyester Tape t = 0.025mm, 2 Layers 4. Electrical Characteristics Pin Specification Remark Inductance 1－3 600μH ± 7% 67kHz, 1V Leakage 1－3 15μH Maximum Short All Other Pins 5. Core & Bobbin (cid:131) Core: EER3019 (Ae=134.0mm2) (cid:131) Bobbin: EER3019 © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 13

F 6. Bill of Materials S G Part # Value Note Part # Value Note M 0 Fuse Capacitor 5 6 5 F101 250V 3.15A C101 220nF/275V Box (Pilkor) R NTC C102 150nF/275V Box (Pilkor) B Electrolytic — NTC101 5D-11 DSC C103 100μF/400V (SamYoung) G Resistor C104 3.3nF/630V Film (Sehwa) r e e R101 1.5MΩ, J 0.5W C105 22nF/100V Film (Sehwa) n - R102 75kΩ, J 1/2W C106 220nF SMD (2012) M Electrolytic o R103 33kΩ, J 1W C107 47μF/50V d (SamYoung) e Electrolytic F R104 62Ω, J 1/2W C201 1000μF/25V (SamYoung) a i R201 330Ω, J 1/4W C202 1000μF/25V Electrolytic rc (SamYoung) h i Electrolytic l R202 1.2kΩ, F 1/4W, 1% C203 1000μF/25V d (SamYoung) P Electrolytic o R203 18kΩ, F 1/4W, 1% C204 2200μF/10V (SamYoung) w Electrolytic e R204 8kΩ, F 1/4W, 1% C205 1000μF/16V r (SamYoung) S Electrolytic w R205 8kΩ, F 1/4W, 1% C206 1000μF/16V (SamYoung) it c IC C207 47nF/100V Film (Sehwa) h FSGM0565RB FSGM0565RB Fairchild C208 100nF SMD (2012) (F Semiconductor P Fairchild S IC201 KA431LZ C209 100nF SMD (2012) ™ Semiconductor ) Fairchild IC301 FOD817B C301 4.7nF/Y2 Y-cap (Samhwa) Semiconductor Diode Inductor D101 RGP15M Vishay LF101 20mH Line filter 0.7Ø D102 UF4004 Vishay L201 5μH 5A Rating ZD101 1N4749 Vishay L202 5μH 5A Rating Fairchild D201 MBR20150CT Jumper Semiconductor Fairchild D202 FYPF2006DN J101 Semiconductor BD101 G3SBA60 Vishay Transformer T101 600μH © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FSGM0565RB • Rev. 1.0.0 14

2.74 2.34 10.36 (0.70) B A 9.96 6.88 C 5.18 6.48 4.98 3.40 3.20 3.28 Ø 3.08 16.08 15.68 (17.83) (21.01) (1.13) R1.00 1.30 0.85 5PLCS #2,4,6 1.05 0.75 0.65 R1.00 6PLCS 0.55 #1 #6 #1,3,5 4.90 6PLCS 4.70 0.61 2.19 1.75 3.18 0.46 0.05 C 1.27 0.20 A B 3.81 5° 5° NOTES: A) NO PACKAGE STANDARD APPLIES. B) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. C) DIMENSIONS ARE IN MILLIMETERS. D) DRAWING FILENAME : MKT-TO220E06REV2 4.80 4.40 APPROVALS DATE DRAWN: J.U. COMPARATIVO JR. 03MAR2010 CHECKED: L. STA CRUZ APPROVED: 6LD,TO220,FULLPACK M.R. GESTOLE L-FORMING C.N. TANGPUZ SCALE SIZE DRAWING NUMBER REV 1:1 N/A MKT-T0220E06 2 [MM] FORMERLY: N/A SHEET : 1 OF1

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