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F S B 5 0 8 April 2015 2 FSB50825AS 5 A S Motion SPM® 5 Series tm M o t i o Features Related Source n S • UL Certified No. E209204 (UL1557) • RD-FSB50450A - Reference Design for Motion SPM 5 P Series Ver.2 M • 250 V RDS(on) = 0.45 Max FRFET MOSFET 3- ® Phase Inverter with Gate Drivers and Protection • AN-9082 - Motion SPM5 Series Thermal Performance 5 • Built-in Bootstrap Diodes Simplify PCB Layout by Contact Pressure S e • AN-9080 - User’s Guide for Motion SPM 5 Series V2 r • Separate Open-Source Pins from Low-Side MOSFETs i e for Three-Phase Current-Sensing s General Description • Active-HIGH Interface, Works with 3.3 / 5 V Logic, The FSB50825AS is an advanced Motion SPM® 5 Schmitt-trigger Input module providing a fully-featured, high-performance • Optimized for Low Electromagnetic Interference inverter output stage for AC Induction, BLDC and PMSM motors. These modules integrate optimized gate drive of • HVIC Temperature-Sensing Built-in for Temperature the built-in MOSFETs(FRFET® technology) to minimize Monitoring EMI and losses, while also providing multiple on-module • HVIC for Gate Driving and Under-Voltage Protection protection features including under-voltage lockouts and • Isolation Rating: 1500 Vrms / 1 min. thermal monitoring. The built-in high-speed HVIC requires only a single supply voltage and • Moisture Sensitive Level (MSL) 3 translates the incoming logic-level gate inputs to the • RoHS Compliant high-voltage, high-current drive signals required to properly drive the module's internal MOSFETs. Applications Separate open-source MOSFET terminals are available for each phase to support the widest variety of control • 3-Phase Inverter Driver for Small Power AC Motor algorithms. Drives Package Marking & Ordering Information Device Marking Device Package Reel Size Packing Type Quantity FSB50825AS FSB50825AS SPM5Q-023 330mm Tape-Reel 450 ©2012 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S Absolute Maximum Ratings B 5 0 Inverter Part (each MOSFET unless otherwise specified.) 8 2 Symbol Parameter Conditions Rating Unit 5 A V Drain-Source Voltage of Each MOSFET 250 V S DSS *I Each MOSFET Drain Current, Continuous T = 25°C 3.6 A M D 25 C o *ID 80 Each MOSFET Drain Current, Continuous TC = 80°C 2.7 A ti o *IDP Each MOSFET Drain Current, Peak TC = 25°C, PW < 100 s 9.0 A n *I Each MOSFET Drain Current, Rms T = 80°C, F < 20 kHz 1.9 A S DRMS C PWM rms P *PD Maximum Power Dissipation TC = 25°C, For Each MOSFET 14.2 W M ® Control Part (each HVIC unless otherwise specified.) 5 S Symbol Parameter Conditions Rating Unit e r i V Control Supply Voltage Applied Between V and COM 20 V e CC CC s V High-side Bias Voltage Applied Between V and V 20 V BS B S V Input Signal Voltage Applied Between IN and COM -0.3 ~ V + 0.3 V IN CC Bootstrap Diode Part (each bootstrap diode unless otherwise specified.) Symbol Parameter Conditions Rating Unit VRRMB Maximum Repetitive Reverse Voltage 250 V * I Forward Current T = 25°C 0.5 A FB C * IFPB Forward Current (Peak) TC = 25°C, Under 1ms Pulse Width 1.5 A Thermal Resistance Symbol Parameter Conditions Rating Unit Each MOSFET under Inverter Oper- R Junction to Case Thermal Resistance 8.8 °C/W JC ating Condition (1st Note 1) Total System Symbol Parameter Conditions Rating Unit T Operating Junction Temperature -40 ~ 150 °C J T Storage Temperature -40 ~ 125 °C STG 60 Hz, Sinusoidal, 1 Minute, Con- V Isolation Voltage 1500 V ISO nect Pins to Heat Sink Plate rms 1st Notes: 1. For the measurement point of case temperature TC, please refer to Figure 4. 2. Marking “ * “ is calculation value or design factor. ©2012 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S Pin descriptions B 5 0 Pin Number Pin Name Pin Description 8 2 1 COM IC Common Supply Ground 5 A 2 V Bias Voltage for U-Phase High-Side MOSFET Driving S B(U) 3 VCC(U) Bias Voltage for U-Phase IC and Low-Side MOSFET Driving M o 4 IN Signal Input for U-Phase High-Side (UH) t i 5 IN Signal Input for U-Phase Low-Side o (UL) n 6 N.C No Connection S P 7 V Bias Voltage for V-Phase High Side MOSFET Driving B(V) M 8 V Bias Voltage for V-Phase IC and Low Side MOSFET Driving ® CC(V) 9 IN Signal Input for V-Phase High-Side 5 (VH) S 10 IN(VL) Signal Input for V-Phase Low-Side e r 11 VTS Output for HVIC Temperature Sensing ie s 12 VB(W) Bias Voltage for W-Phase High-Side MOSFET Driving 13 V Bias Voltage for W-Phase IC and Low-Side MOSFET Driving CC(W) 14 IN Signal Input for W-Phase High-Side (WH) 15 IN Signal Input for W-Phase Low-Side (WL) 16 N.C No Connection 17 P Positive DC-Link Input 18 U, V Output for U-Phase & Bias Voltage Ground for High-Side MOSFET Driving S(U) 19 N Negative DC-Link Input for U-Phase U 20 N Negative DC-Link Input for V-Phase V 21 V, V Output for V-Phase & Bias Voltage Ground for High-Side MOSFET Driving S(V) 22 N Negative DC-Link Input for W-Phase W 23 W, V Output for W Phase & Bias Voltage Ground for High-Side MOSFET Driving S(W) (1) COM (2) V (17) P B(U) (3) V VCC VB CC(U) (4) IN HIN HO (UH) (5) IN(UL) LIN VS (18) U, VS(U) COM LO (6) N.C (19) N (7) V U B(V) (8) V VCC VB (20) N CC(V) V (9) IN HIN HO (VH) (10) IN(VL) LIN VS (21) V, VS(V) COM LO (11) VTS VTS (12) V B(W) (13) V VCC VB (22) N CC(W) W (14) IN HIN HO (WH) (15) IN(WL) LIN VS (23) W, VS(W) COM LO (16) N.C Figure 1. Pin Configuration and Internal Block Diagram (Bottom View) 1st Notes: 3. Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside Motion SPM® 5 product. External connections should be made as indicated in Figure 3. ©2012 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S Electrical Characteristics B (T = 25°C, V = V = 15 V unless otherwise specified.) J CC BS 5 0 Inverter Part (each MOSFET unless otherwise specified.) 8 2 Symbol Parameter Conditions Min Typ Max Unit 5 A Drain - Source S BVDSS Breakdown Voltage VIN = 0 V, ID = 1 mA (2nd Note 1) 250 - - V M Zero Gate Voltage o IDSS Drain Current VIN = 0 V, VDS = 250 V - - 1 mA ti o n Static Drain - Source RDS(on) Turn-On Resistance VCC = VBS = 15 V, VIN = 5 V, ID = 2.0 A - 0.33 0.45  S P Drain - Source Diode M V V = V = 15V, V = 0 V, I = -2.0 A - - 1.2 V SD Forward Voltage CC BS IN D ® t - 950 - ns 5 ON S tOFF VPN = 150 V, VCC = VBS = 15 V, ID = 2.0 A - 520 - ns e V = 0 V  5 V, Inductive Load L = 3 mH r trr Switching Times HIiNgh- and Low-Side MOSFET Switching - 150 - ns ie s EON (2nd Note 2) - 100 - J E - 10 - J OFF V = 200 V, V = V = 15 V, I = I , V = BV , Reverse Bias Safe Oper- PN CC BS D DP DS DSS RBSOA T = 150°C Full Square ating Area J High- and Low-Side MOSFET Switching (2nd Note 3) Control Part (each HVIC unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit V = 15 V, I Quiescent V Current CC Applied Between V and COM - - 200 A QCC CC V = 0 V CC IN V = 15 V, Applied Between V - U, I Quiescent V Current BS B(U) - - 100 A QBS BS V = 0 V V - V, V - W IN B(V) B(W) UVCCD Low-Side Under-Voltage VCC Under-Voltage Protection Detection Level 7.4 8.0 9.4 V UV Protection (Figure 8) V Under-Voltage Protection Reset Level 8.0 8.9 9.8 V CCR CC UVBSD High-Side Under-Voltage VBS Under-Voltage Protection Detection Level 7.4 8.0 9.4 V UV Protection (Figure 9) V Under-Voltage Protection Reset Level 8.0 8.9 9.8 V BSR BS HVIC Temperature Sens- VTS ing Voltage Output VCC = 15 V, THVIC = 25°C (2nd Note 4) 600 790 980 mV V ON Threshold Voltage Logic HIGH Level - - 2.9 V IH Applied between IN and COM V OFF Threshold Voltage Logic LOW Level 0.8 - - V IL Bootstrap Diode Part (each bootstrap diode unless otherwise specified.) Symbol Parameter Conditions Min Typ Max Unit V Forward Voltage I = 0.1 A, T = 25°C (2nd Note 5) - 2.5 - V FB F C t Reverse Recovery Time I = 0.1 A, T = 25°C - 80 - ns rrB F C 2nd Notes: 1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each MOSFET inside Motion SPM® 5 product. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VPN should not exceed BVDSS in any case. 2. tON and tOFF include the propagation delay of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applications due to the effect of different printed circuit boards and wirings. Please see Figure 6 for the switching time definition with the switching test circuit of Figure 7. 3. The peak current and voltage of each MOSFET during the switching operation should be included in the Safe Operating Area (SOA). Please see Figure 7 for the RBSOA test circuit that is same as the switching test circuit. 4. Vts is only for sensing-temperature of module and cannot shutdown MOSFETs automatically. 5. Built-in bootstrap diode includes around 15 resistance characteristic. Please refer to Figure 2. ©2012 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S Recommended Operating Condition B 5 0 Symbol Parameter Conditions Min. Typ. Max. Unit 8 2 5 V Supply Voltage Applied Between P and N - 150 200 V PN A V Control Supply Voltage Applied Between V and COM 13.5 15.0 16.5 V S CC CC V High-Side Bias Voltage Applied Between V and V 13.5 15.0 16.5 V M BS B S o VIN(ON) Input ON Threshold Voltage Applied Between IN and COM 3.0 - VCC V tio VIN(OFF) Input OFF Threshold Voltage 0 - 0.6 V n Blanking Time for Preventing S tdead Arm-Short VCC = VBS = 13.5 ~ 16.5 V, TJ 150°C 1.0 - - s P M fPWM PWM Switching Frequency TJ 150°C - 15 - kHz ® 5 S e r i e Built-in Bootstrap Diode V-I Characteristic s F F 1.0 0.9 0.8 0.7 0.6 A] 0.5 [F I 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 V [V] F Tc=25°C Figure 2. Built-in Bootstrap Diode Characteristics (Typical) ©2012 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S B 5 These values depend on PWM control algorithm 0 8 2 +15 V C1 * Example Circuit : V phase 5 A S V DC P HIN LIN Output Note M VCC VB Inverter 0 0 Z Both FRFETOff o R t U 5 HIN HO V Output 0 1 0 Low side FRFET On io MC LIN VS C3 1 0 VDC High side FRFET On n S C5 COM LO 1 1 Forbidden Shoot through P VTS N R3 Open Open Z Same as(0,0) M 10F C2 C4 One Leg Diagram of Motion SPM® 5 Product ® 5 * Example of Bootstrap Param:ters S C = C = 1F Ceramic Capacitor e 1 2 r i Figure 3. Recommended MCU Interface and Bootstrap Circuit with Parameters e s 3rd Notes: 1. Parameters for bootstrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. 2. RC-coupling (R5 and C5) and C4 at each input of Motion SPM 5 product and MCU (Indicated as Dotted Lines) may be used to prevent improper signal due to surge-noise. 3. Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge-voltage. Bypass capacitors such as C1, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple-current. Figure 4. Case Temperature Measurement 3rd Notes: 4. Attach the thermocouple on top of the heat-sink of SPM 5 package (between SPM 5 package and heatsink if applied) to get the correct temperature measurement. 3.5 3.0 2.5 ] V 2.0 [S T V 1.5 1.0 0.5 20 40 60 80 100 120 140 160 THVIC [oC] Figure 5. Temperature Profile of VTS (Typical) ©2012 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S B 5 0 8 V V IN IN 2 I 5 rr 100% of ID 120% of ID AS V I DS D M o 10% of I t D i I V o D DS n S P t t t ON rr OFF M ® (a) Turn-on (b) Turn-off 5 S Figure 6. Switching Time Definitions e r i e C s BS V I CC D VCC VB L V HIN HO DC LIN VS + COM LO V DS - VTS One Leg Diagram of Motion SPM® 5 Product Figure 7. Switching and RBSOA (Single-pulse) Test Circuit (Low-side) Input Signal UV Protection RESET DETECTION RESET Status UV Low-side Supply, V CCR CC UV CCD MOSFET Current Figure 8. Under-Voltage Protection (Low-Side) Input Signal UV Protection RESET DETECTION RESET Status UV High-side Supply, V BSR BS UV BSD MOSFET Current Figure 9. Under-Voltage Protection (High-Side) ©2012 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FSB50825AS Rev. 1.6

F S B 5 0 8 2 C 1 5 A (1) COM S (2) VB(U) (17) P M (3) VCC(U) VCC VB o R5 ((45)) IINN((UUHL)) HLIINN HVOS (18) U, VS(U) C3 VDC tion S C5 C2 COM LO P (6) N.C M (7) VB(V) (19) NU ® 5 (8) VCC(V) VCC VB (20) NV S (9) IN(VH) e m (10) IN(VL) HIN HO (21) V, VS(V) M rie LIN VS o s Mic (11) VTS CVOM LO TS (12) V B(W) (13) V (22) N CC(W) W VCC VB (14) IN (WH) HIN HO (15) IN(WL) (23) W, VS(W) LIN VS COM LO (16) N.C C 4 R For current-sensing and protection 4 15V Supply C6 R3 Figure 10. Example of Application Circuit 4th Notes: 1. About pin position, refer to Figure 1. 2. RC-coupling (R5 and C5, R4 and C6) and C4 at each input of Motion SPM® 5 product and MCU are useful to prevent improper input signal caused by surge-noise. 3. The voltage-drop across R3 affects the low-side switching performance and the bootstrap characteristics since it is placed between COM and the source terminal of the low- side MOSFET. For this reason, the voltage-drop across R3 should be less than 1 V in the steady-state. 4. Ground-wires and output terminals, should be thick and short in order to avoid surge-voltage and malfunction of HVIC. 5. All the filter capacitors should be connected close to Motion SPM 5 product, and they should have good characteristics for rejecting high-frequency ripple current. ©2012 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com FSB50825AS Rev. 1.6

None

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