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F R 0 1 1 November 2012 L 5 J — L o w FR011L5J (11mΩ, -30V) -S i d Low-Side Reverse Bias / Reverse Polarity Protector e R e v e Features rs Description e  Up to -30V Reverse-Bias Protection B Reverse bias is an increasingly common fault event that i a  Nano Seconds of Reverse-Bias Blocking may be generated by user error, improperly installed s Response Time batteries, automotive environments, erroneous / connections to third-party chargers, negative “hot plug” R  +29V 24-Hour “Withstand” Rating e transients, inductive transients, and readily available v  11mΩ Typical Series Resistance at 5V negatively biased rouge USB chargers. e r s  MicroFET™ 2x2mm Package Size Fairchild circuit protection is proud to offer a new type of e reverse bias protection devices. The FR devices are low P  RoHs Compliant resistance, series switches that, in the event of a o l  USB Tested and Compatible reverse bias condition, shut off power and block the a r negative voltage to help protect downstream circuits. it y Applications The FR devices are optimized for the application to offer P best in class reverse bias protection and voltage ro  USB 1.0, 2.0 and 3.0 Devices capabilities while minimizing size, series voltage drop, t e  USB Charging and normal operating power consumption. ct o  Mobile Devices In the event of a reverse bias application, FR011L5J r devices effectively provide a full voltage block and can  Mobile Medical easily protect -0.3V rated silicon.  POS Systems From a power perspective, in normal bias, an 11mΩ FR  Toys device in a 1.5A application will generate only 17mV of voltage drop or 25mW of power loss. In reverse bias,  Any DC Barrel Jack Powered Device FR devices dissipate less then 20µW in a 16V reverse  Any DC Devices subject to Negative Hot Plug or bias event. This type of performance is not possible with a diode solution. Inductive Transients  Automotive Peripherals Benefits extend beyond the device. Due to low power dissipation, not only is the device small, but heat sinking Pin 1 CTL requirements and cost can be minimized as well. NEG POS MicroFET 2x2 mm Ordering Information Part Number Top Mark Package Packing Method 6-Lead, Molded Leadless Package (MLP), Dual, 3000 on Tape & Reel; FR011L5J 11L Non-JEDEC, 2mm Square, Single-Tied DAP 7-inch Reel, 12mm Tape © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3

F R 0 Diagrams 1 1 L CTL Protected USB Device Circuit 5 J — Power IIN L Switch o Power Source USB Device w V - NEG Startup Diode POS (USB Connector) IN Circuit S Inrush Reducer CTL id e OV Bypass NEG POS R Protection e FR011L5J v e r s Figure 1. Block Diagram Figure 2. Typical Schematic e B i a s / R Pin Configuration e v e r s Pin 1 e CTL P o l a r i t NEG y P r o POS t e c to r Figure 3. Pin Assignments Pin Definitions Name Pin Description The ground of the load circuit being protected. Current flows into this pin during normal POS 4 operation. The control pin of the device. A positive voltage to the NEG pin turns the switch on and a CTL 3 negative voltage turns the switch to a high-impedance state. NEG 1, 2, 5, 6 The ground of the input power source. Current flows out of this pin during normal operation. © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 2

F R 0 Absolute Maximum Ratings 1 1 L Values are at TA=25°C unless otherwise noted. 5 J Symbol Parameter Value Unit — L Steady-State Normal Operating Voltage between CTL and NEG Pins V+ +20 o MAX_OP (VIN = V+ MAX_OP, IIN = 1.5A, Switch On) w - 24-Hour Normal Operating Voltage Withstand Capability between CTL and S V+ 24 NEG Pins (V = V+ , I = 1.5A, Switch On) +29 V id IN 24 IN e V- Steady-State Reverse Bias Standoff Voltage between CTL and NEG Pins -30 R MAX_OP (VIN = V- MAX_OP) e v I Input Current V = 5V, Continuous(2) (see Figure 4) 10 A e IN IN r s TJ Operating Junction Temperature 150 °C e T = 25°C(2) (see Figure 4) 2.4 B A PD Power Dissipation TA = 25°C(2) (see Figure 5) 0.9 W ias / I Steady-State Diode Continuous Forward Current from POS to NEG 2 DIODE_CONT R A I Pulsed Diode Forward Current from POS to NEG (300µs Pulse) 210 e DIODE_PULSE v e Human Body Model, JESD22-A114 0.6 r s Electrostatic Discharge Charged Device Model, JESD22-C101 2 e ESD kV P Capability System Model, IEC61000-4-2 Contact 8 o (CTL is shorted to POS)(3) Air 15 la r i t Notes: y 1. The V rating is NOT a survival guarantee. It is a statistically calculated survivability reference point taken on P +24 qualification devices, where the predicted failure rate is less than 0.01% at the specified voltage for 24 hours. It is ro intended to indicate the device’s ability to withstand transient events that exceed the recommended operating te voltage rating. Specification is based on qualification devices tested using accelerated destructive testing at c t higher voltages, as well as production pulse testing at the V level. Production device field life results may vary. o +24 r Results are also subject to variation based on implementation, environmental considerations, and circuit dynamics. Systems should never be designed with the intent to normally operate at V levels. Contact Fairchild +24 Semiconductor for additional information. 2. The device power dissipation and thermal resistance (R ) are characterized with device mounted on the following θ FR4 printed circuit boards, as shown in Figure 4 and Figure 5 3. Conducted with shorted load. Open load performance is not guaranteed. Figure 4. 1 Square Inch of 2-ounce copper Figure 5. Minimum Pads of 2-ounce Copper Thermal Characteristics Symbol Parameter Value Unit R Thermal Resistance, Junction to Ambient(2) (see Figure 4) 61 θJA °C/W R Thermal Resistance, Junction to Ambient(2) (see Figure 5) 153 θJA © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 3

F R 0 Electrical Characteristics 1 1 L Values are at TA = 25°C unless otherwise noted. 5 J Symbol Parameter Conditions Min. Typ. Max. Unit — Positive Bias Characteristics L o w V = +4V, I = 1.5A 13 20 IN IN - S V = +5V, I = 1.5A 11 15 IN IN i d RON Device Resistance, Switch On VIN = +5V, IIN = 1.5A, 15 mΩ e T = 125°C R J e V = +12V, I = 1.5A 9 13 v IN IN e Input Voltage, VIN, at which Voltage rs VON at POS, VPOS, Reaches a Certain IIN = 100mA, VPOS = 45mV, 1.4 2.4 3.5 V e Level at Given Current V = 0V B NEG i a ∆VON / ∆TJ Temperature Coefficient of VON -3.9 mV/°C s IDIODE_CONT Continuous Diode Forward Current VCTL = VPOS 2 A / R V = V , I = 0.1A, e V Diode Forward Voltage CTL POS DIODE 0.56 0.60 0.73 V v F Pulse width < 300µs e r Bias Current Flowing out of NEG Pin V = 5V, V = 0V, s I CTL NEG 15 nA e BIAS during Normal Bias Operation No Load P Negative Bias Characteristics o l a V- Reverse Bias Breakdown Voltage -30 V r MAX_OP i t ∆V- MAX_OP Reverse Bias Breakdown Voltage IIN = -250µA, VCTL = VPOS = 0V 16 mV/°C y P / ∆T Temperature Coefficient J r o Leakage Current from NEG to POS t I- V = 20V, V = V = 0V 1 µA e in Reverse-Bias Condition NEG CTL POS c t V = 5V, V = 0V, C = o Time to Respond to Negative Bias NEG CTL LOAD r t 10µF, Reverse Bias Startup 50 ns RN Condition Inrush Current = 0.2A Dynamic Characteristics Input Capacitance between CTL and C 1011 I NEG Switch Capacitance between POS V = -5V, V = V = 0V, f C IN CTL POS 81 pF S and NEG = 1MHz Output Capacitance between CTL C 1456 O and POS R Control Internal Resistance 1.7 Ω C © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 4

F Typical Characteristics R 0 1 TJ = 25°C unless otherwise specified. 1 L 5 Ω) 16 NG 3.2 J — E (m 14 Input Voltage, VIN = 4V URNI L C T 3.0 o AN 12 5V GE V) w RESIST 108 VOLTA WITCH (2.8 -Sid TCH ON- 46 9V 12V 16V M INPUT N THE S2.6 e Rev WI U O2.4 e R, SON 020 2 4 6 8 10 12 14 16 18 20 , MINIMN 2.20.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 rse B O V i a IIN, INPUT CURRENT (A) IIN, INPUT CURRENT (A) s / Figure 6. Switch On Resistance vs. Switch Current Figure 7. Minimum Input Voltage to Turn On Switch R e vs. Current at 45mV Switch Voltage Drop v e r Ω) s CE ( 1.0 Ω) 15 e P CH RESISTAN 00..68 IIN0 =.9 0A.1A TJ = 25oC ESISTANCE (m 11111234 IIN = 0.1A VIN = 5V olarity P WIT 1.5A N-R 10 12V ro S 0.4 O t E H 9 e , EFFECTIVW 00..02 R, SWITCON 678 ctor RS 1 3 5 7 9 11 13 15 17 19 21 -75 -50 -25 0 25 50 75 100 125 150 V , INPUT VOLTAGE (V) T, JUNCTION TEMPERATURE (oC) IN J Figure 8. Effective Switch Resistance R vs. Figure 9. Switch On Resistance vs. Junction SW Input Voltage V Temperature at 0.1A IN Ω) 15 1000 E (m 14 IIN = 1.5A W) TANC 1123 V = 5V WER ( 100 S IN O ESI 11 E P R G 10 N- 10 12V A O K H 9 AC C P WIT 8 AK 1 ,SN 7 PE O R 6 0.1 -75 -50 -25 0 25 50 75 100 125 150 1E-4 1E-3 0.01 0.1 1 10 100 1000 T, JUNCTION TEMPERATURE (oC) t, PULSE WIDTH (s) J Figure 10. Switch On Resistance vs.Junction Figure 11.Single-Pulse Maximum Power vs.Time Temperature at 1.5A © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 5

F R Typical Characteristics 0 1 T = 25°C unless otherwise specified. 1 J L 5 J A) — T ( 100 REN VPOS = VCTL = 0V Lo UR 10 w D C TJ = 125oC -S AR 1 id ORW 25oC e R F 0.1 E e D -55oC v O e DI 0.01 r P s U e T R 1E-3 B STA 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 ia I, F VF, STARTUP DIODE FORWARD VOLTAGE (V) s / R Figure 12. Startup Diode Current vs. Forward Voltage e v e r s e P o l a r i t y P r o t e c t o r © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 6

F R 0 Application Test Configurations 1 1 L 5 Protected USB Device Circuit J — L o I w IN - S i d Power Source USB Device e R V (USB Connector) IN Circuit e v e CTL r s e NEG POS B i a s FR011L5J / R e v Figure 13. Typical Application Circuit for USB Applications e r s e P o Q1-1 l a FDS8858CZ r 5,6 D2 it y 3 S2 P i r IN o t 4 G2 e c R1 t o r D SC Q1-2 up P C1 7,8 D1 FDS8858CZ po lw y e 2 G1 r R3 C2 G e nP 1 S1 erauls R2 te o CTL r NEG POS FR011L5J Figure 14. Startup Test Circuit – Normal Bias with FR011L5J © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 7

F R 0 Application Test Configurations (Continued) 1 1 L 5 J — L o i IN w G enP -S eu R2 id rals 1 S1 e toe R r e 2 G1 v e D Q1-2 rs SC FDS8858CZ e u P 7,8 D1 B p po ia lyw C1 R3 C2 s e r / R e v e R1 r s 4 G2 e CTL P o 3 S2 5,6 D2 NEG POS l a r Q1-1 i t y FDS8858CZ FR011L5J P r o Figure 15. Startup Test Circuit – Reverse Bias with FR011L5J t e c t o Q1-1 r FDS8858CZ 5,6 D2 3 S2 i IN 4 G2 R1 D SC Q1-2 up P C1 7,8 D1 FDS8858CZ po lw y e 2 G1 r R3 C2 G e nP 1 S1 eruls R2 a e t o r Figure 16. Startup Test Circuit – without FR011L5J © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 8

F R 0 Typical Application Waveforms 1 1 L Typical USB3.0 conditions. 5 J — L o w - S i d e ─ V , 2V/div. The input voltage between CTL and NEG IN R ─ V , 1V/div. The startup diode voltage between POS and NEG e D v ─ VOUT, 2V/div. The output voltage between CTL and POS e ─ iIN, 5A/div. The input current flowing from POS to NEG rs e B i a s / R e v e r s e P Time: 5µs/div o l a r i t y Figure 17. Normal Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10kΩ, R3=27Ω P r o t e c t o r ─ V , 2V/div. The input voltage between CTL and NEG IN ─ V , 2V/div. The startup diode voltage between POS and NEG D ─ V , 1V/div. The output voltage between CTL and POS OUT ─ i , 0.1A/div. The input current flowing out of NEG IN Time: 100ns/div Figure 18. Reverse Bias Startup Waveform, DC Power Source=5V, C =100µF, C =10µF, R =R =10kΩ, R =27Ω 1 2 1 2 3 © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 9

F R 0 1 Typical Application Waveforms (Continued) 1 L Typical USB3.0 conditions. 5 J — L o w - S i d e R e v e r s e B i a s / ─ V , 2V/div. The voltage applied on the load circuit R IN e ─ iIN, 2A/div. The input current v e r s e P o l a r i Time: 5us/div ty P Figure 19. Startup Waveform without FR011L5J, DC Power Source=5V, C =100µF, C =10uF, r 1 2 o R1=R2=10kΩ, R3=27Ω te c t Application Information o r Figure 17 shows the voltage and current waveforms USB3.0 device is reversely biased; the output voltage is when a virtual USB3.0 device is connected to a 5V near 0 and response time is less than 50ns. source. A USB application allows a maximum source Figure 19 shows the voltage and current waveforms output capacitance of C = 120µF and a maximum 1 when no reverse bias protection is implemented. In device-side input capacitance of C = 10µF plus a 2 Figure 17, while the reverse bias protector is present, maximum load (minimum resistance) of R = 27Ω. C = 3 1 the input voltage, V , and the output voltage, V , are 100µF, C = 10µF and R = 27Ω were used for testing. IN O 2 3 separated and look different. When this reverse bias When the DC power source is connected to the circuit protector is removed, V and V merge, as shown IN O (refer to Figure 13), the built-in startup diode initially inFigure 19 as V . This V is also the voltage applied to IN IN conducts the current such that the USB device powers the load circuit. It can be seen that, with reverse bias up. Due to the initial diode voltage drop, the FR011L5J protection, the voltage applied to the load and the effectively reduces the peak inrush current of a hot plug current flowing into the load look very much the same as event. Under these test conditions, the input inrush without reverse bias protection. current reaches about 6.3A peak. While the current Benefits of Reverse Bias Protection flows, the input voltage increases. The speed of this input voltage increase depends on the time constant The most important benefit is to prevent accidently formed by the load resistance R3 and load capacitance reverse-biased voltage from damaging the USB load. C2. The larger the time constant, the slower the input Another benefit is that the peak startup inrush current voltage increase. As the input voltage approaches a can be reduced. How fast the input voltage rises, the level equal to the protector’s turn-on voltage, VON, the input/output capacitance, the input voltage, and how protector turns on and operates in Low-Resistance heavy the load is determine how much the inrush Mode as defined by VIN and operating current IIN. current can be reduced. In a 5V USB application, for example, the inrush current can be 5% - 20% less with In the event of a negative transient, or when the DC different input voltage rising rate and other factors. This power source is reversely connected to the circuit, the can offer a system designer the option of increasing C device blocks the flow of current and holds off the 2 while keeping “effective” USB device capacitance down. voltage, thereby protecting the USB device. Figure 18 shows the voltage and current waveforms when a virtual © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 10

F R 0 1 Physical Dimensions 1 L 5 J (0.20) — 2.00 A 0.10 C 1.00 No Traces allowed in 2X B 6 4 this Area Lo w - S 1.35 2.00 1.05 i d 2.30 e (0.475) R 0.10 C e Pin #1 location TOP VIEW 2X 0.65 TYP1 3 0.40 TYP ve r s RECOMMENDED LAND PATTERN OPT 1 e B i 0.8 MAX a s 0.10 C / (0.20) R e v 0.08 C 0.05 e 0.00 SIDE VIEW C r s SEATING e PLANE P o l a 0.15 0.45 r i 0.50 0.20 ty PIN #1 IDENT 10..0800 0.30 1.00 P r 1 3 6 4 o 6X00..3230 00..6511 te c 10..0955 1.05 0.661.352.30 to 0.50 r 6 4 1 3 0.35 0.65 6X 0.25 0.65 TYP 0.40 TYP 1.30 0.10 C A B 0.05 C RECOMMENDED LAND PATTERN OPT 2 BOTTOM VIEW A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-229 DATED AUG/2003 B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. DRAWING FILENAME: MKT-MLP06Lrev3. Figure 20. 6-Lead, Molded Leadless Package (MLP), Dual, Non-JEDEC, 2mm Square, Single-Tied DAP Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2012 Fairchild Semiconductor Corporation www.fairchildsemi.com FR011L5J • Rev. C3 11

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