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F P F 1 3 September 2013 2 0 / F P F FPF1320 / FPF1321 1 3 2 IntelliMAX™ Dual-Input Single-Output Advanced Power 1 — Switch with True Reverse-Current Blocking I n t Features e Description ll i M  DISO Load Switches The FPF1320/21 is a Dual-Input Single-Output (DISO) A  Input Supply Operating Range: 1.5 V ~ 5.5 V load switch consisting of two sets of slew-rate X™ controlled, low on-resistance, P-channel MOSFET  RON 50 mΩ at VIN=3.3 V Per Channel (Typical) switches and integrated analog features. The slew-rate- D  True Reverse-Current Blocking (TRCB) controlled turn-on characteristic prevents inrush current ua and the resulting excessive voltage droop on the power l  Fixed Slew Rate Controlled 130 µs for < 1 µF COUT rails. The input voltage range operates from 1.5 V to -In  I : 1.5 A Per Channel (Maximum) 5.5 V to align with the requirements of low-voltage p SW u  Quick Discharge Feature on FPF1321 pseoartmableles s dpeovwiceer -spoouwrceer trraanilssi.t ioFnPs Fb1e3t2w0e/e2n1 twpeor foinrpmust t S  Logic CMOS IO Meets JESD76 Standard for GPIO power rails using the SEL pin with advanced break- in Interface and Related Power Supply Requirements before-make operation. gl e  ESD Protected: FPF1320/21 has a TRCB function to block unwanted -O reverse current from output to input during ON/OFF u - Human Body Model: >6 kV states. The switch is controlled by logic inputs of the tp - Charged Device Model: >1.5 kV SEL and EN pins, which are capable of interfacing u t - IEC 61000-4-2 Air Discharge: >15 kV directly with low-voltage control signals (GPIO). A d - IEC 61000-4-2 Contact Discharge: >8 kV FPF1321 has 65 Ω on-chip load resistor for output quick v discharge when EN is LOW. a n Applications FPF1320/21 is available in 1.0 mm x 1.5 mm WLCSP, c e 6-bump, with 0.5 mm pitch. FPF1321B is available in d  Smart phones / Tablet PCs 1.0 mm x 1.5 mm WLCSP, 6-bump, 0.5 mm pitch with P  Portable Devices backside laminate. ow  Near Field Communication (NFC) Capable er SIM Card Power Supply S w i t c Ordering Information h Switch Per Reverse Top Output Rise Part Number Channel Channel (Typ.) Current Package Mark Discharge Time (t ) at 3.3 V Blocking R IN FPF1320UCX QS DISO 50 mΩ Yes NA 130 µs 1.0 mm X 1.5 mm Wafer-Level Chip- Scale Package (WLCSP) 6-Bumps, FPF1321UCX QT DISO 50 mΩ Yes 65 Ω 130 µs 0.5 mm Pitch 1.0 mm X 1.5 mm Wafer-Level Chip- Scale Package FPF1321BUCX QT DISO 50 mΩ Yes 65 Ω 130 µs (WLCSP) 6-Bumps, 0.5 mm Pitch with Backside Laminate © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2

F P Application Diagram F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X Figure 1. Typical Application ™ D u a l - I n Block Diagram p u t S i n g l e - O u t p u t A d v a n c e d P o w e r S w i t c h Figure 2. Functional Block Diagram (Output Discharge Path for FPF1321 Only) © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 2

F P F Pin Configuration 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ Figure 3. Pin Configuration in Package View with Pin 1 Indicator D u a l - I n p EN VINA VINA EN u t A1 A2 A2 A1 S i n SEL VOUT VOUT SEL g l e B1 B2 B2 B1 - O u GND VINB VINB GND t p C1 C2 C2 C1 u t A d v a n Top View Bottom View c e Figure 4. Pin Assignments d P o Pin Description w e r Pin # Name Description S w A1 EN Enable input. Active HIGH. There is an internal pull-down resistor at the EN pin. i t Input power selection inputs. See Table 1. There are internal pull-down resistors at the c B1 SEL h SEL pins. A2 V A Supply Input. Input to the power switch A. IN B2 V Switch output OUT C1 GND Ground C2 V B Supply Input. Input to power switch B. IN Table 1. Truth Table SEL EN Switch A Switch B V Status OUT LOW HIGH ON OFF V A V A Selected IN IN HIGH HIGH OFF ON V B V B Selected IN IN Floating for FPF1320 X LOW OFF OFF Both Switches are OFF GND for FPF1321 © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 3

F P F Absolute Maximum Ratings 1 3 2 Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be 0 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. / In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. F P The absolute maximum ratings are stress ratings only. F 1 3 Symbol Parameters Min. Max. Unit 2 1 VIN VINA, VINB, VSEL, VEN, VOUT to GND -0.3 6 V — ISW Maximum Continuous Switch Current per Channel 1.5 A I n PD Total Power Dissipation at TA=25°C 1.2 W te l TSTG Operating and Storage Junction Temperature -65 150 °C liM Thermal Resistance, Junction-to-Ambient 85(1) A ΘJA (1 in.2 Pad of 2-oz. Copper) 110(2) °C/W X™ Human Body Model, JESD22-A114 6.0 D u Charged Device Model, JESD22-C101 1.5 a ESD EClaepcatrboislittay tic Discharge AIEirC D6i1s0c0h0a-r4g-e2 (SVyINsAte, mVI NLBe vtoe lG ND), 15.0 kV l-Inp u Contact Discharge (VINA, VINB to 8.0 t GND), IEC61000-4-2 System Level S i n Notes: g 1. Measured using 2S2P JEDEC std. PCB. l e 2. Measured using 2S2P JEDEC PCB cold-plate method. - O u tp u t Recommended Operating Conditions A d v The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended a n operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not c recommend exceeding them or designing to Absolute Maximum Ratings. e d P Symbol Parameters Min. Max. Unit o w V Input Voltage on V A, V B 1.5 5.5 V IN IN IN e r TA Ambient Operating Temperature -40 85 °C S w i t c h © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 4

F P Electrical Characteristics F 1 3 V A=V B=1.5 to 5.5 V, T =-40 to 85°C unless otherwise noted. Typical values are at V A=V B=3.3 V and T =25°C. 2 IN IN A IN IN A 0 / Symbol Parameters Condition Min. Typ. Max. Unit F P Basic Operation F 1 V A, V B Input Voltage 1.5 5.5 V 3 IN IN 2 SEL=HIGH or LOW, EN=GND, 1 I Shutdown Current 5 µA SD V =GND, V A=V B=5.5 V — OUT IN IN I Quiescent Current IOUT=0mA, SEL=HIGH or LOW, 12 22 μA In Q EN=HIGH, V A=V B=5.5 V t IN IN e l VINA=VINB=5.5 V, IOUT=200 mA, 42 60 liM T =25°C A A V A=V B=3.3 V, I =200 mA, X IN IN OUT 50 ™ T =25°C A RON On-Resistance mΩ D V A=V B=1.8 V, I =200 mA, IN IN OUT 80 u TA=25°C to 85°C a l VINA=VINB=1.5 V, IOUT=200 mA, 170 -In TA=25°C p u SEL, EN Input Logic High t VIH Voltage VINA, VINB=1.5 V – 5.5 V 1.15 V S i n SEL, EN Input Logic Low V A V B=1.8 V – 5.5 V 0.65 V g Voltage IN , IN le VIL SEL, EN Input Logic Low -O Voltage VINA, VINB=1.5 V – 1.8 V 0.60 u t p Output Voltage Droop while u VDROOP_OUT CHhigahnenr eInl Spuwti tVcohlitnagg efr oLmow er VVINAA= 3. 3V VB, V, RINB==155 0V ,Ω S, wCitchi=n1g µfrFo m 100 mV t A IN IN L OUT d Input Voltage(3) v a Input Leakage at SEL and n ISEL/IEN EN Pin 1.2 μA c e d RSEL_PD/REN_PD PSuElLl- Door wEnN RPeins istance at 7 MΩ P o w Output Pull-Down SEL=HIGH or LOW, EN=GND, R 65 Ω e PD Resistance IFORCE=20 mA, TA=25°C, FPF1321 r S True Reverse Current Blocking w i VT_RCB RCB Protection Trip Point VOUT - VINA or VINB 45 mV tc h RCB Protection Release V V A or V B -V 25 mV R_RCB Trip Point IN IN OUT V Aor V B Current During V =5.5 V, V A or V B=Short to I IN IN OUT IN IN 9 15 μA RCB RCB GND RCB Response Time when tRCB_ON Device is ON(3) VINA or VINB=5 V, VOUTVINA,B=100 mV 5 µs Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 5

F P Electrical Characteristics (Continued) F 1 3 V A=V B=1.5 to 5.5 V, T =-40 to 85°C unless otherwise noted. Typical values are at V A=V B=3.3 V and T =25°C. 2 IN IN A IN IN A 0 / Symbol Parameters Condition Min. Typ. Max. Unit F P Dynamic Characteristics F 1 t Turn-On Delay(4) 120 μs 3 DON V A or V B=3.3 V, R =150 Ω, 2 tR VOUT Rise Time(4) CILN=1 µF, ITNA=25°C, SELL: HIGH, 130 μs 1 — tON Turn-On Time(6) EN: LOW  HIGH 250 μs I n tDOFF Turn-Off Delay(4) VINA or VINB=3.3 V, RL=150 Ω, 15 μs te tF VOUT Fall Time(4) CL=1 µF, TA=25°C, SEL: HIGH, 320 μs lli M tOFF Turn-Off Time(7) EN: HIGH  LOW 335 μs A t Turn-Off Delay(4,5) V A or V B =3.3 V, R =150 Ω, 6 μs X DOFF IN IN L ™ tF VOUT Fall Time(4,5) CENL=: 1H µIGF,H T A= 2L5O°WC,, S EL: HIGH, 110 μs D tOFF Turn-Off Time(5,7) Output Discharge Mode, FPF1321 116 μs ua l Transition Time V A=3.3 V, V B=5 V, - tTRANR LOW  HIGH(4) SIwNitching fromIN V A  V B, 3 μs In IN IN p SEL: LOW  HIGH, EN: HIGH, u tSLH Switch-Over Rising Delay(4) RL=150 Ω, CL=1 µF, TA=25°C 1 μs t S t Transition Time VINA=3.3 V, VINB=5 V, 45 μs in TRANF HIGH  LOW(4) Switching from VINB  V A, g IN l SEL: HIGH  LOW, EN: HIGH, e tSHL Switch-Over Falling Delay(4) RL=150 Ω, C=1 µF, TA=25°C 5 μs -O u Notes: t p 3. This parameter is guaranteed by design and characterization; not production tested. u 4. t /t /t /t /t /t /t /t are defined in Figure 5. t DON DOFF R F TRANR TRANF SLH SHL A 5. FPF1321 output discharge is enabled during off. d 6. tON=tR + tDON. v 7. t =t + t . a OFF F DOFF n c e d P o w e r S w i t c h © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 6

F Timing Diagram P F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ D u a l - I n p u t S i n g l e - O u Figure 5. Dynamic Behavior Timing Diagram tp u t A d v a n c e d P o w e r S w i t c h © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 7

F P F Typical Characteristics 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ D Figure 6. Supply Current vs. Temperature Figure 7. Supply Current vs. Supply Voltage u a l - I n p u t S i n g l e - O u t p u t A d v a n c e Figure 8. Shutdown Current vs. Temperature Figure 9. Shutdown Current vs. Supply Voltage d P o w e r S w i t c h Figure 10. R vs. Temperature Figure 11. R vs. Supply Voltage ON ON Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 8

F P Typical Characteristics F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ Figure 12. VIL vs. Temperature Figure 13. VIL vs. Supply Voltage D u a l - I n p u t S i n g l e - O u t p u t A d v a n c e Figure 14. VIH vs. Temperature Figure 15. VIH vs. Supply Voltage d P o w e r S w i t c h Figure 16. V / V vs. Supply Voltage Figure 17. R and R vs. Temperature IH IL SEL_PD EN_PD Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 9

F P Typical Characteristics F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ Figure 18. RSEL_PD and REN_PD vs. Supply Voltage Figure 19. tDON and tDOFF vs. Temperature D u a l - I n p u t S i n g l e - O u t p u t A d v a n c e d Figure 20. tR and tF with FPF1320 vs. Temperature Figure 21. tR and tF with FPF1321 vs. Temperature P o w e r S w i t c h Figure 22. Transition Time vs. Temperature Figure 23. Switch Over Time vs. Temperature Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 10

F P Typical Characteristics F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ Figure 24. TRCB Trip and Release vs. Temperature Figure 25. IRCB vs. Temperature D u a l - I n p u t S i n g l e - O u t p u t A d v a n c Figure 26. RPD with FPF1321 vs. Temperature Figure 27. Turn-On Response e d (V A=3.3 V, C =1 µF, C =1 µF, R =150 Ω, IN IN OUT L SEL=LOW) P o w e r S w i t c h Figure 28. Turn-Off Response with FPF1320 Figure 29. Turn-Off Response with FPF1321 (V A=3.3 V, C =1 µF, C =1 µF, R =150 Ω, (V A=3.3 V, C =1 µF, C =1 µF, R =150 Ω, IN IN OUT L IN IN OUT L SEL=LOW) SEL=LOW) Continued on the following page… © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 11

F P Typical Characteristics F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ Figure 30. Power Source Transition from 3.3 V to 5 V Figure 31. Power Source Transition from 5 V to 3.3 V D (V A=3.3 V, V B=5 V, C =1 µF, C =1 µF, (V A=3.3 V, V B=5 V, C =1 µF, C =1 µF, u IN IN IN OUT IN IN IN OUT a RL=150 Ω) RL=150 Ω) l- I n p u t S i n g l e - O u t p u t A d v a n c e d P o w Figure 32. TRCB During Off (V A=V B=Floating, Figure 33. TRCB During On (V A=5 V, V =6 V, IN IN IN OUT e V =5V, C =1 µF, C =1 µF, EN=LOW, No R ) C =1 µF, C =1 µF, EN=HIGH, No R ) r OUT IN OUT L IN OUT L S w i t c h © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 12

F P Operation and Application Description F 1 The FPF1320 and FPF1321 are dual-input single-output Power Source Selection 3 2 power multiplexer switches with controlled turn-on and 0 seamless power source transition. The core is a 50 mΩ Input power source selection can be controlled by the / P-channel MOSFET and controller capable of SEL pin. When SEL is LOW, output is powered from F V A while SEL is HIGH, V B is powering output. The P functioning over a wide input operating range of 1.5 V to IN IN F SEL signal is ignored during device OFF. 5.5 V per channel. The EN and SEL pins are active- 1 3 HIGH, GPIO/CMOS-compatible input. They control the Output Voltage Drop during Transition 2 state of the switch and input power source selection, 1 respectively. TRCB functionality blocks unwanted Output voltage drop usually occurs during input power — source transition period from low voltage to high reverse current during both ON and OFF states when I voltage. The drop is highly dependent on output n higher V than V A or V B is applied. FPF1321 has a OUT IN IN capacitance and load current. te 65 Ω output discharge path during off. l l FPF1320/1 adopts an advanced break-before-make iM Input Capacitor control, which can result in minimized output voltage A To limit the voltage drop on the input supply caused by drop during the transition time. X transient inrush current when the switch turns on into a ™ discharged load capacitor; a capacitor must be placed Output Capacitor D between the VINA or VINB pins to the GND pin. At least Capacitor COUT of at least 1 µF is highly recommended u 1u sµuFa lclye rasumfficic iceanpt.a cHitoigrh, eCrI-Nv,a plulaec eCdI Nc locsaen tob eth eu pseinds , tios boeuttpwuete vno ltthaeg eV dOrUoTp a dnudr inGgN iDnp puitn pso twoe ar cshoiuervcee mtrainnimsitiizoend. al-In reduce more the voltage drop. This capacitor also prevents parasitic board inductance. p u Inrush Current True Reverse-Current Blocking t S Inrush current occurs when the device is turned on. The true reverse-current blocking feature protects the in Inrush current is dependent on output capacitance and input source against current flow from output to input g slew rate control capability, as expressed by: regardless of whether the load switch is on or off. le - O V −V Board Layout u IINRUSH =COUT × IN t INITIAL + ILOAD (1) For best performance, all traces should be as short as tp R possible. To be most effective, the input and output ut where: capacitors should be placed close to the device to A minimize the effect that parasitic trace inductance on d COUT: Output capacitance; normal and short-circuit operation. Wide traces or large va t : Slew rate or rise time at V ; copper planes for power pins (V A, V B, V and n R OUT IN IN OUT c GND) minimize the parasitic electrical effects and the e VIN: Input voltage, VINA or VINB; thermal impedance. d P V : Initial voltage at C , usually GND; and INITIAL OUT o w I : Load current. LOAD e r Higher inrush current causes higher input voltage drop, S depending on the distributed input resistance and input w capacitance. High inrush current can cause problems. it c FPF1320/1 has a 130 µs of slew rate capability under h 3.3 V at 1 µF of C and 150 Ω of R so inrush IN OUT L current and input voltage drop can be minimized. © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 13

F P Physical Dimensions F 1 3 2 0 0.03 C E A F (Ø0.250) / F 2X Cu Pad P B SOL(ØDE0.R3 5M0A)SK A1 F 1 OPENING 3 BALL A1 (1.00) 21 INDEX AREA D — (0.50) 0.03 C In 2X te l TOP VIEW RECOMMENDED LAND PATTERN liM (NSMD PAD TYPE) A X 0.06 C ™ 0.625 0.332±0.018 D 0.05 C 0.539 E 0.250±0.025 u a l - I n C SEATING PLANE D p u SIDE VIEWS t S i n NOTES: g l e A. NO JEDEC REGISTRATION APPLIES. - O 0.005 C A B B. DIMENSIONS ARE IN MILLIMETERS. ut p Ø0.315 +/- .025 C. DIMENSIONS AND TOLERANCE u 0.50 6X PER ASMEY14.5M, 1994. t A C D. DATUM C IS DEFINED BY THE SPHERICAL d CROWNS OF THE BALLS. v 1.00 B (Y) ±0.018 a 0.50 n A E. PACKAGE NOMINAL HEIGHT IS 582 MICRONS c ±43 MICRONS (539-625 MICRONS). e 1 2 F d (X) ±0.018 F. FOR DIMENSIONS D, E, X, AND Y SEE P PRODUCT DATASHEET. o w BOTTOM VIEW G. DRAWING FILNAME: MKT-UC006AFrev2. e r S w i t Figure 34. 6-Ball, 1.0 x 1.5 mm, Wafer-Level Chip-Scale Package (WLCSP) c h Product-Specific Dimensions Product D E X Y FPF1320UCX 1460 µm ±30 µm 960 µm ±30 µm 230 µm 230 µm FPF1321UCX 1460 µm ±30 µm 960 µm ±30 µm 230 µm 230 µm FPF1321BUCX 1460 µm ±30 µm 960 µm ±30 µm 230 µm 230 µm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. http://www.fairchildsemi.com/dwg/UC/UC006AF.pdf © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 14

F P F 1 3 2 0 / F P F 1 3 2 1 — I n t e l l i M A X ™ D u a l - I n p u t S i n g l e - O u t p u t A d v a n c e d P o w e r S w i t c h © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FPF1320 / FPF1321 • Rev. 1.0.2 15

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