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F O D 8 July 2014 3 1 6 — FOD8316 2 . 5 2.5 A Output Current, IGBT Drive Optocoupler with A O Desaturation Detection and Isolated Fault Sensing u t p u t Features Description C u ■ High Noise Immunity Characterized by The FOD8316 is an advanced 2.5 A output current rr e Common Mode Rejection – 35 kV/µs Minimum, IGBT drive optocoupler capable of driving most 1200 V / n VCM = 1500 VPEAK 150 A IGBTs. It is ideally suited for fast-switching driving t, ■ 2.5 A Peak Output Current Driving Capability for Most of power IGBTs and MOSFETs used in motor-control IG 1200 V / 150 A IGBTs inverter applications and high-performance power B systems. The FOD8316 offers critical protection features T ■ Optically Isolated Fault Sensing Feedback necessary for preventing fault conditions that lead to D ■ “Soft” IGBT Turn-off r destructive thermal runaway of IGBTs. iv ■ Built-in IGBT Protection e The device utilizes Fairchild’s proprietary Optoplanar® – Desaturation Detection O coplanar packaging technology, and optimized IC design p – Under-Voltage Lockout (UVLO) Protection to achieve high noise immunity, characterized by high to ■ Wide Supply Voltage Range: 15 V to 30 V common-mode rejection and power supply rejection c o – P-Channel MOSFETs at Output Stage Enables specifications. u Output Voltage Swing Close to the Supply Rail p The FOD8316 consists of an integrated gate drive opto- l (Rail-to-Rail Output) e coupler featuring low R CMOS transistors to drive r DS(ON) ■ 3.3 V / 5 V, CMOS/TTL Compatible Inputs the IGBT from rail-to-rail and an integrated high-speed w i ■ High Speed isolated feedback for fault sensing. The device is housed th – 500 ns Maximum Propagation Delay Over Full in a compact 16-pin small-outline plastic package which D Operating Temperature Range meets the 8 mm creepage and clearance requirements. e s ■ Extended Industrial Temperate Range: a t –40°C to 100°C u r ■ Safety and Regulatory Approvals a t i – UL1577, 4,243 V for 1 Minute o RMS n – DIN EN/IEC 60747-5-5: D 1,414 VPEAK Working Insulation Voltage Rating e t 8,000 VPEAK Transient Isolation Voltage Rating e c ■ RDS(ON) of 1 Ω (Typical) Offers Lower Power ti Dissipation o n ■ User-Configurable: Inverting, Non-inverting, a Auto-reset, Auto-shutdown n d ■ 8 mm Creepage and Clearance Distances I s o Applications l a t ■ Industrial Inverter e d ■ Induction Heating F a ■ Isolated IGBT Drive u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1

F O Truth Table D 8 3 UVLO DESAT 1 VIN+ VIN– (VDD2 – VE) Detected? FAULT VO 6 — X X Active X X LOW 2 X X X Yes LOW LOW .5 A LOW X X X X LOW O X HIGH X X X LOW u HIGH LOW Not Active No HIGH HIGH tp u t C Pin Configuration u r r e n VIN+ 1 16 VE t, I G VIN– 2 15 VLED2+ B T VDD1 3 14 DESAT D r i GND1 4 13 VDD2 ve O RESET 5 12 VS p t o FAULT 6 11 VO c o u VLED1+ 7 10 VSS p l e VLED1-* 8 9 VSS r w i t h *Pin 8 (VLED1-) is internally connected to Pin 4 (GND1). D e Figure 1. Pin Configuration s a t u Pin Definitions ra t i o Pin # Name Description n D 1 V Non-inverting Gate Drive Control Input IN+ e 2 VIN– Inverting Gate-Drive Control Input te c 3 V Positive Input Supply Voltage (3 V to 5.5 V) t DD1 i o 4 GND1 Input Ground n 5 RESET FAULT Reset Input a n 6 FAULT Fault Output (Open Drain) d I 7 V LED 1 Anode (Do not connect. Leave floating.) s LED1+ o 8 VLED1- LED 1 Cathode (Must be connected to ground.) la t 9 V Output Supply Voltage (Negative) e SS d 10 VSS Output Supply Voltage (Negative) F a 11 VO Gate-Drive Output Voltage u l 12 VS Pull-up PMOS Transistor Source t S 13 V Positive Output Supply Voltage e DD2 n 14 DESAT Desaturation Voltage Input s i n 15 VLED2+ LED 2 Anode (Do not connect. Leave floating.) g 16 V Output Supply Voltage / IGBT Emitter E ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 2

F O Block Diagram D 8 3 VLED1+ 16 7 — 2 . 5 Output IC A VDD1 3 Input IC 13 VDD2 O VIN+ 1 12 VS utp VIN– 2 u FAULT 6 t C OGpatotec oDuripvleer Drive UVLO 11 VO urre LED1 r n t GND1 4 , I G 8 DESAT VLED1– Shield B T 9,10 VSS D 14 DESAT r RESET 5 Fault LED2 16 VE ive O p Fault Sense t Optocoupler o c o Shield u p l 15 e r VLED2+ w i t Figure 2. Functional Block Diagram h D e s a t u r a t i o n D e t e c t i o n a n d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 3

F O Safety and Insulation Ratings D 8 As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit 3 1 data. Compliance with the safety ratings must be ensured by means of protective circuits. 6 — Symbol Parameter Min. Typ. Max. Unit 2 Installation Classifications per DIN VDE 0110/1.89 Table 1 .5 Rated Mains Voltage < 150 V I–IV A RMS O Rated Mains Voltage < 300 V I–IV RMS u t Rated Mains Voltage < 450 V I–IV p RMS u Rated Mains Voltage < 600 V I–IV t RMS C Rated Mains Voltage < 1000 V I–III u RMS r Climatic Classification 40/100/21 re n Pollution Degree (DIN VDE 0110/1.89) 2 t , I CTI Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1) 175 G B VPR Input-to-Output Test Voltage, Method b, VIORM x 1.875 = VPR, 2651 Vpeak T 100% Production Test with tm = 1 s, Partial Discharge < 5 pC D r Input-to-Output Test Voltage, Method a, V x 1.6 = V , 2262 V i IORM PR peak v Type and Sample Test with t = 10 s, Partial Discharge < 5 pC e m O V Maximum Working Insulation Voltage 1414 V IORM peak p t V Highest Allowable Over Voltage 8000 V o IOTM peak c External Creepage 8.0 mm o u External Clearance 8.0 mm p l e Insulation Thickness 0.5 mm r w Safety Limit Values – Maximum Values in Failure; i t h T Case Temperature 150 °C Case D Safety Limit Values – Maximum Values in Failure; e s P Input Power 100 mW a S,INPUT t u Safety Limit Values – Maximum Values in Failure; r a PS,OUTPUT Output Power 600 mW tio R Insulation Resistance at T , V = 500 V 109 Ω n IO S IO D e t e c t i o n a n d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 4

F O Absolute Maximum Ratings D 8 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 3 1 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 6 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. T = 25ºC unless otherwise specified. A 2 . 5 Symbol Parameter Value Units A T Storage Temperature -40 to +125 ºC O STG u TOPR Operating Temperature -40 to +100 ºC tp T Junction Temperature -40 to +125 ºC u J t T Lead Wave Solder Temperature 260 for 10 seconds ºC C SOL (no solder immersion) u r r Refer to reflow temperature profile on page 27. e n I Fault Output Current 15 mA t FAULT , I Peak Output Current(1) 3 A IG O(PEAK) V – V Negative Output Supply Voltage(2) 0 to 15 V B E SS T V – V Positive Output Supply Voltage -0.5 to 35 – (V – V ) V D DD2 E E SS r V Gate Drive Output Voltage -0.5 to 35 V i O(peak) v e VDD2 – VSS Output Supply Voltage -0.5 to 35 V O VDD1 Positive Input Supply Voltage -0.5 to 6 V p t V , V and V Input Voltages -0.5 to V V o IN+ IN- RESET DD1 c V Fault Pin Voltage -0.5 to V V o FAULT DD1 u V Source of Pull-up PMOS Transistor Voltage V + 6.5 to V V p S SS DD2 l e VDESAT DESAT Voltage VE to VE + 11 V r PD Input Power Dissipation(3)(5) 100 mW w I i PD Output Power Dissipation(4)(5) 600 mW th O D Notes: e s 1. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. a 2. This negative output supply voltage is optional. It’s only needed when negative gate drive is implemented. Refer to tu “Dual Supply Operation – Negative Bias at Vss” on page 23. ra t 3. No derating required across temperature range. i o 4. Derate linearly above 64°C, free air temperature at a rate of 10.2 mW/°C n 5. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected D e to conditions outside these ratings. t e c Recommended Operating Conditions t i o n The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended a operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not n recommend exceeding them or designing to absolute maximum ratings. d I s Symbol Parameter Min. Max. Unit o l a T Ambient Operating Temperature -40 +100 ºC t A e V Input Supply Voltage(6) 3 5.5 V d DD1 F VDD2 – VSS Total Output Supply Voltage 15 30 V a u VE – VSS Negative Output Supply Voltage 0 15 V lt V – V Positive Output Supply Voltage(6) 15 30 – (V – V ) V S DD2 E E SS e V Source of Pull-up PMOS Transistor Voltage V + 7.5 V V n S SS DD2 s i Note: n g 6. During power up or down, it is important to ensure that V remains low until both the input and output supply IN+ voltages reaches the proper recommended operating voltages to avoid any momentary instability at the output state. See also the discussion in the “Time to Good Power” section on page 23. ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 5

F O Isolation Characteristics D 8 Apply over all recommended conditions, typical value is measured at T = 25ºC 3 A 1 6 Symbol Parameter Conditions Min. Typ. Max. Units — V Input-Output Isolation T = 25°C, Relative Humidity < 50%, 4,243 V 2 ISO A RMS . Voltage t = 1.0 minute, I ≤ 10 µA, 5 I-O 50 Hz(7)(8)(9) A O R Isolation Resistance V = 500 V(7) 1011 Ω ISO I-O u C Isolation Capacitance V = 0 V, Freq = 1.0 MHz(7) 1 pF tp ISO I-O u t Notes: C 7. Device is considered a two terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. u r 8. 4,243 VRMS for 1-minute duration is equivalent to 5,091 VRMS for 1-second duration. r e 9. The input-output isolation voltage is a dielectric voltage rating as per UL1577. It should not be regarded as an n t input-output continuous voltage rating. For the continuous working voltage rating refer to your equipment-level , I G safety specification or DIN EN/IEC 60747-5-5 Safety and Insulation Ratings Table. B T D Electrical Characteristics r i v Apply over all recommended conditions, typical value is measured at V = 5V, V – V = 30 V, V – V = 0 V, e DD1 DD2 SS E SS and T = 25°C; unless otherwise specified. O A p t Symbol Parameter Conditions Min. Typ. Max. Units Figure o c o V , V , Logic Low Input Voltages 0.8 V IN+L IN-L u VRESETL p l V , V , Logic High Input Voltages 2.0 V e IN+H IN-H r VRESETH w IIN+L, IIN-L, Logic Low Input Currents VIN = 0.4 V -0.5 -0.001 mA ith IRESETL D I FAULT Logic Low Output Current V = 0.4 V 5.0 12.0 mA 3, 34 e FAULTL FAULT s I FAULT Logic High Output Current V = V -40 0.002 µA 34 a FAULTH FAULT DD1 t u I High Level Output Current V = V – 3 V -1 -3 A 4, 9, 35 OH O DD2 r a VO = VDD2 – 6 V(10) -2.5 A ti o IOL Low Level Output Current VO = VSS + 3 V 1 3 A 5, 36 n V = V + 6 V(11) 2.5 A D O SS e I Low Level Output Current During V – V = 14 V 90 185 230 mA 6, 40 t OLF O SS e Fault Condition c t V High Level Output Voltage I = –100 mA(12)(13)(14) V – 1.0 V V – 0.5 V V 7, 9, 37 io OH O S S n VOL Low Level Output Voltage IO = 100 mA 0.1 0.5 V 8, 10, a 37 n d IDD1H High Level Supply Current VIN+ = VDD1 = 5.5 V, 14 17 mA 11, 38 I V = 0 V s IN– o IDD1L Low Level Supply Current VIN+ = VIN- = 0 V, 2 3 mA la VDD1 = 5.5 V te d IDD2H High Level Output Supply Current VO = Open(14) 1 3 mA 12, 13, F I Low Level Output Supply Current V = Open 0.8 2.8 mA 39 a DD2L O u ISH High Level Source Current IO = 0 mA 0.65 1.5 mA 39 lt S ISL Low Level Source Current IO = 0 mA 0.6 1.4 mA 39 e n IEL VE Low Level Supply Current -0.5 -0.2 mA 15, 39 s i I V High Level Supply Current -0.5 -0.25 mA n EH E g I Blanking Capacitor Charge V = 2 V(14)(15) -0.13 -0.25 -0.37 mA 14, 40 CHG DESAT Current ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 6

F O Electrical Characteristics (Continued) D 8 Apply over all recommended conditions, typical value is measured at V = 5 V, V – V = 30 V, V – V = 0V, 3 DD1 DD2 SS E SS 1 and TA = 25°C; unless otherwise specified. 6 — Symbol Parameter Conditions Min. Typ. Max. Units Figure 2 . I Blanking Capacitor V = 7 V 10 36 mA 40 5 DSCHG DESAT Discharge Current A V Under Voltage Lockout V > 5 V @ 25°C 11.5 13.5 V 17, 31, O UVLO+ O Threshold(14) 41 u V V < 5 V @ 25°C 9 10 V t UVLO- O p UVLO Under Voltage Lockout @ 25°C 0.4 1.5 V u HYS t Threshold Hysteresis C V DESAT Threshold(14) V – V > V , 6.0 7.0 9.0 V 18, 40 u DESAT DD2 E ULVO- r V < 5 V r O e n Notes: t , 10.Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. IG 11.Maximum pulse width = 4.99 ms, maximum duty cycle = 99.8%. B T 12.VOH is measured with the DC load current in this testing (Maximum pulse width = 1 ms, maximum duty D cycle = 20%).When driving capacitive loads, V will approach V as I approaches zero units. OH DD OH r i 13.Positive output supply voltage (V – V ) should be at least 15 V to ensure adequate margin in excess of the v DD2 E e maximum under-voltage lockout threshold, V , of 13.5 V. UVLO+ O 14.When V – V > V and output state V is allowed to go high, the DESAT detection feature is active and p DD2 E UVLO O t provides the primary source of IGBT protection. UVLO is needed to ensure DESAT detection is functional. o c 15.The blanking time, tBLANK, is adjustable by an external capacitor (CBLANK), where tBLANK = CBLANK × (VDESAT / ICHG). o u p l e Switching Characteristics r w Apply over all recommended conditions, typical value is measured at V = 5 V, V – V = 30 V, V – V = 0 V, i DD1 DD2 SS E SS t h and T = 25°C; unless otherwise specified. A D e Symbol Parameter Conditions Min. Typ. Max. Units Figure s a tPHL Propagation Delay Time to Rg = 10 Ω, Cg = 10nF, 300 500 ns 19, 20, tu Logic Low Output(17) f = 10 kHz, 21, 22, r a Duty Cycle = 50%(16) 23, 24, t tPLH PLorogpica gHaigtiho nO Duteplauyt( 1T8i)me to 250 500 ns 42, 50 ion D PWD Pulse Width Distortion, 50 300 ns | tPHL – tPLH|(19) ete PDD Skew Propagation Delay Difference –350 350 ns c t Between Any Two Parts or io Channels, ( t – t )(20) n PHL PLH a tR Output Rise Time (10% to 90%) 34 ns 42, 50 n d tF Output Fall Time (90% to 10%) 34 ns I s t DESAT Sense to 90% V Delay(21) Rg = 10 Ω, Cg = 10 nF, 850 ns 25, 43 o DESAT(90%) O l tDESAT(10%) DESAT Sense to 10% VO Delay(21) VDD2 – VSS = 30 V 2 3 µs 26, 28, at e 29, 43 d t DESAT Sense to Low Level FAULT 1.8 5 µs 27, 43, F DESAT(FAULT) Signal Delay(22) 51 au l tDESAT(LOW) DPrEoSpAaTg aStieonns De etola yD(E23S)AT Low 850 ns 43 t S e n tRESET(FAULT) RESET to High Level FAULT Signal 3 6 20 µs 30, 44, s Delay(24) 51 in g PW RESET Signal Pulse Width 1.2 µs RESET ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 7

F O Switching Characteristics (Continued) D 8 Apply over all recommended conditions, typical value is measured at V = 5 V, V – V = 30 V, V – V = 0 V, 3 DD1 DD2 SS E SS 1 and TA = 25°C; unless otherwise specified. 6 — Symbol Parameter Conditions Min. Typ. Max. Units Figure 2 t UVLO Turn On Delay(25) V = 20V in 4 µs 31, 45 .5 UVLO ON DD2 tUVLO OFF UVLO Turn Off Delay(26) 1.0ms Ramp 3 µs A O tGP Time to Good Power(27) VDD2 = 0 to 30V in 30 µs 32, 33, u 10µs Ramp 45 tp u | CMH | Common Mode Transient TA = 25ºC, VDD1 = 5V, 35 50 kV/µs 47, 48 t Immunity at Output High V = 25V, C DD2 u V = Ground, SS r V = 1500Vpk(28) r CM e n | CML | Common Mode Transient TA = 25ºC, VDD1 = 5V, 35 50 kV/µs 46, 49 t Immunity at Output Low VDD2 = 25V, , IG V = Ground, SS B VCM = 1500Vpk(29) T D Notes: r i v 16.This load condition approximates the gate load of a 1200 V / 150 A IGBT. e 17.Propagation delay t is measured from the 50% level on the falling edge of the input pulse (V , V ) to the 50% O PHL IN+ IN- level of the falling edge of the V signal. Refer to Figure 50. p O t o 18. Propagation delay t is measured from the 50% level on the rising edge of the input pulse (V , V ) to the 50% PLH IN+ IN- c level of the rising edge of the V signal. Refer to Figure 50. o O u 19.PWD is defined as | t – t | for any given device. p PHL PLH l 20.The difference between t and t between any two FOD8316 parts under same operating conditions with equal e PHL PLH r loads. w 21.This is the amount of time the DESAT threshold must be exceeded before VO begins to go LOW. This is supply ith voltage dependent. See Figure 51. D 22.This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes LOW. e s See Figure 51. a t 23.The length of time the DESAT threshold must be exceeded before VO begins to go LOW, and the FAULT output u begins to go LOW. See Figure 51. ra t 24.The length of time from when RESET is asserted LOW, until FAULT output goes HIGH. See Figure 51. io 25.The UVLO turn-on delay, t , is measured from V threshold voltage of the output supply voltage (V ) n UVLOON UVLO+ DD2 D to the 5 V level of the rising edge of the V signal. O e 26.The UVLO turn-off delay, t , is measured from V threshold voltage of the output supply voltage (V ) t UVLOOFF UVLO– DD2 e to the 5 V level of the falling edge of the V signal. c O t i 27.The time to good power, t , is measured from 13.5 V level of the rising edge of the output supply voltage (V ) o GP DD2 n to the 5 V level of the rising edge of the V signal. O a 28.Common-mode transient immunity at output HIGH state is the maximum tolerable negative dVCM/dt on the trailing n d edge of the common-mode pulse, V , to assure the output will remain in HIGH state (i.e., V > 15 V or CM O I FAULT > 2 V). s o 29.Common-mode transient immunity at output LOW state is the maximum positive tolerable dVCM/dt on the leading l a edge of the common-mode pulse, V , to assure the output will remain in LOW state (i.e., V < 1.0 V or t CM O e FAULT < 0.8 V). d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 8

F O Typical Performance Characteristics D 8 3 50 7 1 6 ULT CURRENT (mA) 4300 T HIGH CURRENT (A) 6543 VO = VDD2 – 6 V — 2.5 A Ou I – FAFAULTL2100 VVILDIENDD+12 =+= =55 V 1V0 mA I – OUTPUOH 21 VO = VDD2 – 3 V tput Cu TA = 25°C VDD2 – VSS = 30 V r 0 0 VDD1 = 5V re 0 1 2 3 4 5 -40 -20 0 20 40 60 80 100 n VFAULTL – FAULT VOLTAGE (V) TA – TEMPERATURE (°C) t, Figure 3. Fault Logic Low Output Current (IFAULTL) Figure 4. Output High Current (IOH) IG vs. Fault Logic Low Output Voltage (VFAULTL) vs. Temperature B T D 7 225 r ENT (A) 65 CURRENT NS (mA) 210705 TTTAAA === -2145000°°C°CC ive Op I – OUTPUT LOW CURROL 4321 VVDDDD21 –= V5 SVS = 30 V VVOO == VVSSSS ++ 63 VV I – LOW LEVEL OUTPUT OLFDURING FAULT CONDITIO 1115207505050 VVDDDD21 –= V5 SVS = 30 V tocoupler with D 0 25 -40 -20 0 20 40 60 80 100 0 5 10 15 20 25 30 e s TA – TEMPERATURE (°C) VO – OUTPUT VOLTAGE (V) a t Figure 5. Output Low Current (IOL) vs. Figure 6. Low Level Output Current (IOLF) vs. u r Temperature Output Voltage (VO) a t i o V) 0.1 0.25 n P ( D T VOLTAGE DRO -0.01 IIOO == --160500 mμAA VOLTAGE (V) 00..2105 etection TPU -0.2 OW IO = 100 mA a OU T L n (V–V) – HIGH OHDD2 ---000...345-40 VVVDDINDD+21 = -–=2 5 0V5 V SVS = 30 0V 20 40 60 80 100 V – OUTPUOL00..10050-40 VVVDDINDD+21 = -–=2 0 0V5 V SVS = 30 0V 20 40 60 80 100 d Isolated F TA – TEMPERATURE (°C) TA – TEMPERATURE (°C) a u Figure 7. Output High Voltage (VOH–VDD2) Figure 8. Output Low Voltage (VOL) lt vs. Temperature vs. Temperature S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 9

F O Typical Performance Characteristics (Continued) D 8 3 30 5 1 VDD2 – VSS = 30 V 6 UTPUT HIGH VOLTAGE (V) 222987 12050°°CC TA = -40°C UTPUT LOW VOLTAGE (V) 432 VVDIND+1 = = 0 5 V V TA = 100°C 25°C -40°C — 2.5 A Outpu O O V – OH 26 VVDDDD21 –= V5 SVS = 30 V V – OL 1 t Cu 25 VIN+ = 5 V 0 rre 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 n IOH – OUTPUT HIGH CURRENT (A) IOL – OUTPUT LOW CURRENT (A) t, Figure 9. Output High Voltage (VOH) vs. Figure 10. Output Low Voltage (VOL) vs. IG Output High Current (IOH) Output Low Current (IOL) B T D 20 1.4 r i VVDIND+ 1= =5 5V. 5( IVDD1H) or 0 V (IDD1L) mA) ve A) T ( 1.2 O ENT (m 15 IDD1H URREN IDD2H pto LY CURR 10 UPPLY C 1.0 coup I – SUPPDD1 5 IDD1L – OUTPUT SD2 00..86 VVDDDD21 –= V5 SVS = 30 V IDD2L ler with ID VIN+ = 5 V (IDD2H) or 0 V (IDD2L) D 0 0.4 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 e TA – TEMPERATURE (°C) TA – TEMPERATURE (°C) sa t Figure 11. Supply Current (IDD1) Figure 12. Output Supply Current (IDD2) u r vs. Temperature vs. Temperature a t i o n 1.2 -0.15 RENT (mA) 1.0 VVDIND+1 = = 5 5 V V (IDD2H) or 0 VID (DID2HD2L) CHARGING VVVVDDIDNDDE+S21 = A–= T5 V5 =V SV 0S V= t3o0 6 V V Detect PUT SUPPLY CUR 0.8 IDD2L KING CAPACITOR CURRENT (mA) --00..2205 ion and Is UT 0.6 AN o I – ODD2 0.415 20 25 30 I – BLCHG -0.30-40 -20 0 20 40 60 80 100 lated F VDD2 – OUTPUT SUPPLY VOLTAGE (V) TA – TEMPERATURE (°C) au Figure 13. Output Supply Current (IDD2) vs. Figure 14. Blanking Capacitor Charging lt Output Supply Voltage (VDD2) Current (ICHG) vs. Temperature Se n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 10

F O Typical Performance Characteristics (Continued) D 8 3 -0.10 3.0 1 -40°C 6 25°C — -0.15 2.5 100°C mA) mA) 2 NT ( -0.20 IEL NT ( 2.0 .5 E E RR IEH RR A CU -0.25 CU 1.5 O LY CE u I – SUPPE--00..3305 VDD2 – VSS = 30 V I – SOURS 10..05 VDD2 – VSS = 30 V tput C VDD1 = 5 V VDD1 = 5 V u VIN+ = 5 V (IEH) / 0 V (IEL) VIN+ = 5 V r -0.40 0 r -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 e TA – TEMPERATURE (°C) IO – OUTPUT CURRENT (mA) nt Figure 15. Supply Current (IE) vs. Figure 16. Source Current (IS) vs. , IG Temperature Output Current (IO) B T LD (V) 15 8.0 Dr O i H v S e GE LOCKOUT THRE 10 VVUUVVLLOO–+ AT THRESHOLD (V) 77..50 Optocou A S p DER VOLT 5 – DEESAT 6.5 ler w – UNO VVDIND+1 = = 5 5 V V VD VVVDDINDD+21 = =– 5 V5 V SVS = 30 V ith VL 0 6.0 D U -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 V e TA – TEMPERATURE (°C) TA – TEMPERATURE (°C) s a Figure 17. Under Voltage Lockout Figure 18. DESAT Threshold (VDESAT) tu Threshold (VUVLO) vs. Temperature vs. Temperature r a t i o 0.5 0.45 n D 0.40 e μY (s) 0.4 μY (s) 0.35 tec N DELA tPLH N DELA 0.30 tPLH tion GATIO 0.3 tPHL GATIO 0.25 tPHL an PA PA d RO RO 0.20 I P 0.2 P s t – P VVDDDD21 –= V5 SVS = 30 V t – P 0.15 VDD1 = 5 V ol f = 10 kHz 50% Duty Cycle f = 10 kHz 50% Duty Cycle a RL = 10 Ω, CL = 10 nF RL = 10 Ω, CL = 10 nF te 0.1-40 -20 0 20 40 60 80 100 0.1015 20 25 30 d TA – TEMPERATURE (°C) VDD2 – SUPPLY VOLTAGE (V) Fa Figure 19. Propagation Delay (tP) Figure 20. Propagation Delay (tP) vs. u l vs. Temperature Supply Voltage (VDD2) t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 11

F O Typical Performance Characteristics (Continued) D 8 3 0.45 0.35 1 VDD2 – VSS = 30 V VDD2 – VSS = 30 V 6 f = 10 kHz 50% Duty Cycle f = 10 kHz 50% Duty Cycle s) RL = 10 Ω, CL = 10 nF s) RL = 10 Ω, CL = 10 nF — μ μ Y ( 0.40 Y ( 0.30 2 ELA ELA .5 D D N N A ATIO 0.35 ATIO 0.25 O AG AG u ROP ROP tp P P u – PLH 0.30 VDD1 = 4.5 V – PHL 0.20 VDD1 = 4.5 V t C t VVDDDD11 == 55..05 VV t VVDDDD11 == 55..05 VV ur 0.25 0.15 r -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 e TA – TEMPERATURE (°C) TA – TEMPERATURE (°C) nt Figure 21. Propagation Delay Time to Figure 22. Propagation Delay Time to , I G Logic High Output (tPLH) vs. Temperature Logic Low Output (tPHL) vs. Temperature B T D 0.40 0.40 r VDD2 – VSS = 30 V VDD2 – VSS = 30 V iv VDD1 = 5 V VDD1 = 5 V e f = 10 kHz 50% Duty Cycle f = 10 kHz 50% Duty Cycle μY (s) 0.35 RL = 10 Ω μY (s) 0.35 CL = 10 nF Op A A L L t DE tPLH DE tPLH o N N c ATIO 0.30 ATIO 0.30 ou G G p OPA tPHL OPA tPHL le – PR 0.25 – PR 0.25 r w P P t t i t h 0.20 0.20 D 0 20 40 60 80 100 0 10 20 30 40 50 e CL – LOAD CAPACITANCE (nF) RL – LOAD RESISTANCE (Ω) s a Figure 23. Propagation Delay (tP) vs. Figure 24. Propagation Delay (tP) vs. tu Load Capacitance (CL) Load Resistance (RL) ra t i o μLAY (s) 1.2 VVDDDD21 –= V5 SVS = 30 V μAY (s) 3.0 VVDDDD21 –= V5 SVS = 15 or 30 V n D V DEO 1.1 RVILN =+ 1=0 5 Ω V, CL = 10 nF DELO 2.5 VRILN =+ 1=0 5 Ω V, CL = 10 nF ete SE TO 90% 1.0 E TO 10% V 2.0 VDD2 – VSS = 30 V ction N S a SE EN n DESAT 0.9 ESAT S 1.5 VDD2 – VSS = 15 V d Is t – DESAT(90%) 0.8-40 -20 0 TA – T2E0MPERAT4U0RE (°C)60 80 100 t – DDESAT(10%) 1.0-40 -20 0 TA – T2E0MPERAT4U0RE (°C)60 80 100 olated Fa Figure 25. DESAT Sense to 90% Figure 26. DESAT Sense to 10% VO u l VO (tDESAT(90%)) vs. Temperature Delay (tDESAT(10%)) vs. Temperature t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 12

F O Typical Performance Characteristics (Continued) D 8 3 2.6 0.008 1 FAULT VVVDDINDD+21 = –= 5 V5 V SVS = 30 V VVVDDINDD+21 = –= 5 V5 V SVS = 15 V or 30 V 6 — W 2.4 RL = 10 Ω, CL = 10 nF O RL = 10 Ω t – DESAT SENSE TO LODESAT(FAULT)μSIGNAL DELAY (s) 2211....2086-40 -20 0 VE – V2S0S = 0 V 40 VE –6 0VSS = 158 V0 100 t – DESAT SENSE TO 10% VDESAT(10%) 000...00000064200 5 10 15 VDD2 2–0 VSVS D=D 320 – V 2V5SS = 15 V30 2.5 A Output Curre TA – TEMPERATURE (°C) CL – LOAD CAPACITANCE (nF) n t Figure 27. DESAT Sense to Low Fault Signal Figure 28. DESAT Sense to 10% VO , IG Delay (tDESAT(FAULT)) vs. Temperature Delay (tDESAT(10%)) vs. Load Capacitance (CL) B T D μs) 0.0030 10 r – DESAT SENSE TO 10% V DELAY (ODESAT(10%) 0000....000020005211005010VVVCDDILN DD=+21 1= –=0 5 V5n V SFVS = 152 0V or 30 V 30 VDVD4D20D –2 V –S VSS =S 3=0 1 V5 V50 t – RESET TO HIGH LEVEL FAULT RESET(FAULT)μSIGNAL DELAY (s) 987654-40VVRDILN D=+2 1= –0 -5 V2Ω V0S, SC =L 3=V0 1 DV0D0 n1F = 5V.5D DV12 0= 5.0 V 40 VDD601 = 4.5 V80 100 ive Optocoupler with D t e RL – LOAD RESISTANCE (Ω) TA – TEMPERATURE (°C) s a Figure 29. DESAT Sense to 10% VO Figure 30. RESET to High Level FAULT t u Delay (tDESAT(10%)) vs. Load Resistance (RL) Signal Delay (tRESET(FAULT)) vs. Temperature r a t i o n 10 VDD2 = 20 V 100 VDD1 = 5 V D t – UNDER VOLTAGE LOCKOUT UVLOμTHRESHOLD DELAY (s) 8642 VVft R=DIN =D5+ 011 = =Hm 5 z5s ,V V50% Duty CyctUleVLO ONtUVLO OFF μ t – TIME TO GOOD POWER (s)GP 86420000 Vf =IN 5+0 = H 5z ,V 50% Duty Cycle etection and Isolat e 0 0 d -40 -20 0 20 40 60 80 100 15 20 25 30 F TA – TEMPERATURE (°C) VDD2 – SUPPLY VOLTAGE (V) a u Figure 31. Under Voltage Lockout Threshold Figure 32. Time to Good Power (tGP) l t Delay (tUVLO) vs. Temperature vs. Supply Voltage (VDD2) S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 13

F O Typical Performance Characteristics (Continued) D 8 3 120 1 VDD2 = 15 V to 30 V 6 VDD1 = 5 V — μR (s)100 Vf =IN 5+0 = H 5z V50% Duty Cycle 2 POWE 80 .5 A D OO 60 O G O u T t E 40 p – TIMGP 20 ut C t u r 0-40 -20 0 20 40 60 80 100 re n TA – TEMPERATURE (°C) t , Figure 33. Time to Good Power (tGP) IG vs. Temperature B T D r i v e O p t o c o u p l e r w i t h D e s a t u r a t i o n D e t e c t i o n a n d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 14

F O Test Circuits D 8 3 FOD8316 1 1 VIN+ VE 16 A 10 mA 6 — 0.1 μF 5 V +– 0.1 μF 2 VIN– VLED2+ 15 2. 3 VDD1 DESAT 14 5 A 4 GND1 VDD2 13 O VFAULT –+ 5 RESET VS 12 utp 6 FAULT VO 11 u t IFAULT 7 VLED1+ VSS 10 Switch A closed for IFAULTL C u VFAULT = 0.4 V for IFAULTL 8 VLED1-* VSS 9 Switch A opened for IFAULTH rr e VFAULT = 5.0 V for IFAULTH n t *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). , I G B Figure 34. Fault Output Current (I ) and (I ) Test Circuit T FAULTL FAULTH D r FOD8316 i v Pulse Gen 1 VIN+ VE 16 e O PPWeri o=d 1 =0 5μ sms +– 2 VIN– VLED2+ 15 0.1μF +– VE pt 0.1 μF 5 V –+ 3 VDD1 DESAT 14 oc 0.1 μF 47 μF 0.1 μF47 μF o 4 GND1 VDD2 13 u 5 RESET VS 12 +– VO ple + 30 V r 6 FAULT VO 11 – w 3 kΩ i t 7 VLED1+ VSS 10 h D 8 VLED1-* VSS 9 e s a *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). tu r a Figure 35. High Level Output Current (IOH) Test Circuit tio n D FOD8316 e t 1 VIN+ VE 16 e c Pulse Gen PW = 4.99 ms + 2 VIN– VLED2+ 15 0.1 μF +– VE tio Period = 5 ms – 5 V – n 0.1 μF + 3 VDD1 DESAT 14 a n 4 GND1 VDD2 13 d I 5 RESET VS 12 s o 3 kΩ 6 FAULT VO 11 0.1 μF 47 μF +VO +– 30 V late 7 VLED1+ VSS 10 – d F 8 VLED1-* VSS 9 a 0.1 μF 47 μF u l t *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). S e n Figure 36. Low Level Output Current (IOL) Test Circuit s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 15

F O Test Circuits (Continued) D 8 3 1 A FOD8316 6 1 VIN+ VE 16 — B 2 VIN– VLED2+ 15 0.1 μF VE +– 2.5 0.1 μF 5 V +– 3 VDD1 DESAT 14 A O 4 GND1 VDD2 13 100 mA u t 5 RESET VS 12 pulsed p 6 FAULT VO 11 VO BA 0.1 μF 30 V +– ut C 3 kΩ 100 mA u 7 VLED1+ VSS 10 pulsed rr e 8 VLED1-* VSS 9 n SSwwiittcchh AB ffoorr VVOOHL tteesstt t, IG *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). B T Figure 37. High Level (V ) and Low Level (V ) Output Voltage Test Circuit OH OL D r i v A FOD8316 e 1 VIN+ VE 16 O p B t 2 VIN– VLED2+ 15 o c 0.1 μF 5 V +– 3 VDD1 DESAT 14 ou IDD1 p 4 GND1 VDD2 13 le r 5 RESET VS 12 w i 6 FAULT VO 11 th D 7 VLED1+ VSS 10 e s 8 VLED1-* VSS 9 a Switch A for IDD1H test tu Switch B for IDD1L test ra *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). t i o Figure 38. High Level (I ) and Low Level (I ) Supply Current Test Circuit n DD1H DD1L D e t e A FOD8316 IE c 1 VIN+ VE 16 tio B n 2 VIN– VLED2+ 15 0.1 μF VE +– a 5 V + n 0.1 μF – 3 VDD1 DESAT 14 d IDD2 I 4 GND1 VDD2 13 s IS o l 5 RESET VS 12 a VO 30 V + te 6 FAULT VO 11 0.1 μF – d F 7 VLED1+ VSS 10 a u l 8 VLED1-* VSS 9 t S Switch A for IDD2H, ISH and IEH test e Switch B for IDD2L, ISL and IEL test n *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). s i n Figure 39. High Level (IDD2H), Low Level (IDD2L) Output Supply Current, g High Level (I ), Low Level (I ) Source Current, SH SL V High Level (I ), and V Low Level (I ) Supply Current Test Circuit E EH E EL ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 16

F O Test Circuits (Continued) D 8 3 FOD8316 1 6 1 VIN+ VE 16 — VDESAT – 5 V + 2 VIN– VLED2+ 15 ICHG/DSCHG + 0.1 μF VE +– 2.5 0.1 μF – 3 VDD1 DESAT 14 A 4 GND1 VDD2 13 O u 5 RESET VS 12 VRL tp VO RL 30 V + u 3 kΩ 6 FAULT VO 11 IOLF 0.1 μF – t C 7 VLED1+ VSS 10 10 nF u r r 8 VLED1-* VSS 9 en t , *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). IG B Figure 40. Low Level Output Current During Fault Conditions (IOLF), Blanking Capacitor Charge Current (ICHG), T Blanking Capacitor Discharging Current (I ) and DESAT Threshold (V ) Test Circuit D DSCHG DESAT r i v e FOD8316 O 1 VIN+ VE 16 pt o 2 VIN– VLED2+ 15 co 5 V + u 0.1 μF – 3 VDD1 DESAT 14 p l e 4 GND1 VDD2 13 r w 5 RESET VS 12 DC Sweep i VO 0 to 15 V + th 6 FAULT VO 11 0.1 μF (100 steps) – D Parameter e 7 VLED1+ VSS 10 Analyzer s a 8 VLED1-* VSS 9 tu r a t *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). io n Figure 41. Under Voltage Lockout Threshold (V ) Test Circuit D UVLO e t e F = 10 kHz c DC = 50% + FOD8316 ti o – 1 VIN+ VE 16 n a 2 VIN– VLED2+ 15 0.1 μF VE +– n d 0.1 μF 5 V +– 3 VDD1 DESAT 14 Is o 4 GND1 VDD2 13 l a 5 RESET VS 12 VCL te 6 FAULT VO 11 VO 0.1 μF 30 V +– d F 3 kΩ RL a u 7 VLED1+ VSS 10 l 10 nF t S 8 VLED1-* VSS 9 e n s *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). in g Figure 42. Propagation Delay (t , t ), Pulse Width Distortion (PWD), PLH PHL Rise Time (t ) and Fall Time (t ) Test Circuit R F ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 17

F O Test Circuits (Continued) D 8 3 Low to High 1 + FOD8316 6 — – 1 VIN+ VE 16 2 2 VIN– VLED2+ 15 100 pF 0.1 μF VE +– .5 5 V + A 0.1 μF – 3 VDD1 DESAT 14 O 4 GND1 VDD2 13 u t p 5 RESET VS 12 u VO 30 V + t 6 FAULT VO 11 0.1 μF – C 3 kΩ RL u 7 VLED1+ VSS 10 rr VFAULT 10 nF e n 8 VLED1-* VSS 9 t , I G *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). B T Figure 43. DESAT Sense (t , t ), DESAT Fault (t ), and (t ) Test Circuit DESAT(90%) DESAT(10%) DESAT(FAULT) DESAT(LOW) D r i v FOD8316 e 1 VIN+ VE 16 O p 5 V 2 VIN– VLED2+ 15 Strobe 8 V 0.1 μF VE +– toc 0.1 μF +– 3 VDD1 DESAT 14 ou p 4 GND1 VDD2 13 le r 5 RESET VS 12 w 6 FAULT VO 11 VO 0.1 μF 30 V +– ith 3 kΩ RL + D VFAULT – 7 VLED1+ VSS 10 10 nF es 8 VLED1-* VSS 9 a t u r a *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). t i o Figure 44. Reset Delay (t ) Test Circuit n RESET(FAULT) D e t FOD8316 e c 1 VIN+ VE 16 ti o 2 VIN– VLED2+ 15 0.1 μF VE +– n 0.1 μF 5 V +– 3 VDD1 DESAT 14 and 4 GND1 VDD2 13 Is o 5 RESET VS 12 VO la + te 6 FAULT VO 11 0.1 μF VDD2** d 3 kΩ – F 7 VLED1+ VSS 10 a u 8 VLED1-* VSS 9 lt **1.0 ms ramp for tUVLO S 10 μs ramp for tGP e *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). n s i n Figure 45. Under Voltage Lockout Delay (t ) and Time to Good Power (t ) Test Circuit UVLO GP g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 18

F O Test Circuits (Continued) D 8 3 FOD8316 1 6 1 VIN+ VE 16 — 5 V 2 VIN– VLED2+ 15 2. 5 3 VDD1 DESAT 14 25 V A 0.1 μF O 0.1 μF 4 GND1 VDD2 13 u t 1 kΩ 5 RESET VS 12 pu SCOPE t 6 FAULT VO 11 C 10 Ω u 300 pF 7 VLED1+ VSS 10 rr 10nF e n 8 VLED1-* VSS 9 t, I G B T D Floating GND VCM r i *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). v e O Figure 46. Common Mode Low (CM ) Test Circuit @ LED1 Off L p t o c o u FOD8316 p 1 VIN+ VE 16 le r 5 V 2 VIN– VLED2+ 15 w i t h 3 VDD1 DESAT 14 25 V 0.1 μF D e 4 GND1 VDD2 13 s 1 kΩ 0.1 μF a 5 RESET VS 12 tu r a 6 FAULT VO 11 SCOPE t i o 300 pF 7 VLED1+ VSS 10 10 Ω n D 8 VLED1-* VSS 9 10 nF et e c t i o n Floating GND VCM an *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). d I s o Figure 47. Common Mode High (CMH) Test Circuit @ LED1 On la t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 19

F O Test Circuits (Continued) D 8 FOD8316 3 1 1 VIN+ VE 16 6 — 5 V 2 VIN– VLED2+ 15 2 . 3 VDD1 DESAT 14 25 V 5 A 0.1 μF 4 GND1 VDD2 13 O 1 kΩ 0.1 μF u 5 RESET VS 12 tp u SCOPE 6 FAULT VO 11 t C 300 pF 7 VLED1+ VSS 10 10 Ω ur r e 8 VLED1-* VSS 9 10 nF n t , I G B T VCM Floating GND D r *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). iv e Figure 48. Common Mode High (CM ) Test Circuit @ LED2 Off H O p t o c o FOD8316 u 1 VIN+ VE 16 pl e r 5 V 2 VIN– VLED2+ 15 w 3 VDD1 DESAT 14 25 V 750 Ω ith D 0.1 μF 4 GND1 VDD2 13 + 9 V e 1 kΩ 5 RESET VS 12 0.1 μF – sat u SCOPE 6 FAULT VO 11 ra t i 7 VLED1+ VSS 10 10 Ω on 300 pF D 8 VLED1-* VSS 9 10 nF e t e c t i o n VCM Floating GND a n *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). d Figure 49. Common Mode Low (CML) Test Circuit @ LED2 On Is o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 20

F O Timing Diagrams D 8 3 1 6 VIN+ 2.5 V 2.5 V — 2 . 5 VIN– 0V A O tR tF u t p 90% u t C 50% u r r VO 10% en t , I G tPLH tPHL B T D r Figure 50. Propagation Delay (t , t ), Rise Time (t ) and Fall Time (t ) Timing Diagram iv PLH PHL R F e O p t o c o u RESET 50% p l e tDESAT (LOW) r 7 V w i VDESAT tRESET (FAULT) th 50% D e s a tDESAT (90%) tu r 90% a t VO io n 10% D e tDESAT (10%) t e c t i o FAULT 50% (0.5 x VDD1) n a tDESAT (FAULT) nd I s o l Figure 51. Definitions for Fault Reset Input (RESET), Desaturation Voltage Input (DESAT), Output Voltage (V ) a O t e and Fault Output (FAULT) Timing Waveforms d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 21

F O Application Information D 8 3 FOD8316 1 1 VIN+ VE 16 6 ControllerMicro 1 kΩ5 V +– 0.1 μF 23456 VVGRFAIDENNDUS–D1LE1TT DVELVESDDVAVD2OTS+2 1111154321 C1C1 21μμFF C103 μF+– VD11D00200 = pΩ F15D+ VDRVEgFS–AT Q1 +– VCE3-Phase — 2.5 A Outp 330 pF 7 VLED1+ VSS 10 D1 +– VSS = –8 V Q2 + Output ut 8 VLED1- VSS 9 C VCE u *Pin 8 (VLED1-) is internally connected to pin 4 (GND1). – rr e n t Figure 52. Recommended Application Circuit , I G Functional Description B T The typical application circuit is shown in Figure 52 and The relationship between the inputs and output are D the functional behavioral of the FOD8316 is illustrated by illustrated in the Figure 54. r i the detailed internal schematic shown in Figure 53. This v During normal operation, when no fault is detected, the e helps explain the interaction and sequence of internal FAULT output, which is an open-drain configuration, will O and external signals, together with the timing diagrams. be latched to HIGH state. This allows the gate driver to p t 1. Non-Inverting and Inverting Inputs be controlled by the input logic signal. o c There are two CMOS/TTL compatible inputs, V and When a fault is detected, the FAULT output will be o IN+ u V to control the IGBT, in non-inverting and inverting latched to LOW state. This condition will remain until the p IN- configurations respectively. When V is set to LOW, RESET pin is also pulled low for a period longer than le IN- r VIN+ controls the driver output, VO, in non-inverting con- PWRESET. While setting the RESET pin to a low state, w figuration. When VIN+ is set to HIGH, VIN- controls the the input pins must be pulled to low to ensure an output it driver output in inverting configuration. state (VIN+ is low or VIN- is HIGH). h D e s a 250 μA tu r 14 a + DESAT t i – VDESAT o VDD1 3 VLED+ n D VIN+ 1 7 OGpatotec oDurpivleer 16 e VIN– 2 VE te c FAULT 6 UVLO Comp–arator 13 VDD2 tio n 4 + 12 V 12 VS a GND1 n Delay d I s VLED1– 8 Q 11 VO ola R S Fault Sense te 5 Optocoupler 5μs Pulse 50x d RESET Generator F 1x 9,10 VSS au 15 lt S VLED2+ e n s i Figure 53. Detailed Internal Schematic n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 22

F O 2. Gate Driver Output 4. “Soft” Turn-Off D 8 A pair of PMOS and NMOS transistors made up the The soft turn-off feature ensures the safe turn off of the 3 1 output driver stage, which facilitates close to rail-to-rail IGBT under fault condition. This reduces the voltage 6 output swing. This feature allows a tight control of gate spike on the collector of the IGBT. Without this, the IGBT — voltage during on-state and short circuit condition. The would see a heavy spike on the collector, resulting in a 2 output driver is typically capable of sinking 2 A and permanent damage to the device when it’s turned off . 5 sourcing 2 A at room temperature. Due to the low immediately. A RDS(ON) of the MOSFETs, the power dissipation is 5. Under Voltage Lockout (UVLO) O reduced as compared to those bipolar-type driver output u stages. The absolute maximum rating of the output peak Under voltage detection prevents the application of t p current, I is 3 A, thus the careful selection of the insufficient gate voltage to the IGBT. This could be u O(PEAK) dangerous, as it would drive the IGBT out of saturation t gate resistor, Rg, is required to limit the short circuit C and into the linear operation where the losses are very current of the IGBT. u high and quickly overheats. This feature ensures proper r As shown in Figure 53, the gate driver output is influ- operating of the IGBTs. The output voltage, V , remains re enced by signals from the photodetector circuitry, the LOW irregardless of the inputs, as long as Othe supply nt UVLO comparator, and the DESAT signals. Under no voltage, VDD2 – VE, is less than VULVO+. When the , IG fault condition, normal operation resumes while the supply voltage falls below VULVO- , VO goes LOW, as B supply voltage is above the UVLO threshold, the output illustrated in Figure 56. T of the photodetector will drive the MOSFETs of the D output stage. 6. Time to Good Power r i v The logic circuitry of the output stage will ensure that the At initial power up, the LED is off and the output of the e push-pull devices will never be turned “ON” simulta- gate driver should be in the LOW or OFF state. O neously. When the output of the photodetector is HIGH, Sometimes race conditions exist that cause the output to p t the output, VO will be pulled to HIGH state by turning on follow VD (assuming VDD2 and VE are connected oc the PMOS. When the output of the photodetector is externally), until all of the circuits in the output IC have o LOW, V will be pulled to LOW state by turning on the stabilized. This condition can result in output transitions u O p NMOS. or transients that are coupled to the driven IGBT. These l e transients can cause the high- and low-side IGBTs to r When VDD2 supply goes below VUVLO, which is the conduct shoot-through current that can damage power w designated ULVO threshold at the comparator, VO will semiconductor devices. it be pulled down to LOW state regardless of photo- h detector output. Fairchild has introduced an initial turn-on delay, called D “time to good power”. This delay, typically 30 µs, is only e When desaturation is detected, V will turn off slowly as s it is pulled low by the NMOS1X dOevice, the input to the present during the initial power-up of the device. Once at powered, the “time to good power” delay is determined u Fault Sense circuitry will be latched to HIGH state and r by the delay of the UVLO circuitry. If the LED is ON a tNuMrnOs So5n0X thdee viLcEe Dt.u rWnsh eonn VagOa igno, ecsla mbeplionwg t2h eV I,G tBhTe during the initial turn-on activation, low-to-high transition tio at the output of the gate driver will only occur 30 µs after n gate firmly to VSS. The Fault Sense signal will remain the V power is applied. D latched in the HIGH state until the LED of the gate driver DD2 e circuitry turns off. 7. Dual Supply Operation – Negative Bias at VSS te c 3. Desaturation Protection, FAULT Output The IGBT’s off-state noise immunity can be enhanced by t i o providing a negative gate-to-emitter bias when the IGBT Desaturation detection protection ensures the protection n is in the OFF state. This static off-state bias can be of the IGBT at short circuit by monitoring the collector- a supplied by connecting a separate negative voltage n emitter voltage of the IGBT in the half bridge. When the d DESAT voltage goes up and reaches above the source between the VE (pin 16) and VSS (pin 9 &10). I Figure 53 illustrates the two distinct grounds. The s threshold voltage, a short circuit condition is detected o and the driver output stage will execute a “soft” IGBT primary ground reference is the IGBT’s emitter la connection. V (pin 16). The under-voltage threshold t turn-off and will be eventually driven low. This sequence E e and desaturation voltage detection are referenced to the d is illustrated in Figure 55. The FAULT open-drain output IGBT’s emitter (V ) ground. F is triggered active low to report a desaturation error. It E a could only be cleared by activating active low by the The recommended application circuit, Figure 52, shows u l external controller to the RESET input. the interconnection of the VDD2 and VE supplies. The t S The DESAT fault detector should be disabled for a short IGBT’s gate to emitter voltage is the absolute value sum e n of the V supply and the V reverse bias. The time period (blanking time) before the IGBT turns on to DD2 SS s negative voltage supply at V appears at the gate drive i allow the collector voltage to fall below DESAT thresh- SS n input, V , when the FOD8316 is in the LOW state. g old. This blanking period protects against false trigger of O When the input drives the output high, the output the DESAT while the IGBT is turning on. voltage, V , will have the potential of the V and V . O DD2 SS ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 23

F O Figure 52 shows the operation with a dual or split power available output current. C3 is a low ESR 1812 style, D supply. The Vss supply provides the negative gate bias, 10 µF, multilayer ceramic capacitor. This capacitor is the 8 3 and VDD2 + VSS supplies power to the output IC. The primary filter for the Vss and VDD2 supplies. C1 and C2 1 6 V and V supplies require three power supply are also low ESR capacitors. They provide the primary SS DD2 — bypass capacitors. These capacitors provide the low gate charge and discharge paths. The Schottky diode, equivalent series resistant (ESR) paths for the D1, is connected between V and V to protect against 2 E SS . instantaneous gate charging and discharging currents. a reverse voltage greater than 0.5 V. 5 Selecting capacitors with low ESR will optimize the A O u t p u VIN– t C u r r e VIN+ n t , I G B VO T D r i v Figure 54. Input/Output Relationship e O p t o c o Normal Fault Condition Reset u Operation p VIN– le 0 V r w i 5 V th VIN+ 0 V D e s a RESET Blanking tu Time r 7 V a t VDESAT io n D e VO te c t i o n FAULT a n d I s o Figure 55. Timing Relationship Among Desatuation Voltage (DESAT), Fault Output (FAULT) and l a Fault Reset Input (RESET) t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 24

F O D 8 3 1 VIN– 6 — 2 5 V .5 VIN+ 0 V A O u VUVLO+ VUVLO– tp u VDD2 – VE t C u r r e VO n t , I G Figure 56. Under Voltage Lockout (UVLO) for Output Side B T D r i v e O p t o c o u p l e r w i t h D e s a t u r a t i o n D e t e c t i o n a n d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 25

F O Ordering Information D 8 3 Part Number Package Packing Method 1 6 FOD8316 SO 16-Pin Tube (50 units per tube) — FOD8316R2 SO 16-Pin Tape and Reel (750 units per reel) 2 FOD8316V SO 16-Pin, DIN EN/IEC 60747-5-5 option Tube (50 units per tube) .5 A FOD8316R2V SO 16-Pin, DIN EN/IEC 60747-5-5 option Tape and reel (750 units per reel) O u All packages are lead free per JEDEC: J-STD-020B standard. tp u t C u r r Marking Information e n t , I G B T D 1 2 ri v 3 e 8316 V O p t D X YY KK J 8 o c o u p l e r w i t 4 5 6 7 h D e Definitions s a t 1 Fairchild logo u r a 2 Device number, e.g., ‘8316’ for FOD8316 t i o 3 DIN EN/IEC60747-5-5 Option (only appears on n component ordered with this option) D e 4 Plant code, e.g., ‘D’ t e c 5 Last digit year code, e.g., ‘E’ for 2014 t i o 6 Two digit work week ranging from ‘01’ to ‘53’ n 7 Lot traceability code a n 8 Package assembly code, e.g., ‘J’ d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 26

F O Reflow Profile D 8 3 Max. Ramp-up Rate = 3°C/S 1 TP Max. Ramp-down Rate = 6°C/S 6 260 — 240 tP 220 TL 2.5 200 Tsmax A C) 180 Preheat Area tL O u (° 160 Tsmin tp e r 140 u u ts t t 120 C a r u e 100 r p r m 80 e n e T 60 t, I 40 G B 20 T 0 D 120 240 360 r i v Time 25°C to Peak e O Time (seconds) p t o Figure 57. Relow Profile c o u p l e Profile Freature Pb-Free Assembly Profile r w Temperature Minimum (Tsmin) 150°C ith Temperature Maximum (Tsmax) 200°C D e Time (tS) from (Tsmin to Tsmax) 60 to 120 seconds s a Ramp-up Rate (tL to tP) 3°C/second maximum tu Liquidous Temperature (TL) 217°C ra t Time (tL) Maintained Above (TL) 60–150 seconds io n Peak Body Package Temperature 260°C +0°C / –5°C D Time (t ) within 5°C of 260°C 30 seconds e P t e Ramp-Down Rate (T to T ) 6°C/second maximum c P L t i Time 25°C to Peak Temperature 8 minutes maximum o n a n d I s o l a t e d F a u l t S e n s i n g ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8316 Rev. 1.2.1 27

0.20 C A-B 1.27 TYP 0.64 TYP 10.30 2X 16 9 A D 16 9 3 6 1. 1 7 3.75 4 . 9 10.30 1 3 7.50 . 7 (2.16) 0.10 C D 1 8 2X 1 8 0.33 C LAND PATTERN PIN ONE 2X 8 TIPS 1.27 INDICATOR RECOMMENDATION 0.51 (16X) 0.51 TYP B 0.31 0.25 C A-B D A 0.10 C 3.0 MAX 2.35±0.10 0.10 C 16X SEATING PLANE 0.30±0.15 C NOTES: UNLESS OTHERWISE SPECIFIED (1.42) A) DRAWING REFERS TO JEDEC MS-013, (R0.17) VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF GAUGE (R0.17) BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS PLANE 0.25 D) DRAWING CONFORMS TO ASME 8° 0.19 Y14.5M-1994 0° E) LAND PATTERN STANDARD: SOIC127P1030X275-16N 0.25 1.27 F) DRAWING FILE NAME: MKT-M16FREV2 C 0.40 SEATING PLANE SCALE: 3:1

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