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F O D 8 December 2010 0 0 1 — FOD8001 H i g High Noise Immunity, 3.3V/5V Logic Gate Optocoupler h N o i s Features Description e I ■ High Noise Immunity characterized by Common Mode The FOD8001 is a 3.3V/5V high-speed logic gate m m Rejection (CMR) and Power Supply Rejection (PSR) Optocoupler, which supports isolated communications u specifications allowing digital signals to communicate between sys- n – 20kV/µs Minimum Static CMR @ Vcm = 1000V tems without conducting ground loops or hazardous it – 25kV/µs Typical Dynamic CMR @ Vcm = 1500V, vaoglitnagg etesc. hItn uotlioligzye,s O Fpatiorcphlailnda’sr ®p,r oapnrdie otaprtyim ciozpelda nICar d peasicgkn- y, 3 20MBaud Rate to achieve high noise immunity, characterized by high .3V – PSR in excess of 10% of the supply voltages common mode rejection and power supply rejection /5 across full operating bandwidth specifications. V ■ High Speed: L This high-speed logic gate optocoupler, packaged in a o – 25Mbit/sec Date Rate (NRZ) compact 8-pin small outline package, consists of a high- g i – 40ns max. Propagation Delay speed AlGaAs LED driven by a CMOS buffer IC coupled c G – 6ns max. Pulse Width Distortion to a CMOS detector IC. The detector IC comprises an a – 20ns max. Propagation Delay Skew integrated photodiode, a high-speed transimpedance te ■ 3.3V and 5V CMOS Compatibility amplifier and a voltage comparator with an output driver. O The CMOS technology coupled to the high efficiency of p ■ Extended industrial temperate range, -40°C to 105°C the LED achieves low power consumption as well as to temperature range very high speed (40ns propagation delay, 6ns pulse c o ■ Safety and regulatory pending approvals: width distortion). u p – UL1577, 3750 VACRMS for 1 min. l Related Resources e – IEC60747-5-2 (pending) r ■ www.fairchildsemi.com/products/opto/ Applications ■ www.fairchildsemi.com/pf/FO/FOD0721.html ■ Industrial fieldbus communications ■ www.fairchildsemi.com/pf/FO/FOD0720.html – Profibus, DeviceNet, CAN, RS485 ■ www.fairchildsemi.com/pf/FO/FOD0710.html ■ Programmable Logic Control ■ Isolated Data Acquisition System Functional Schematic VDD1 1 8 VDD2 Truth Table VI 2 7 NC V LED V I O H OFF H * 3 6 VO L ON L GND1 4 5 GND2 *: Pin 3 must be left unconnected ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3

F O Pin Definitions D 8 0 Pin Number Pin Name Pin Function Description 0 1 1 VDD1 Input Supply Voltage — 2 VI Input Data H 3 LED Anode – Must be left unconnected ig h 4 GND1 Input Ground N 5 GND2 Output Ground o i 6 V Output Data s O e 7 NC Not Connected Im 8 V Output Supply Voltage m DD2 u n i Absolute Maximum Ratings (T = 25°C Unless otherwise specified.) ty Stresses exceeding the absolute maximumA ratings may damage the device. The device may not function or be , 3 . operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 3 V In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. / 5 The absolute maximum ratings are stress ratings only. V L Symbol Parameter Value Units o g TSTG Storage Temperature -40 to +125 °C ic TOPR Operating Temperature -40 to +105 °C G a TSOL Lead Solder Temperature 260 for 10 sec °C te (Refer to Reflow Temperature Profile) O V , V Supply Voltage 0 to 6.0 V p DD1 DD2 t o V Input Voltage -0.5 to V + 0.5 V I DD1 c o I Input DC Current -10 to +10 µA I u p V Output Voltage -0.5 to V + 0.5 V O DD2 l e I Average Output Current 10 mA r O PD Input Power Dissipation(1)(3) 90 mW I PD Total Power Dissipation(2)(3) 70 mW O Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit T Ambient Operating Temperature -40 +105 °C A V , V Supply Voltages (3.3V Operation)(4) 3.0 3.6 V DD1 DD2 Supply Voltages (5.0V Operation)(4) 4.5 5.5 V Logic High Input Voltage 2.0 V V IH DD V Logic Low Input Voltage 0 0.8 V IL t, t Input Signal Rise and Fall Time 1.0 ms r f Notes: 1.Derate linearly from 25°C at a rate of tbd W/°C 2.Derate linearly from 25°C at a rate of tbd mW/°C. 3.Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings. 4.0.1µF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 2

F O Isolation Characteristics (Apply over all recommended conditions, typical value is measured at T = 25°C) D A 8 0 Symbol Characteristics Test Conditions Min. Typ.* Max. Unit 0 1 V Input-Output Isolation Voltage f = 60Hz, t = 1.0 min, I ≤ 10µA(5)(6) 3750 — — Vac ISO I-O RMS — R Isolation Resistance V = 500V(5) 1011 — — Ω ISO I-O H CISO Isolation Capacitance VI-O = 0V, f = 1.0MHz(5) — 0.2 — pF ig h Notes: N 5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted o i together. s e 6. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration. Im m u n Electrical Characteristics (Apply over all recommended conditions, typical value is measured at it y VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C) , 3 . 3 Symbol Parameter Conditions Min. Typ. Max. Units V / 5 INPUT CHARACTERISTICS V I Logic Low Input Supply V = 0V 6.2 10.0 mA L DD1L I o Current g i I Logic High Input Supply V = V 0.8 3.0 mA c DD1H I DD1 Current G a IIA, IIB Input Current -10 +10 µA te OUTPUT CHARACTERISTICS O p I Logic Low Output Supply V = 0V 4.5 9.0 mA t DD2L I o Current c o I Logic High Output Supply V = V 4.5 9.0 mA u DD2H I DD1 p Current l e V Logic High Output Voltage I = -20µA, V = V , V = +3.3V 2.9 3.3 V r OH O I IH DD2 I = -4mA, V = V , V = +3.3V 1.9 2.9 O I IH DD2 I = -20µA, V = V , V = +5.0V 4.4 5.0 O I IH DD2 I = -4mA, V = V , V = +5.0V 4.0 4.8 O I IH DD2 VOL Logic Low Output Voltage I = 20µA, V = V 0 0.1 V O I IL I = 4mA, V = V 0.3 1.0 O I IL ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 3

F O Switching Characteristics (Apply over all recommended conditions, typical value is measured at D 8 VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25°C) 0 0 Symbol Parameter Test Conditions Min. Typ. Max. Unit 1 — tPHL Propagation Delay Time to CL = 15pF 25 40 ns H Logic Low Output i g t Propagation Delay Time to C = 15pF 25 40 ns h PLH L Logic High Output N o PWD Pulse Width Distortion, PWD = 40ns, C = 15pF 2 6 ns i L s | t – t | e PHL PLH I Data Rate 25 Mb/s m m t Propagation Delay Skew C = 15pF(7) 20 ns PSK L u n t Output Rise Time (10%–90%) 6.5 ns R i t y tF Output Fall Time (90%–10%) 6.5 ns , 3 |CMH| Common Mode Transient VI = VDD1, VO > 0.8 VDD1, 20 40 kV/µs .3 Immunity at Output High V = 1000V(8) V CM / 5 |CML| Common Mode Transient VI = 0V, VO < 0.8V, 20 40 kV/µs V Immunity at Output Low VCM = 1000V(8) L o CPDI Input Dynamic Power 30 pF g Dissipation Capacitance(9) ic G C Output Dynamic Power 3 pF PDO a Dissipation Capacitance(9) t e O Notes: p t 7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any o given temperature within the recommended operating conditions. c o 8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of u p the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity l e at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to r assure that the output will remain low. 9. Unloaded dynamic power dissipation is calculated as follows: C x V x f + I + V where f is switched time in MHz. PD DD DD PD ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 4

F O Typical Performance Curves D 8 0 Figure 1. Typical Output Voltage vs. Input Voltage Figure 2. Input Voltage Switching Threshold vs. Input Supply Voltage 01 4.0 VDD1=VDD2=3.3V 2.0 VDD2=3.3V — 3.5 V) H 3.0 eshold( 1.8 igh V-OutputVoltage(V)O 122...505 nputVoltageSwicthingThr 11..46 Noise Imm 01..50 V-TypicalIITH 1.2 unity, 3 . 3 0.0 1.0 V 0 1 2 3 4 5 3.0 3.5 4.0 4.5 5.0 5.5 / VI-InputVoltage(V) VDD1-InputSupplyVoltage(V) 5V L o Figure 3. Propogation Delay vs. Ambient Temperature Figure 4. Pulse Width Distortion vs. Ambient Temperature g i 32 FDruetqyuCeyncclye==1520.%5MHz 4.0 FDruetqyuCeyncclye==1520.%5MHz c G VDD1=VDD2=3.3V 3.5 VDD1=VDD2=3.3V at 30 e (ns) 3.0 Op Delay(ns) 28 Distortion 2.5 toco t-PropagationP 2246 ttPPHLHL WD-PulseWidth 12..50 upler P 1.0 22 0.5 20 0.0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 TA-AmbientTemperature(°C) TA-AmbientTemperature(°C) Figure 5. Typical Rise Time vs. Ambient Temperature Figure 6. Typical Fall Time vs. Ambient Temperature 7.5 Frequency=12.5MHz 7.5 Frequency=12.5MHz DutyCycle=50% DutyCycle=50% VDD1=VDD2=3.3V 7.0 VDD1=VDD2=3.3V 7.0 6.5 RiseTime(ns) 6.5 FallTime(ns) 56..50 - - tr tf 5.0 6.0 4.5 5.5 4.0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 TA-AmbientTemperature(°C) TA-AmbientTemperature(°C) ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 5

F O Typical Performance Curves (Continued) D 8 0 0 Figure 7. Typical Propogation Delay vs. Output Load Capacitance Figure 8. Typical Width Distortion vs. Output Load Capacitance 1 34 Frequency=12.5MHz 2.6 Frequency=12.5MHz — DVDuDty1=CyVcDleD2==530.%3V 2.4 DVDuDty1=CyVcDlDe2==530.3%V H 32 i g h t-PropagationDelay(ns)P 223680 ttPPHLHL WD-PulseWidthDistortion(ns) 1122....6802 Noise Immun P 1.4 i t 24 y , 1.2 3 . 3 22 1.0 V 15 20 25 30 35 40 45 50 55 15 20 25 30 35 40 45 50 55 /5 CL-OutputLoadCapacitance(pF) CL-OutputLoadCapacitance(pF) V L o g Figure 9. Typical Rise Time vs. Output Load Capacitance Figure 10. Typical Fall Time vs. Output Load Capacitance i c 12 Frequency=12.5MHz 16 Frequency=12.5MHz G DutyCycle=50% DutyCycle=50% 11 VDD1=VDD2=3.3V 14 VDD1=VDD2=3.3V at e O 10 12 p t o me(ns) 9 me(ns) 10 co Ti 8 Ti u t-Riser 7 t-Fallf 8 pler 6 6 4 5 4 2 15 20 25 30 35 40 45 50 55 15 20 25 30 35 40 45 50 55 CL-OutputLoadCapacitance(pF) CL-OutputLoadCapacitance(pF) Figure 11. Input Supply Current vs. Frequency Figure 12. Output Supply Current vs. Frequency 6.5 6.0 VDD1=5.5V VDD1=VDD2=5.5V *Pin6Floating 6.0 5.8 T =25°C InputSupplyCurrent(mA) 455...505 TTTAAA===12-40505°°C°CC OutputSupplyCurrent(mA) 55..46 TTAAA==1-4005°°CC I-DD1 4.0 I-DD2 5.2 3.5 3.0 5.0 0 2000 4000 6000 8000 10000 12000 0 2000 4000 6000 8000 10000 12000 f-Frequency(kHz) f-Frequency(kHz) ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 6

F O Test Circuits D 8 0 0 1 1 8 — 0.1µF H 2 7 0.1µF i V = 3.3V g VDD1 = 3.3V 0V–3.3V DD2 h VO N 3 6 o Pulse width = 40ns CL is Duty Cycle = 50% e 4 5 I m m u n tPLH tPHL it y 3.3V , 3 Input 50% .3 V V IN / 5 V V L Output 90% OH o 50% g VOUT 10% VOL ic t t G R F a t Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time e O p t o c o 1 8 u 0.1µF pl e SW 0.1µF r 2 7 V = 3.3V B DD2 A V O V = 3.3V 3 6 DD1 C L 4 5 + – V CM 1kV VCM GND VOH Switching Pos. (A) V = 3.3V CMH IN 0.8 x V DD 0.8V VOL Switching Pos. (B) VIN = 0V CML Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 7

F O Application Information D 8 0 Noise is defined as any unwanted signal that degrades Test circuit functions were built to interface a commercial 0 or interferes with the operation of a system or circuit. pseudo-random bit sequence (PRBS) generator and 1 Input-output noise rejection is a key characteristic of an error detector with a pair of high speed optocouplers, — optocoupler, and the performance specification for this FOD8001, connected in a loop-back configuration. With H noise rejection is called, “Common Mode Transient a 10MBaud PRBS serial data stream, no error was i g Immunity or Common Mode Rejection, CMR”. The CMR detected until the common mode voltage rose above h test configuration is presented in high speed optocoupler 2.5kV with a dv/dt of 45kV/us. And increasing the data N o datasheets, which tests the optocoupler to a specified rate beyond 10Mbaud, the test was conducted at i s rate of interfering signal (dv/dt), at a specified peak volt- 20MBaud, and no error was detected at dv/dt of 25kV/us e age (Vcm). at common mode voltage of 1.5kV. I m This defined noise signal is applied to the test device The test data for the dynamic CMR is comparable or m while the coupler is a stable logic high or logic low state. better than the static CMR specifications found in the u n This test procedure evaluates the interface device in a datasheet. These excellent noise rejection performances i t constant or static logic state. This type of CMR can be are results of the innovative circuit design and the y referred to as “Static CMR”. Fairchild’s high speed opto- proprietary coplanar assembly process. , 3 . couplers, which use an optically transparent, electrically 3 Power Supply Noise Rejection V conductive shield, and offer active totem pole logic out- / put have static CMR in excess of 50KV/us at peak ampli- High levels of electrical noise can cause the optocoupler 5V tudes of 1.5kV to 2.0kV. to register the incorrect logic state. The most commonly L discussed noise signal is the common mode noise found o Dynamic Common Mode Rejection between the input and output of the optocoupler. How- g i c The noise susceptibility of an interface while it is actively ever, common mode noise is not the only path of noise G transferring data is a common requirement in serial data into the input or output of the optocoupler. Due to the a communication. However, the static CMR specification is high gain and wide bandwidth of the transimpedance t e not adequate in quantifying the electrical noise suscepti- amplifier used for the photo detector circuits, power sup- O bility for optocouplers used in isolating high speed data ply noise can cause the optocoupler to change state p transfer. independent of the LED operation. Power supply noise is to typically characterized as either random or periodic c A serial data communication network’s noise perfor- o pulses with varying amplitudes and rates of rise and fall. u mance is usually quantified as the number of bit errors The necessary tests have been conducted to understand p per second or as a ratio of the number of bits transmitted l the influence of the power supply noise and its effect of e in a specified time frame. This describes Bit Error Rate, r the proper operation of the FOD8001. The optocoupler BER. Test equipment that evaluates BER is called a Bit under test offered power supply noise rejection in excess Error Rate Tester, BERT. When a BERT system is com- of 10% of the supply voltage for a frequency ranging bined with a CMR tester, the active or dynamic noise from 100kHz to 35MHz, for logic high and logic low rejection of an isolated interface can then be quantified. states. This type of CMR is thus defined as “Dynamic CMR”. Therefore, evaluating the common mode rejection while the optocoupler is switching at high speed represents a realistic approach to understand noise interference. ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 8

F O Carrier Tape Specification D 8 0 8.0 ± 0.10 0 1 3.50 ± 0.20 — 2.0 ± 0.05 Ø1.5 MIN H 0.30 MAX 4.0 ± 0.10 1.75 ± 0.10 ig h N o i 5.5 ± 0.05 s e 8.3 ± 0.10 12.0 ± 0.3 Im 5.20 ± 0.20 m u n i t y 0.1 MAX 6.40 ± 0.20 Ø1.5 ± 0.1/-0 , 3 . 3 User Direction of Feed V / Note: 5 V All dimensions are in millimeters. L o g i Ordering Information c G Option Order Entry Identifier Description a t e No Suffix FOD8001 Small outline 8-pin, shipped in tubes (50 units per tube) O p R2 FOD8001R2 Small outline 8-pin, tape and reel (2,500 units per reel) t o c o All packages are lead free per JEDEC: J-STD-020B standard. u p l e r Marking Information 1 8001 2 X YY S1 5 3 4 Definitions 1 Fairchild logo 2 Device number 3 One digit year code, e.g., ‘8’ 4 Two digit work week ranging from ‘01’ to ‘53’ 5 Assembly package code ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 9

F O Reflow Profile D 8 0 0 300 1 280 260°C — 260 H >245°C = 42 Sec 240 ig 220 h 200 N o 180 i s Temperature 160 Time above e (°C) 140 183°C = 90 Sec Im 120 m 100 1.822°C/Sec Ramp up rate u n 80 i t y 60 , 40 3 . 33 Sec 3 20 V 0 /5 0 60 120 180 270 360 V L Time (s) o g i c G a t e O p t o c o u p l e r ©2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD8001 Rev. 1.0.3 10

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