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F O D 3 February 2011 1 8 2 — FOD3182 3 A 3A Output Current, High Speed MOSFET Gate Driver O u t Optocoupler p u t C u Features Applications r r e ■ High noise immunity characterized by 50kV/µs (Typ.) ■ Plasma Display Panel n common mode rejection @ VCM = 2,000V ■ High performance DC/DC convertor t, H ■ Guaranteed operating temperature range of ■ High performance switch mode power supply i g -40°C to +100°C ■ High performance uninterruptible power supply h ■ 3A peak output current ■ Isolated Power MOSFET gate drive S ■ Fast switching speed p e – 210ns max. propagation delay e Description d – 65ns max pulse width distortion M ■ Fast output rise/fall time The FOD3182 is a 3A Output Current, High Speed O – Offers lower dynamic power dissipation MOSFET Gate Drive Optocoupler. It consists of a S ■ 250kHz maximum switching speed aluminium gallium arsenide (AlGaAs) light emitting diode F E ■ Wide VDD operating range: 10V to 30V optically coupled to a CMOS detector with PMOS and T ■ Use of P-Channel MOSFETs at output stage NMOS output power transistors integrated circuit power G enables output voltage swing close to the supply rail stage. It is ideally suited for high frequency driving of a t (rail-to-rail output) power MOSFETS used in Plasma Display Panels e ■ 5000Vrms, 1 minute isolation (PDPs), motor control inverter applications and high D r ■ Under voltage lockout protection (UVLO) with performance DC/DC converters. iv hysteresis – optimized for driving MOSFETs e The device is packaged in an 8-pin dual in-line housing r ■ Minimum creepage distance of 8.0mm compatible with 260°C reflow processes for lead free O ■ Minimum clearance distance of 10mm to 16mm solder compliance. p t (option TV or TSV) o c ■ Minimum insulation thickness of 0.5mm o u ■ UL and VDE* p ■ 1,414 peak working insulation voltage (VIORM) le r *Requires ‘V’ ordering option Functional Block Diagram Package Outlines NC 1 8 V DD 8 8 ANODE 2 7 V O2 1 1 CATHODE 3 6 V O1 NC 4 5 V SS 8 8 1 Note: 1 A 0.1µF bypass capacitor must be connected between pins 5 and 8. ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9

F O Truth Table D 3 1 V –V “Positive Going” V –V “Negative Going” DD SS DD SS 8 LED (Turn-on) (Turn-off) V 2 O — Off 0V to 30V 0V to 30V Low 3 On 0V to 7.4V 0V to 7V Low A O On 7.4V to 9V 7V to 8.5V Transition u On 9V to 30V 8.5V to 30V High tp u t C u r Pin Definitions r e n Pin # Name Description t, H 1 NC Not Connected i g h 2 Anode LED Anode S 3 Cathode LED Cathode p e 4 NC Not Connected e d 5 VSS Negative Supply Voltage M O 6 V Output Voltage 2 (internally connected to V ) O2 O1 S 7 V Output Voltage 1 F O1 E 8 V Positive Supply Voltage T DD G a t e D r i v e r O p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 2

F O Safety and Insulation Ratings D 3 As per DIN EN/IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety 1 limit data. Compliance with the safety ratings shall be ensured by means of protective circuits. 8 2 — Symbol Parameter Min. Typ. Max. Unit 3 Installation Classifications per DIN VDE 0110/1.89 Table 1 A For Rated Mains Voltage < 150Vrms I–IV O u For Rated Mains Voltage < 300Vrms I–IV t p For Rated Mains Voltage < 450Vrms I–III u t For Rated Mains Voltage < 600Vrms I–III C u For Rated Mains Voltage < 1000Vrms (Option T, TS) I–III r r e Climatic Classification 40/100/21 n t Pollution Degree (DIN VDE 0110/1.89) 2 , H i CTI Comparative Tracking Index 175 g h VPR Input to Output Test Voltage, Method b, 2651 S V x 1.875 = V , 100% Production Test with p IORM PR e tm = 1 sec., Partial Discharge < 5pC e d Input to Output Test Voltage, Method a, 2121 M V x 1.5 = V , Type and Sample Test with IORM PR O tm = 60 sec.,Partial Discharge < 5 pC S F VIORM Max Working Insulation Voltage 1,414 Vpeak E T VIOTM Highest Allowable Over Voltage 6000 Vpeak G External Creepage 8 mm a t e External Clearance 7.4 mm D External Clearance (for Option T or TS - 0.4” Lead Spacing) 10.16 mm r i v Insulation Thickness 0.5 mm e r Safety Limit Values – Maximum Values Allowed in the O p Event of a Failure t o T Case Temperature 150 °C c Case o I Input Current 25 mA u S,INPUT p PS,OUTPUT Output Power (Duty Factor ≤ 2.7%) 250 mW le r R Insulation Resistance at T , V = 500V 109 Ω IO S IO ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 3

F O Absolute Maximum Ratings (T = 25°C unless otherwise specified) D A 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 1 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 8 2 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. 3 A Symbol Parameter Value Units O u T Storage Temperature -40 to +125 °C STG t p T Operating Temperature -40 to +100 °C u OPR t T Junction Temperature -40 to +125 °C C J u T Lead Solder Temperature – Wave solder 260 for 10 sec. °C r SOL r (Refer to Reflow Temperature Profile, pg. 22) e n IF(AVG) Average Input Current(1) 25 mA t, H IF(tr, tf) LED Current Minimum Rate of Rise/Fall 250 ns ig V Reverse Input Voltage 5 V h R S IOH(PEAK) “High” Peak Output Current(2) 3 A p e I “Low” Peak Output Current(2) 3 A e OL(PEAK) d VDD – VSS Supply Voltage -0.5 to 35 V M V Output Voltage 0 to V V O O(PEAK) DD S P Output Power Dissipation(4) 250 mW F O E P Total Power Dissipation(5) 295 mW T D G a t e Recommended Operating Conditions D The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended r i v operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not e recommend exceeding them or designing to absolute maximum ratings. r O p Symbol Parameter Value Units t o c VDD – VSS Power Supply 10 to 30 V o u IF(ON) Input Current (ON) 10 to 16 mA p l e V Input Voltage (OFF) -3.0 to 0.8 V F(OFF) r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 4

F O Electrical-Optical Characteristics (DC) D 3 Apply over all recommended conditions, typical value is measured at VDD = 30V, VSS = 0V, TA = 25°C, 1 unless otherwise specified. 8 2 — Symbol Parameter Test Conditions Min. Typ. Max. Unit 3 IOH High Level Output Current VOH = (VDD – VSS – 1V) 0.5 0.9 A A V = (V – V – 6V) 2.5 O OH DD SS u IOL Low Level Output Current VOL = (VDD – VSS + 1V) 0.5 1 A tp V = (V – V + 6V) 2.5 u OL DD SS t V High Level Output Voltage(5)(6) I = -100mA V – 0.5 V C OH O DD u VOL Low Level Output Voltage(5)(6) IO = 100mA VSS + 0.5 V rr e I High Level Supply Current Output Open, 2.6 4.0 mA n DDH t IF = 10 to 16mA , H IDDL Low Level Supply Current Output Open, 2.5 4.0 mA ig V = -3.0 to 0.8V h F S IFLH Threshold Input Current Low to IO = 0mA, VO > 5V 3.0 7.5 mA p High e e V Threshold Input Voltage High to Low I = 0mA, V < 5V 0.8 V d FHL O O M VF Input Forward Voltage IF = 10mA 1.1 1.43 1.8 V O ∆V /T Temperature Coefficient of Forward I = 10mA -1.5 mV/°C S F A F F Voltage E T VUVLO+ UVLO Threshold VO > 5V, IF = 10mA 7 8.3 9 V G V V < 5V, I = 10mA 6.5 7.7 8.5 V a UVLO– O F t e UVLOHYST UVLO Hysteresis 0.6 V D BV Input Reverse Breakdown Voltage I = 10µA 5 V r R R i v C Input Capacitance f = 1MHz, V = 0V 25 pF e IN F r O p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 5

F O Switching Characteristics D 3 Apply over all recommended conditions, typical value is measured at VDD = 30V, VSS = 0V, TA = 25°C, 1 unless otherwise specified. 8 2 — Symbol Parameter Test Conditions Min. Typ. Max. Unit 3 t Propagation Delay Time to High Output Level(7) I = 10mA, 50 120 210 ns A PLH F t Propagation Delay Time to Low Output Level(7) Rg = 10Ω, 50 145 210 ns O PHL f = 250kHz, u PWD Pulse Width Distortion(8) Duty Cycle = 50%, 35 65 ns tp u PDD Propagation Delay Difference Between Any Cg = 10nF -90 90 ns t (t – t ) Two Parts(9) C PHL PLH u tr Rise Time CL = 10nF, 38 ns rr R = 10Ω e t Fall Time g 24 ns n f t tUVLO ON UVLO Turn On Delay 2.0 µs , H i t UVLO Turn Off Delay 0.3 µs g UVLO OFF h | CMH | Output High Level Common Mode Transient TA = +25°C, 35 50 kV/µs S Immunity(10) (11) I = 7mA to 16mA, p f e VCM = 2kV, e V = 30V d DD M | CML | Output Low Level Common Mode Transient TA = +25°C, 35 50 kV/µs O Immunity(10) (12) Vf = 0V, S V = 2kV, F CM E VDD = 30V T G a t e D r i Isolation Characteristics v e r Symbol Parameter Test Conditions Min. Typ.* Max. Unit O p VISO Withstand Isolation Voltage(13) (14) TA = 25°C, 5000 Vrms to R.H. < 50%, t = 1min., c o I ≤ 10µA u I-O p R Resistance (input to output)(14) V = 500V 1011 Ω l I-O I-O e r C Capacitance (input to output) Freq. = 1MHz 1 pF I-O *Typical values at T = 25°C A ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 6

F O Notes: D 3 1. Derate linearly above +79°C free air temperature at a rate of 0.37mA/°C. 1 8 2. Maximum pulse width = 10µs, maximum duty cycle = 11%. 2 3 Derate linearly above +79°C, free air temperature at the rate of 5.73mW/°C. — 4. No derating required across operating temperature range. 3 A 5. In this test, V is measured with a dc load current of 100mA. When driving capacitive load V will approach V OH OH DD O as I approaches zero amps. OH u 6. Maximum pulse width = 1ms, maximum duty cycle = 20%. tp u 7. t propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the PHL t falling edge of the V signal. t propagation delay is measured from the 50% level on the rising edge of the input C O PLH u pulse to the 50% level of the rising edge of the VO signal. rr e 8. PWD is defined as | tPHL – tPLH | for any given device. n t 8. The difference between tPHL and tPLH between any two FOD3182 parts under same operating conditions, with , H equal loads. i g 10. Pin 1 and 4 need to be connected to LED common. h 11. Common mode transient immunity in the high state is the maximum tolerable dV /dt of the common mode pulse S CM p V to assure that the output will remain in the high state (i.e. V > 15V). e CM O e 12. Common mode transient immunity in a low state is the maximum tolerable dV /dt of the common mode pulse, d CM M V , to assure that the output will remain in a low state (i.e. V < 1.0V). CM O O 13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000Vrms, S 60Hz for 1 second (leakage detection current limit I < 10µA). F I-O E 14. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted T together. G a t e D r i v e r O p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 7

F O Typical Performance Curves D 3 1 Fig. 1 Output High Voltage Drop vs. Output High Current Fig. 2 Output High Voltage Drop vs. Ambient Temperature 8 V) 0.5 V) 0.00 2 AGE DROP ( -0.05 FDIVVFrDSu e=SDtqy 1u ==C0e 01mynVc5cAlVye t =to=o 2 10306.010mV%HAz AGE DROP ( -0.05 VVIIFODS ==SD 1=-=10 001mV05AmV tAtoo 1360mVA — 3A O LT LT -0.10 u PUT VO --11..05 TA = -40°C PUT VO -0.15 tput UT UT C HIGH O -2.0 TA =100°C TA = 25°C HIGH O -0.20 urre – -2.5 – n - V) HDD -3.-0 - V) HDD -0.25 t, Hi O O g (V -3.5 (V -0.30 h 0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 S IOH – OUTPUT HIGH CURRENT (A) TA – AMBIENT TEMPERATURE (°C) p e e Fig. 3 Output High Current vs. Ambient Temperature Fig. 4 Output High Current vs. Ambient Temperature d M 8 8 O Frequency = 200Hz Frequency = 100Hz Duty Cycle = 0.2% Duty Cycle = 0.5% S T (A) IVFD =D 1=0 1m5AV ttoo 1360mVA T (A) IVFD =D 1=0 1m5AV ttoo 1360mVA FE EN 6 EN 6 T R R R R G U U C C a HIGH 4 VO = 6V HIGH 4 VO = 6V te D TPUT VO = 3V TPUT VO = 3V riv U U e O O r – H 2 – H 2 O IO IO p t o c 0 0 o -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 u TA – AMBIENT TEMPERATURE (°C) TA – AMBIENT TEMPERATURE (°C) p l e r Fig. 5 Output Low Voltage vs. Output Low Current Fig. 6 Output Low Voltage vs. Ambient Temperature 4 0.30 GE (V) 3 FDVVVrFDSue(SDtqoy u =f=Cfe) 0 1yn=Vc5c l0Vye. 8=t=oV 2 930900.V9H%z GE (V) 0.25 VVVIODSF =SD= =1=-0 3 010VV5m VtoA t0o. 83V0V OLTA TA =100°C TA = 25°C OLTA 0.20 V V W W UT LO 2 UT LO 0.15 P P UT UT 0.10 V – OOL 1 TA = -40°C V – OOL 0.05 0 0 0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 IOL – OUTPUT LOW CURRENT (A) TA – AMBIENT TEMPERATURE (°C) ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 8

F O Typical Performance Curves (Continued) D 3 1 Fig. 7 Output Low Current vs. Ambient Temperature Fig. 8 Output Low Current vs. Ambient Temperature 8 2 8 8 — Frequency = 200Hz Frequency = 100Hz Duty Cycle = 99.8% Duty Cycle = 99.5% 3 A) VF = 0.8V A) VF = 0.8V A T ( VDD = 15V to 30V T ( VDD = 15V to 30V N 6 N 6 O E E R R u UR VO = 6V UR tp W C W C VO = 6V u O 4 O 4 t L L C PUT VO = 3V PUT VO = 3V ur OUT OUT re – 2 – 2 n I OL I OL t, H i g 0 0 h -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 S TA – AMBIENT TEMPERATURE (°C) TA – AMBIENT TEMPERATURE (°C) p e e d Fig. 9 Supply Current vs. Ambient Temperature Fig. 10 Supply Current vs. Supply Voltage M 3.6 3.6 O NT (mA) 33..42 VVIIFFDS ==SD 01==m0 01mAV5A V( f (otforo rI3D I0DDVDL)H ) NT (mA) 3.2 IIVTFFAS == S= 01 =2m0 50mA°VCA ( f(ofro rID IDDDL)H ) SFET G RE IDDH(30V) RE a UR 3.0 UR te I – SUPPLY CDD 222...864 IDDL(30V) IIDDDDLH((1155VV)) I – SUPPLY CDD 22..84 IIDDDDHL Driver Opt o c 2.2 2.0 o -40 -20 0 20 40 60 80 100 15 20 25 30 u p TA – AMBIENT TEMPERATURE (°C) VDD – SUPPLY VOLTAGE (V) l e r Fig. 11 Low-to-High Input Current Threshold mA) vs. Ambient Temperature Fig. 12 Propagation Delay vs. Supply Voltage T THRESHOLD ( 333...642 VVODSuSDtp ==u t 0 1=V5 VO ptoe n30V LAY (ns) 225000 RITCDFFAruGG e= t =qy ==1 u 2C011e5my00n°cΩncCAlFye t =o= 2155600m%kAHz N E E D CURR 3.0 TION 150 H INPUT 2.8 ROPAGA ttPPLHHL G 2.6 P o-HI t – P100 W-t 2.4 O L – H 2.2 50 FL -40 -20 0 20 40 60 80 100 15 18 21 24 27 30 I TA – AMBIENT TEMPERATURE (°C) VDD – SUPPLY VOLTAGE (V) ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 9

F O Typical Performance Curves (Continued) D 3 1 8 Fig. 13 Propagation Delay vs. LED Forward Current Fig. 14 Propagation Delay vs. Ambient Temperature 2 250 450 — ELAY (ns) 200 CDFVTRArDuGGe Dt =qy== u= 2C11e 51y00n°c5ΩncClVFye =t=o 2 535000%VkHz ELAY (ns) 350 IVRCDFFrDuGG e=Dt qy == 1 u= C011e 1my00nc5ΩncAlVFye t =to=o 2 15356000m%VkAHz 3A Out D D p N N u ATIO 150 ATIO 250 t C AG tPHL AG u P P r O O r t – PRP100 tPLH t – PRP 150 ttPPHLLH ent, H i g h 50 50 6 8 10 12 14 18 -40 -20 0 20 40 60 80 100 S p IF – FORWARD LED CURRENT (mA) TA – AMBIENT TEMPERATURE (°C) e e d Fig. 15 Propagation Delay vs. Series Load Resistance Fig. 16 Propagation Delay vs. Series Load Capacitance M 450 450 O IVFD =D 1=0 1m5AV ttoo 1360mVA IVFD =D 1=0 1m5AV ttoo 1360mVA S CG = 10nF RG = 10Ω F s) Duty Cycle = 50% s) Duty Cycle = 50% E Y (n 350 Frequency = 250kHz Y (n 350 Frequency = 250kHz T A A G L L E E a D D N N te TIO 250 TIO 250 D A A G G r A A iv P P O O e R R r – P 150 tPHL – P 150 tPHL O t P t P p tPLH tPLH to c o 50 50 u 0 10 20 30 40 50 0 20 40 60 80 100 p RG – SERIES LOAD RESISTANCE (Ω) CG – SERIES LOAD CAPACITANCE (nF) le r Fig. 17 Transfer Characteristics Fig. 18 Input Forward Current vs. Forward Voltage 35 100 VDD = 30V TA = 25°C 30 A) 10 OLTAGE (V) 2250 URRENT (m 1 V C T E U R TP 15 WA 0.1 TA =100°C 25°C -40°C OU OR – 10 F O – V I F 0.01 5 0 0.001 0 1 2 3 4 5 0.6 0.8 1.0 1.2 1.4 1.6 1.8 IF – FORWARD LED CURRENT (mA) VR – FORWARE VOLTAGE (V) ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 10

F O Typical Performance Curves (Continued) D 3 1 8 Fig. 19 Under Voltage Lockout 2 20 — 18 3 A V) 16 O GE ( 14 ut A p LT 12 u VO t T 10 C PU u T 8 (8.30V) r U r O e V – O 64 nt, H i 2 g (7.80) h 0 S 0 5 10 15 20 p (VDD – VSS) – SUPPLY VOLTAGE (V) e e d M O S F E T G a t e D r i v e r O p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 11

F O Test Circuit D 3 1 8 2 Power Supply + — C0.11µF + C472µF VDD = 10V to 30V 3A O Pulse Generator u 1 8 t PW = 4.99ms p Period = 5ms Pulse-In u ROUT = 50Ω 2 7 t C u R1020Ω Iol Power Supply rr 3 6 + e LED-IFmon VOL D1 C0.31µF + C474µF V = 6V nt, 4 5 H i g R1 h 100Ω To Scope S p Test Conditions: e Frequency = 200Hz e d Duty Cycle = 99.8% VDD = 10V to 30V M VSS = 0V O VF(OFF) = -3.0V to 0.8V S F E Figure 20. I Test Circuit OL T G a t e D Power Supply r + iv C1 + C2 VDD = 10V to 30V e 0.1µF 47µF r O p Pulse Generator t o PW = 10µs 1 8 c Period = 5ms o R = 50Ω Pulse-In u OUT 2 7 + Power Supply p C3 + C4 le R2 Ioh 0.1µF 47µF V = 6V r 100Ω 3 6 – LED-IFmon VOH D1 Current 4 5 Probe To Scope R1 100Ω Test Conditions: Frequency = 200Hz Duty Cycle = 0.2% VDD = 10V to 30V VSS = 0V IF = 10mA to 16mA Figure 21. I Test Circuit OH ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 12

F O Test Circuit (Continued) D 3 1 8 2 — 1 8 3 A 2 7 0.1µF O + u IF = 10 to 16mA – VDD = 10 to 30V tp u 3 6 VO t C 100mA u r 4 5 r e n t , H Figure 22. V Test Circuit i OH g h S p e e 1 8 d M O 100mA 2 7 S 0.1µF + F – VDD = 10 to 30V E T 3 6 VO G a t e 4 5 D r i v e r O Figure 23. VOL Test Circuit p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 13

F O Test Circuit (Continued) D 3 1 8 2 1 8 — 3 A 2 7 0.1µF O + IF = 10 to 16mA – VDD = 30V u t p 3 6 VO u t C u 4 5 r r e n t , H Figure 24. IDDH Test Circuit ig h S p e 1 8 e d M 2 7 0.1µF O + + S – VF = -0.3 to 0.8V – VDD = 30V F E 3 6 VO T G a t 4 5 e D r i v e Figure 25. IDDL Test Circuit r O p t o c o u p l e r ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 14

F O Test Circuit (Continued) D 3 1 8 2 — 1 8 3 A 2 7 0.1µF O + u – VDD = 10 to 30V t p IF 3 6 VO > 5V ut C u 4 5 rr e n t , H Figure 26. IFLH Test Circuit ig h S p e 1 8 e d M 2 7 0.1µF O + + S – VF = –0.3 to 0.8V – VDD = 10 to 30V F E 3 6 VO T G a t 4 5 e D r i v e Figure 27. VFHL Test Circuit r O p t o c 1 8 o u p l 2 7 0.1µF er + IF = 10mA – 10V or 30V VDD Ramp 3 6 VO = 5V 4 5 Figure 28. UVLO Test Circuit ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 15

F O Test Circuit (Continued) D 3 1 8 2 1 8 — 0.1µF 3 + 2 7 VO +– VDD = 10 to 30V A O – u F = 250kHz Probe 3 6 Rg = 10Ω tp DC = 50% u Cg = 10nF 50Ω t 4 5 C u r r e n t , H i IF g h S tr tf p e e 90% d 50% M O VOUT 10% S F E tPLH tPHL T G Figure 29. t , t , t and t Test Circuit and Waveforms a PHL PLH r f t e D r i v IF 1 8 er O A p 2 7 0.1µF t B +– VDD = 30V oc o 5V +– 3 6 VO u p l e 4 5 r + – VCM = 2,000V VCM 0V ∆t VO VOH Switch at A: IF = 10mA VO VOL Switch at B: IF = 0mA Figure 30. CMR Test Circuit and Waveforms ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 16

F O Ordering Information D 3 1 Part Number Package Packing Method 8 2 FOD3182 DIP 8-Pin Tube (50 units per tube) — FOD3182S SMT 8-Pin (Lead Bend) Tube (50 units per tube) 3 A FOD3182SD SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units per reel) O FOD3182V DIP 8-Pin, IEC60747-5-2 option Tube (50 units per tube) u t FOD3182SV SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-2 option Tube (50 units per tube) p u FOD3182SDV SMT 8-Pin (Lead Bend), DIN EN/IEC 60747-5-2 option Tape and Reel (1,000 units per reel) t C FOD3182TV DIP 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-2 option Tube (50 units per tube) u r FOD3182TSV SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-2 option Tube (50 units per tube) r e n FOD3182TSR2 SMT 8-Pin, 0.4” Lead Spacing Tape and Reel (700 units per reel) t , FOD3182TSR2V SMT 8-Pin, 0.4” Lead Spacing, DIN EN/IEC 60747-5-2 option Tape and Reel (700 units per reel) H i g h S p e e d Marking Information M O S F E T G 1 a t e D 3182 2 r i v e V XX YY B 6 r O p t o c 3 4 5 o u p l e r Definitions 1 Fairchild logo 2 Device number 3 VDE mark (Note: Only appears on parts ordered with DIN EN/IEC 60747-5-2 option – See order entry table) 4 Two digit year code, e.g., ‘11’ 5 Two digit work week ranging from ‘01’ to ‘53’ 6 Assembly package code ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 17

F O Carrier Tape Specifications – Option S D 3 1 D 8 0 2 P0 P2 — t E K 0 3 A O u F t p A 0 u W1 B0 W t C u r r e n t UserDirectionofFeed P , H d D 1 i g h S Symbol Description Dimension in mm p e e W Tape Width 16.0 ± 0.3 d t Tape Thickness 0.30 ± 0.05 M O P0 Sprocket Hole Pitch 4.0 ± 0.1 S F D0 Sprocket Hole Diameter 1.55 ± 0.05 E T E Sprocket Hole Location 1.75 ± 0.10 G F Pocket Location 7.5 ± 0.1 a t e P2 2.0 ± 0.1 D P Pocket Pitch 12.0 ± 0.1 r i v A Pocket Dimensions 10.30 ±0.20 e 0 r B 10.30 ±0.20 O 0 p K 4.90 ±0.20 t 0 o c W Cover Tape Width 13.2 ± 0.2 1 o u d Cover Tape Thickness 0.1 max p l Max. Component Rotation or Tilt 10° e r R Min. Bending Radius 30 ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 18

F O Carrier Tape Specifications – Option TS D 3 1 D 8 0 2 P0 P2 — t E K 0 3 A O u F t p A 0 u W1 B0 W t C u r r e n t UserDirectionofFeed P , H d D 1 i g h S Symbol Description Dimension in mm p e e W Tape Width 24.0 ± 0.3 d t Tape Thickness 0.40 ± 0.1 M O P0 Sprocket Hole Pitch 4.0 ± 0.1 S F D0 Sprocket Hole Diameter 1.55 ± 0.05 E T E Sprocket Hole Location 1.75 ± 0.10 G F Pocket Location 11.5 ± 0.1 a t e P2 2.0 ± 0.1 D P Pocket Pitch 16.0 ± 0.1 r i v A Pocket Dimensions 12.80 ± 0.1 e 0 r B 10.35 ± 0.1 O 0 p K 5.7 ±0.1 t 0 o c W Cover Tape Width 21.0 ± 0.1 1 o u d Cover Tape Thickness 0.1 max p l Max. Component Rotation or Tilt 10° e r R Min. Bending Radius 30 ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 19

F O Reflow Profile D 3 1 Max. Ramp-up Rate = 3°C/S 8 TP Max. Ramp-down Rate = 6°C/S 2 260 — 240 tP TL 3 220 A 200 Tsmax O tL u C) 180 Preheat Area t p °e ( 160 Tsmin ut ur 140 ts C t 120 u a r r r e 100 e p n m 80 t Te 60 , H i 40 g h 20 S p 0 e 120 240 360 e d Time 25°C to Peak M Time (seconds) O S F E T G Profile Freature Pb-Free Assembly Profile a t Temperature Min. (Tsmin) 150°C e D Temperature Max. (Tsmax) 200°C r i v Time (tS) from (Tsmin to Tsmax) 60–120 seconds e r Ramp-up Rate (tL to tP) 3°C/second max. O p Liquidous Temperature (T ) 217°C L t o Time (t ) Maintained Above (T ) 60–150 seconds c L L o Peak Body Package Temperature 260°C +0°C / –5°C u p Time (tP) within 5°C of 260°C 30 seconds le r Ramp-down Rate (T to T ) 6°C/second max. P L Time 25°C to Peak Temperature 8 minutes max. ©2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3182 Rev. 1.0.9 20

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