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F O D 3 February 2016 1 2 0 — FOD3120 H i g High Noise Immunity, 2.5 A Output Current, h N o Gate Drive Optocoupler i s e I m Features Description m • High Noise Immunity Characterized by 35 kV/μs The FOD3120 is a 2.5 A Output Current Gate Drive u n Minimum Common Mode Rejection Optocoupler, capable of driving most medium power i t • 2.5 A Peak Output Current Driving Capability for Most IGBT/MOSFET. It is ideally suited for fast switching y, 1200 V/20 A IGBT driving of power IGBT and MOSFETs used in motor 2 . • Use of P-channel MOSFETs at Output Stage Enables control inverter applications, and high performance 5 A Output Voltage Swing Close to The Supply Rail power system. O • Wide Supply Voltage Range from 15 V to 30 V It utilizes Fairchild’s coplanar packaging technology, u • Fast Switching Speed Optoplanar®, and optimized IC design to achieve high tp – 400 ns max. Propagation Delay noise immunity, characterized by high common mode u t – 100 ns max. Pulse Width Distortion rejection. C • Under Voltage LockOut (UVLO) with Hysteresis u It consists of a gallium aluminum arsenide (AlGaAs) light r • Extended Industrial Temperate Range, emitting diode optically coupled to an integrated circuit re -40°C to 100°C Temperature Range with a high-speed driver for push-pull MOSFET output n t • Safety and Regulatory Approved stage. , G – UL1577, 5000 VRMS for 1 min. a t – DIN EN/IEC60747-5-5 e • R of 1 Ω (typ.) Offers Lower Power Dissipation Related Resources D DS(ON) r • >8.0 mm Clearance and Creepage Distance i v (Option ‘T’ or ‘TS’) • FOD3150, 1 A Output Current, Gate Drive e Optocoupler Datasheet O • 1,414 V Peak Working Insulation Voltage (V ) IORM • www.fairchildsemi.com/products/optoelectronics/ p t Applications o c o • Industrial Inverter u • Uninterruptible Power Supply p l e • Induction Heating r • Isolated IGBT/Power MOSFET Gate Drive Functional Block Diagram Package Outlines NC 1 8 V DD 8 8 ANODE 2 7 VO2 1 1 CATHODE 3 6 VO1 NC 4 5 V 8 SS 8 1 Figure 1. Functional Block Diagram(1) 1 Figure 2. Package Outlines Note: 1. 0.1 μF bypass capacitor must be connected between pins 5 and 8. ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4

F O Truth Table D 3 1 LED VDD–VSS “Positive Going” VDD–VSS “Negative Going” V 2 (Turn-on) (Turn-off) O 0 — Off 0 V to 30 V 0 V to 30 V Low H On 0 V to 11.5 V 0 V to 10 V Low i g h On 11.5 V to 13.5 V 10 V to 12 V Transition N On 13.5 V to 30 V 12 V to 30 V High o i s e I m Pin Definitions m u n Pin # Name Description i t y 1 NC Not Connected , 2 2 Anode LED Anode .5 A 3 Cathode LED Cathode O 4 NC Not Connected u t 5 V Negative Supply Voltage p SS u 6 VO2 Output Voltage 2 (internally connected to VO1) t C 7 V Output Voltage 1 u O1 r r 8 VDD Positive Supply Voltage e n t , G a t e D r i v e O p t o c o u p l e r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 2

F O Safety and Insulation Ratings D 3 As per DIN EN/IEC 60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit 1 2 data. Compliance with the safety ratings shall be ensured by means of protective circuits. 0 — Parameter Characteristics H < 150 V I–IV i RMS g h < 300 V I–IV RMS Installation Classifications per DIN VDE N < 450 V I–III o 0110/1.89 Table 1, For Rated Mains Voltage RMS i s < 600 VRMS I–III e < 1000 VRMS (Option T, TS) I–III Im m Climatic Classification 40/100/21 u Pollution Degree (DIN VDE 0110/1.89) 2 n i t Comparative Tracking Index 175 y , 2 . 5 A Symbol Parameter Value Unit O Input-to-Output Test Voltage, Method A, V x 1.6 = V , u IORM PR 2,262 V t Type and Sample Test with t = 10 s, Partial Discharge < 5 pC peak p V m u PR Input-to-Output Test Voltage, Method B, VIORM x 1.875 = VPR, 2,651 V t C 100% Production Test with tm = 1 s, Partial Discharge < 5 pC peak u r V Maximum Working Insulation Voltage 1,414 V r IORM peak e n VIOTM Highest Allowable Over-Voltage 6,000 Vpeak t , External Creepage ≥ 8.0 mm G a External Clearance ≥ 7.4 mm t e External Clearance (for Option T or TS, 0.4" Lead Spacing) ≥ 10.16 mm D r DTI Distance Through Insulation (Insulation Thickness) ≥ 0.5 mm iv e TS Case Temperature(2) 175 °C O I Input Current(2) 400 mA p S,INPUT t o P Output Power (Duty Factor ≤ 2.7%)(2) 700 mW c S,OUTPUT o R Insulation Resistance at T , V = 500 V(2) > 109 Ω u IO S IO p l Note: e r 2. Safety limit value - maximum values allowed in the event of a failure. ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 3

F O Absolute Maximum Ratings (T = 25ºC unless otherwise specified) D A 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be 1 operable above the recommended operating conditions and stressing the parts to these levels is not recommended. 2 0 In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. — The absolute maximum ratings are stress ratings only. H Symbol Parameter Value Unit ig h T Storage Temperature -55 to +125 ºC STG N o T Operating Temperature -40 to +100 ºC OPR i s T Junction Temperature -40 to +125 ºC e J I Lead Wave Solder Temperature m TSOL (refer to page 21 for reflow solder profile) 260 for 10sec ºC m u I Average Input Current 25 mA n F(AVG) i I Peak Transient Forward Current(3) 1 A ty F(PEAK) , f Operating Frequency(4) 50 kHz 2 . 5 VR Reverse Input Voltage 5 V A I Peak Output Current(5) 3.0 A O O(PEAK) u 0 to 35 t V – V Supply Voltage V p DD SS T ≥ 90°C 0 to 30 u A t C V Peak Output Voltage 0 to V V O(PEAK) DD u tR(IN), tF(IN) Input Signal Rise and Fall Time 500 ns rr e PD Input Power Dissipation(6)(8) 45 mW n I t PDO Output Power Dissipation(7)(8) 250 mW , G a Notes: t e 3. Pulse Width, PW≤ 1 μs, 300 pps D r 4. Exponential Waveform, IO(PEAK)≤ | 2.5 A | (≤ 0.3 μs) iv e 5. Maximum pulse width = 10 μs, maximum duty cycle = 1.1% O 6. Derate linearly above 87°C, free air temperature at a rate of 0.77 mW/°C p t 7. No derating required across temperature range. o c 8. Functional operation under these conditions is not implied. Permanent damage may occur if the device is sub- o u jected to conditions outside these ratings. p l e r Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Value Unit T Ambient Operating Temperature -40 to +100 °C A V – V Power Supply 15 to 30 V DD SS I Input Current (ON) 7 to 16 mA F(ON) V Input Voltage (OFF) 0 to 0.8 V F(OFF) ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 4

F O Isolation Characteristics D 3 Apply over all recommended conditions, typical value is measured at TA = 25ºC 1 2 0 Symbol Parameter Conditions Min. Typ. Max. Unit — VISO Input-Output Isolation TA = 25ºC, R.H.< 50%, t = 1.0min, 5,000 VRMS H Voltage I ≤ 10 μA, 50 Hz(9)(10) I-O i g R Isolation Resistance V = 500 V(9) 1011 Ω h ISO I-O N C Isolation Capacitance V = 0 V, Freq = 1.0 MHz(9) 1 pF ISO I-O o i s Notes: e 9. Device is considered a two terminal device: Pins 2 and 3 are shorted together and Pins 5, 6, 7 and 8 are shorted Im together. m u 10. 5,000 V for 1 minute duration is equivalent to 6,000 VAC for 1 second duration. RMS RMS n i t y , 2 Electrical Characteristics . 5 A Apply over all recommended conditions, typical value is measured at V = 30 V, V = Ground, T = 25°C DD SS A O unless otherwise specified. u t Symbol Parameter Conditions Min. Typ. Max. Unit p u VF Input Forward Voltage IF = 10 mA 1.2 1.5 1.8 V t C Temperature Coefficient u Δ(V / T ) -1.8 mV/ºC r F A of Forward Voltage r e n Input Reverse Breakdown BVR Voltage IR = 10 μA 5 V t, G C Input Capacitance f = 1 MHz, V = 0V 60 pF a IN F t e High Level Output VO = VDD – 3 V -1.0 -2.0 -2.5 D I A OH Current(4) VO = VDD – 6 V -2.0 -2.5 riv e I Low Level Output VO = VSS+ 3 V 1.0 2.0 2.5 A O OL Current(4) V = V + 6 V 2.0 2.5 p O SS t o I = 10 mA, I = -2.5 A V – 6.25 V V – 2.5 V F O DD DD c V High Level Output Voltage V OH o I = 10 mA, I = -100 mA V – 0.25 V V – 0.1 V F O DD DD u p V Low Level Output Voltage IF = 0 mA, IO = 2.5 A VSS + 2.5 V VSS + 6.25 V V le OL I = 0 mA, I = 100 mA V + 0.1 V V + 0.25 V r F O SS SS V = Open, I High Level Supply Current O 2.8 3.8 mA DDH I = 7 to 16 mA F V = Open, I Low Level Supply Current O 2.8 3.8 mA DDL V = 0 to 0.8 V F Threshold Input Current I I = 0 mA, V > 5 V 2.3 5.0 mA FLH Low to High O O Threshold Input Voltage V I = 0 mA, V < 5 V 0.8 V FHL High to Low O O VUVLO+ Under Voltage Lockout IF = 10 mA, VO > 5 V 11.5 12.7 13.5 V V Threshold I = 10 mA, V < 5 V 10.0 11.2 12.0 V UVLO– F O Under Voltage Lockout UVLO 1.5 V HYS Threshold Hysteresis ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 5

F O Switching Characteristics D 3 Apply over all recommended conditions, typical value is measured at VDD = 30 V, VSS = Ground, TA = 25°C 1 2 unless otherwise specified. 0 — Symbol Parameter Conditions Min. Typ. Max. Unit H t Propagation Delay Time to Logic 150 275 400 ns ig PHL Low Output h N Propagation Delay Time to Logic t 150 255 400 ns o PLH High Output i s e PWD P| tuPlHsLe –W tiPdLtHh |Distortion, IRFg = = 7 1 m0 AΩ t o, C1g6 =m1A0, nF, 20 100 ns Im m Propagation Delay Difference f = 10 kHz, Duty Cycle = 50% PDD u Between Any Two Parts or -250 250 ns n (Skew) Channels, (t – t )(11) it PHL PLH y , tR Output Rise Time (10% – 90%) 60 ns 2 . 5 tF Output Fall Time (90% – 10%) 60 ns A tUVLO ON UVLO Turn On Delay IF = 10 mA, VO > 5 V 1.6 μs O t UVLO Turn Off Delay I = 10 mA, V < 5 V 0.4 μs u UVLO OFF F O t p | CMH| CImommumnoitny Mato Oduet pTurat nHsiigehnt TIFA = = 7 2 t5o° C16, VmDAD, = 30 V, 35 50 kV/μs ut C VCM = 2000 V(12) u r Common Mode Transient T = 25°C, V = 30 V, V = 0 V, r | CM | A DD F 35 50 kV/μs e L Immunity at Output Low V = 2000 V(13) n CM t , Notes: G 11. The difference between t and t between any two FOD3120 parts under same test conditions. a PHL PLH t e 12. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of D the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. V > 15.0 V). r O i v e 13. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of O the common pulse signal, Vcm, to assure that the output will remain low (i.e. V < 1.0 V). O p t o c o u p l e r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 6

F O Typical Performance Characteristics D 3 1 2 0 — V) 0.00 HIGHVOLTAGEDROP(V) --0010....0505 TA=-40°CIVVFFDDSr=eDSuqt7==yutC10eoVn5y1cct6yloem=3=A020V5.01H%z TPUTVOLTAGEDROP( ---000...110505 VVIIFODS==SD7=-=1m001AV05VmtoAto163m0VA High Noise I UT -1.5 TA=25°C OU m OUTP -2.0 TA=100°C HIGH -0.20 mu -V)-DD -2.5 V)-DD -0.25 nity (VOH -3.00.0 0.5I -OUTP1.U0THIGHCU1.R5RENT(A)2.0 2.5 (V-OH -0.30-40 -20 0 20 40 60 80 100 , 2.5 OH TA-AMBIENTTEMPERATURE(°C) A Fig. 3 Output High Voltage Drop vs. Output High Current Fig. 4 Output High Voltage Drop vs. Ambient Temperature O u t p u 8 f=200Hz 5 f=100Hz t DUTYCYCLE=0.2% DUTYCYCLE=0.5% C HCURRENT(A) 6 RIFg==75tΩo1to6mGAND VDD=30V HCURRENT(A) 34 RIFg==71t0oΩ16tomGAND VDD=30V urrent, G OUTPUTHIG 24 VDD=15V OUTPUTHIG 2 VDD=15V ate Dri – – 1 v IOH IOH e O 0 0 p -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 to TA–AMBIENTTEMPERATURE(°C) TA–AMBIENTTEMPERATURE(°C) co Fig. 5 Output High Current vs. Ambient Temperature Fig. 6 Output High Current vs. Ambient Temperature u p l e r (V) 4 VFDVrFDue(DtOqy=FuFCe1)ny5=ccV-lye3t=.o=0V239509t0V.o9H0%z.8V E(V) 00..2205 VVVIOFDS(=DSOF==1F0)10=0V5mV-3AtVo3to00V.8V GE 3 VSS=0V AG LTA TA=100°C OLT VO TA=25°C WV 0.15 W O O 2 L TL UT 0.10 U P P T T U -OUOL 1 TA=-40°C V-OOL 0.05 V 0.00 0 0.0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 T -AMBIENTTEMPERATURE(°C) I -OUTPUTLOWCURRENT(A) A OL Fig. 7 Output Low Voltage vs. Output Low Current Fig. 8 Output Low Voltage vs. Ambient Temperature ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 7

F O Typical Performance Characteristics (Continued) D 3 1 2 0 — 8 f=200Hz 5 f=100Hz H DUTYCYCLE=99.8% DUTYCYCLE=99.5% i CURRENT(A) 6 IRFg==75tΩo1to6VmDAD VDD=30V CURRENT(A) 34 RIFg==71t0oΩ16tomVADD gh Nois TLOW 4 UTLOW 2 VDD=30V e Im PU VDD=15V TP m T U OU 2 –O 1 VDD=15V un I–OL IOL ity , 0 2 0-40 -20 T –0AMBIEN2T0TEMPE40RATURE6(0°C) 80 100 -40 -20 TA–0AMBIEN2T0TEMPE4R0ATURE6(0°C) 80 100 .5 A Fig. 9 Output Low Current vs. Ambient Temperature Fig. 10 Output Low Current vs. Ambient Temperature O u t p u mA) 33..46 VVIIFFDS==DS==010m03mV0AAV(f(oforrIDIDDLD)H) mA) 33..26 IIVFFS==S=100m0mA,AT(fA(ofor=Ir2D5IDD°DLC)H) t Curre ( 3.2 ( n RRENT 3.0 RRENT t, G I-SUPPLYCUDD 22..68 IIDDDDLH I-SUPPLYCUDD 22..48 IIDDDDLH ate Drive 2.4 O p 2.2 2.0 t -40 -20 0 20 40 60 80 100 15 20 25 30 o c TA-AMBIENTTEMPEATURE(°C) V-SUPPLYVOLTAGE(V) o Fig. 11 Supply Current vs. Ambient Temperature Fig. 12 Supply Current vs. Supply Voltage u p l e r RESHOLD (mA) 34..50 VVOSDuSDt=p=u10t5V=VOtope3n0V AY (ns) 345000 DfITRF=AUg==T1=10Y210k5m0CHΩ°YACz,CCLgE==1500n%F TH 3.0 EL 300 NT N D tPHL GH CURRE 22..05 OPAGATOI 220500 tPLH W TO HI 1.5 - PRtP150 O L I- FLH 1.0-40 -20 0 20 40 60 80 100 10015 18 21 24 27 30 T -AMBIENTTEMPERATURE(°C) VDD–SUPPLYVOLTAGE(V) A Fig. 13 Low to High Input Current Threshold vs. Fig. 14 Propagation Delay vs. Supply Voltage Ambient Temperature ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 8

F O Typical Performance Characteristics (Continued) D 3 1 2 0 — Y (ns) 450000 VRTDf=DAgUD=T1=0=Y2153k0C°H0ΩYCVz,C,CLVgESS===15000Vn%F Y (ns) 450000 IVRDfF=DgU=D1T=1=0Y013mk0CH0ΩYAVz,C,CLVgESS===15000Vn%F High N A A o L L E E i D D s N N e ATIO 300 tPHL ATIO 300 tPHL Im G G –PROPO 200 tPLH –PROPO 200 tPLH mun tP tP it y , 1006 8 10 12 14 16 100-40 -20 0 20 40 60 80 100 2. IF–FORWARDLEDCURRENT(mA) TA–AMBIENTTEMPERATURE(°C) 5 A Fig. 15 Propagation Delay vs. LED Forward Current Fig. 16 Propagation Delay vs. Ambient Temperature O u t p u 500 IF=10mA 500 IF=10mA t C VDD=30V,VSS=0V VDD=30V,VSS=0V u Y (ns) 400 CTDAgU=T=Y2150C°nCYFCLE=50% Y (ns) 400 DRTAUg=T=Y215C0°ΩYCCLE=50% rre LA f=10kHz LA f=10kHz n E E t D D , N N G OPOGATIO 300 ttPPLHHL OPOGATIO 300 ttPPLHHL ate D PR 200 PR 200 r –P –P iv t t e O 1000 10 20 30 40 50 1000 20 40 60 80 100 p t R -SERIESLOADRESISTANCE(Ω) C -LOADCAPACITANCE(nF) o g g c Fig. 17 Propagation Delay vs. Sereies Load Resistance Fig. 18 Propagation Delay vs. Load Capacitance o u p l e 35 T =25°C 100 r VA = DD 30V 30 mA) 10 E(V) 25 NT( TA=100°C G E VOLTA 20 CURR 1 TA=-40°C UTPUT 15 WARD 0.1 –O OR TA=25°C VO 10 F - 0.01 IF 5 0.001 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 1 2 3 4 5 V -FORWARDVOLTAGE(V) I – FORWARDLEDCURRENT (mA) F F Fig. 19 Transfer Characteristics Fig. 20 Input Forward Current vs. Forward Voltage ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 9

F O Typical Performance Characteristics (Continued) D 3 1 2 0 — 14 (12.75,12.80) H 12 ig (11.25,11.30) h V) 10 N GE( o A i LT 8 s O e V UT I TP 6 m U O m – VO 4 u n i t 2 y , 2 0 (11.20,0.00) (12.70,0.00) .5 0 5 10 15 20 A (V -V )–SUPPLYVOLTAGE(V) DD SS Fig. 21 Under Voltage Lockout O u t p u t C u r r e n t , G a t e D r i v e O p t o c o u p l e r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 10

F O Test Circuit D 3 1 2 0 — Power Supply H + i C1 + C2 VDD = 15 V to 30 V g 0.1μF 47μF h N Pulse Generator o i s 1 8 PW = 4.99 ms e PReriod = = 5 50 mΩs Pulse-In Im OUT 2 7 m R1020Ω Iol Power Supply un 3 6 + i t LED-IFmon VOL D1 C0.31μF + C474μF V = 6 V y, 2 4 5 . 5 A R1 100Ω To Scope O u Test Conditions: t p Frequency = 200 Hz u Duty Cycle = 99.8% t VDD = 15 V to 30 V C VSS = 0 V u VF(OFF) = -3.0 V to 0.8 V r r e n Figure 22. IOL Test Circuit t, G a t e D Power Supply r + iv C0.11μF + 4C72μF VDD = 15 V to 30 V e O p Pulse Generator to c PW = 10μs 1 8 o Period = 5 ms u ROUT = 50Ω Pulse-In p 2 7 + Power Supply le C3 + C4 r R2 Ioh 0.1μF 47μF V = 6 V 100Ω 3 6 – LED-IFmon VOH D1 Current 4 5 Probe To Scope R1 100Ω Test Conditions: Frequency = 200 Hz Duty Cycle = 0.2% VDD = 15 V to 30 V VSS = 0 V IF = 7 mA to 16 mA Figure 23. I Test Circuit OH ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 11

F O Test Circuit (Continued) D 3 1 2 0 — 1 8 H i g h 2 7 0.1μF N IF = 7 to 16 mA +– VDD = 15 to 30 V oi s 3 6 VO e I m 100 mA m 4 5 u n i t y , Figure 24. V Test Circuit 2 OH . 5 A O u t 1 8 p u t 100 mA C 2 7 u 0.1μF + VDD = 15 to 30 V rr – e n 3 6 VO t, G a 4 5 te D r i v e Figure 25. V Test Circuit O OL p t o c o u p l e r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 12

F O Test Circuit (Continued) D 3 1 2 0 — 1 8 H i g h 2 7 0.1μF N + VDD = 30 V o IF = 7 to 16 mA – i s 3 6 VO e I m m 4 5 u n i t y , 2 Figure 26. IDDH Test Circuit .5 A O u 1 8 tp u t C 2 7 0.1μF u + + VDD = 30 V r – VF = -0.3 to 0.8 V – re n 3 6 VO t , G a 4 5 te D r i v e Figure 27. IDDL Test Circuit O p t o c o u p l e r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 13

F O Test Circuit (Continued) D 3 1 2 0 — 1 8 H i g h 2 7 0.1μF N + VDD = 15 to 30 V o – is IF 3 6 VO > 5 V e I m m 4 5 u n i t y , Figure 28. IFLH Test Circuit 2.5 A O u 1 8 t p u t C 2 7 0.1μF u + + VDD = 15 to 30 V r – VF = –0.3 to 0.8 V – r e 3 6 VO nt , G a 4 5 t e D r i v Figure 29. V Test Circuit e FHL O p t o c 1 8 o u p l 2 7 0.1μF er + IF = 10 mA – 15 V or 30 V VDD Ramp 3 6 VO = 5 V 4 5 Figure 30. UVLO Test Circuit ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 14

F O Test Circuit (Continued) D 3 1 2 0 1 8 — 0.1μF H 2 7 VO ig + VDD = 15 to 30 V h + – – N F = 10 kHz Probe 3 6 Rg = 10Ω o DC = 50% is Cg = 10 nF 50Ω e 4 5 I m m u n i t y , IF 2 . 5 tr tf A O 90% u t p 50% u t VOUT 10% C u r r tPLH tPHL e n Figure 31. tPHL, tPLH, tR and tF Test Circuit and Waveforms t, G a t e D IF 1 8 r i v A e 2 7 0.1μF O B + – VDD = 30 V p 5V +– 3 6 VO toc o u 4 5 p l e r + – VCM = 2,000 V VCM 0V Δt VO VOH Switch at A: IF = 10 mA VO VOL Switch at B: IF = 0 mA Figure 32. CMR Test Circuit and Waveforms ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 15

F O Reflow Profile D 3 1 Max. Ramp-up Rate = 3°C/S 2 TP Max. Ramp-down Rate = 6°C/S 0 260 — 240 tP TL H 220 i g 200 Tsmax h tL N C) 180 Preheat Area o °ure ( 116400 Tsmin ts ise Im t 120 a m er 100 u p n m 80 i t e 60 y T , 40 2 . 5 20 A 0 O 120 240 360 u t p Time 25°C to Peak u t Time (seconds) C u r r e n t Profile Freature Pb-Free Assembly Profile , G Temperature Min. (Tsmin) 150°C a t e Temperature Max. (Tsmax) 200°C D Time (t ) from (Tsmin to Tsmax) 60–120 seconds r S i v Ramp-up Rate (t to t ) 3°C/second max. e L P O Liquidous Temperature (T ) 217°C L p t Time (t ) Maintained Above (T ) 60–150 seconds o L L c Peak Body Package Temperature 260°C +0°C / –5°C o u Time (t ) within 5°C of 260°C 30 seconds p P l e Ramp-down Rate (TP to TL) 6°C/second max. r Time 25°C to Peak Temperature 8 minutes max. ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 16

F O Ordering Information D 3 1 Part Number Package Packing Method 2 0 FOD3120 DIP 8-Pin Tube (50 units per tube) — FOD3120S SMT 8-Pin (Lead Bend) Tube (50 units per tube) H FOD3120SD SMT 8-Pin (Lead Bend) Tape and Reel (1,000 units per reel) ig h FOD3120V DIP 8-Pin, DIN_EN/IEC60747-5-5 option Tube (50 units per tube) N FOD3120SV SMT 8-Pin (Lead Bend), DIN_EN/IEC60747-5-5 option Tube (50 units per tube) o i s FOD3120SDV SMT 8-Pin (Lead Bend), DIN_EN/IEC60747-5-5 option Tape and Reel (1,000 units per reel) e I FOD3120TV DIP 8-Pin, 0.4” Lead Spacing, DIN_EN/IEC60747-5-5 option Tube (50 units per tube) m m FOD3120TSV SMT 8-Pin, 0.4” Lead Spacing, DIN_EN/IEC60747-5-5 option Tube (50 units per tube) u FOD3120TSR2V SMT 8-Pin, 0.4” Lead Spacing, DIN_EN/IEC60747-5-5 option Tape and Reel (700 units per reel) n i t y , 2 . 5 Marking Information A O u t p u t C 1 u r r e n 3120 2 t , G V XX YY B 6 a t e D r i v 3 4 5 e O Figure 33. Top Mark p t o c Definitions o u p 1 Fairchild logo l e r 2 Device number 3 DIN_EN/IEC60747-5-5 Option (only appears on component ordered with this option) 4 Two digit year code, e.g., ‘16’ 5 Two digit work week ranging from ‘01’ to ‘53’ 6 Assembly package code ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 17

F O Carrier Tape Specifications (Option SD) D 3 1 D 2 0 0 P0 P2 — t E K 0 H i g h N F o A 0 i W1 B0 W se I m m u n P it d UserDirectionofFeed D1 y, 2 . 5 A Symbol Description Dimension in mm O W Tape Width 16.0 ± 0.3 u t p t Tape Thickness 0.30 ± 0.05 u t P0 Sprocket Hole Pitch 4.0 ± 0.1 C u D Sprocket Hole Diameter 1.55 ± 0.05 0 r r E Sprocket Hole Location 1.75 ± 0.10 e n t F Pocket Location 7.5 ± 0.1 , G P2 2.0 ± 0.1 a t e P Pocket Pitch 12.0 ± 0.1 D A0 Pocket Dimensions 10.30 ±0.20 ri v B 10.30 ±0.20 e 0 O K 4.90 ±0.20 0 p W1 Cover Tape Width 13.2 ± 0.2 to c d Cover Tape Thickness 0.1 max o u Max. Component Rotation or Tilt 10° p l e R Min. Bending Radius 30 r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 18

F O Carrier Tape Specifications (Option TSR2) D 3 1 D 2 0 0 P0 P2 — t E K 0 H i g h N F o A 0 i W1 B0 W se I m m u n P it d UserDirectionofFeed D1 y, 2 . 5 A Symbol Description Dimension in mm O W Tape Width 24.0 ± 0.3 u t p t Tape Thickness 0.40 ± 0.1 u t P0 Sprocket Hole Pitch 4.0 ± 0.1 C u D Sprocket Hole Diameter 1.55 ± 0.05 0 r r E Sprocket Hole Location 1.75 ± 0.10 e n t F Pocket Location 11.5 ± 0.1 , G P2 2.0 ± 0.1 a t e P Pocket Pitch 16.0 ± 0.1 D A0 Pocket Dimensions 12.80 ± 0.1 ri v B 10.35 ± 0.1 e 0 O K 5.7 ±0.1 0 p W1 Cover Tape Width 21.0 ± 0.1 to c d Cover Tape Thickness 0.1 max o u Max. Component Rotation or Tilt 10° p l e R Min. Bending Radius 30 r ©2003 Fairchild Semiconductor Corporation www.fairchildsemi.com FOD3120 Rev. 1.4 19

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