FM33256B 256-Kbit (32 K × 8) Integrated Processor Companion with F-RAM 256-Kbit (32 K × 8) Serial (SPI) F-RAM Features Functional Overview ■256-Kbit ferroelectric random access memory (F-RAM) The FM33256B device integrates F-RAM memory with the most ❐Logically organized as 32 K × 8 commonly needed functions for processor-based systems. ❐High-endurance 100 trillion (1014) read/writes Major features include nonvolatile memory, real time clock, ❐151-year data retention (See the Data Retention and low-VDD reset, watchdog timer, nonvolatile event counter, Endurance table) lockable 64-bit serial number area, and general purpose ❐NoDelay™ writes comparator that can be used for a power-fail (NMI) interrupt or ❐Advanced high-reliability ferroelectric process any other purpose. The FM33256B is a 256-Kbit nonvolatile memory employing an ■High Integration Device Replaces Multiple Parts advanced ferroelectric process. A ferroelectric random access ❐Serial nonvolatile memory memory or F-RAM is nonvolatile and performs reads and writes ❐Real time clock (RTC) with alarm similar to a RAM. It provides reliable data retention for 151 years ❐Low V detection drives reset DD while eliminating the complexities, overhead, and system-level ❐Watchdog window timer reliability problems caused by other nonvolatile memories. The ❐Early power-fail warning / NMI FM33256B is capable of supporting 1014 read/write cycles, or ❐16-bit nonvolatile event counter 100 million times more write cycles than EEPROM. ❐Serial number with write-lock for security The real time clock (RTC) provides time and date information in ■Real-time Clock/Calendar BCD format. It can be permanently powered from an external ❐Backup current at 2 V: 1.15 μA at +25 °C backup voltage source, either a battery or a capacitor. The ❐Seconds through centuries in BCD format timekeeper uses a common external 32.768 kHz crystal and ❐Tracks leap years through 2099 provides a calibration mode that allows software adjustment of ❐Uses standard 32.768 kHz crystal (6 pF/12.5 pF) timekeeping accuracy. ❐Software calibration The processor companion includes commonly needed CPU ❐Supports battery or capacitor backup support functions. Supervisory functions include a reset output ■Processor Companion signal controlled by either a low VDD condition or a watchdog ❐Active-low reset output for VDD and watchdog timeout. RST goes active when VDD drops below a ❐Programmable low-V reset thresholds programmable threshold and remains active for 100 ms (max.) DD ❐Manual reset filtered and debounced after VDD rises above the trip point. A programmable watchdog ❐Programmable watchdog window timer timer runs from 60 ms to 1.8 seconds. The timer may also be ❐Nonvolatile event counter tracks system intrusions or other programmed for a delayed start, which functions as a window events timer. The watchdog timer is optional, but if enabled it will assert ❐Comparator for power-fail interrupt or other use the reset signal for 100 ms if not restarted by the host within the ❐64-bit programmable serial number with lock time window. A flag-bit indicates the source of the reset. ■Fast serial peripheral interface (SPI) A comparator on PFI compares an external input pin to the ❐Up to 16-MHz frequency onboard 1.5 V reference. This is useful for generating a ❐RTC, Supervisor controlled via SPI interface power-fail interrupt (NMI) but can be used for any purpose. The family also includes a programmable 64-bit serial number that ❐Supports SPI mode 0 (0, 0) and mode 3 (1, 1) can be locked making it unalterable. Additionally it offers an ■Low power consumption event counter that tracks the number of rising or falling edges ❐1.1 mA active current at 1 MHz detected on a dedicated input pin. The counter can be ❐150 μA standby current programmed to be nonvolatile under V power or DD battery-backed using only V . If V is connected to a battery ■Operating voltage: V = 2.7 V to 3.6 V BAK BAK DD or capacitor, then events will be counted even in the absence of ■Industrial temperature: –40 °C to +85 °C V . DD ■14-pin small outline integrated circuit (SOIC) package For a complete list of related documentation, click here. ■Restriction of hazardous substances (RoHS) compliant ■Underwriters laboratory (UL) recognized CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-86213 Rev. *C Revised August 5, 2015

FM33256B Logic Block Diagram Document Number: 001-86213 Rev. *C Page 2 of 39

FM33256B Contents Pinout ................................................................................4 WRSR - Write Status Register ..................................26 Pin Definitions ..................................................................4 RDPC - Read Processor Companion ........................27 Overview ............................................................................5 WRPC - Write Processor Companion .......................27 Memory Architecture ...................................................5 Memory Operation ..........................................................28 Processor Companion .....................................................5 Write Operation .........................................................28 Processor Supervisor ..................................................5 Read Operation .........................................................28 Manual Reset ..............................................................6 Maximum Ratings ...........................................................30 Reset Flags .................................................................6 Operating Range .............................................................30 Power Fail Comparator ...............................................6 DC Electrical Characteristics ........................................30 Event Counter .............................................................7 Data Retention and Endurance .....................................32 Serial Number .............................................................7 Capacitance ....................................................................32 Alarm ...........................................................................8 Thermal Resistance ........................................................32 Real-time Clock Operation ...............................................8 AC Test Conditions ........................................................32 Backup Power .............................................................9 Supervisor Timing ..........................................................33 Trickle Charger ..........................................................10 AC Switching Characteristics .......................................34 Calibration .................................................................10 Ordering Information ......................................................35 Crystal Type ..............................................................10 Ordering Code Definitions .........................................35 Layout Recommendations .............................................10 Package Diagram ............................................................36 Register Map ...................................................................13 Acronyms ........................................................................37 Serial Peripheral Interface – SPI Bus ............................23 Document Conventions .................................................37 SPI Overview .............................................................23 Units of Measure .......................................................37 SPI Modes .................................................................24 Document History Page .................................................38 Power Up to First Access ..........................................25 Sales, Solutions, and Legal Information ......................39 Command Structure ..................................................25 Worldwide Sales and Design Support .......................39 WREN - Set Write Enable Latch ...............................25 Products ....................................................................39 WRDI - Reset Write Enable Latch .............................25 PSoC® Solutions ......................................................39 Status Register and Write Protection ...........................26 Cypress Developer Community .................................39 RDSR - Read Status Register ...................................26 Technical Support .....................................................39 Document Number: 001-86213 Rev. *C Page 3 of 39

FM33256B Pinout Figure 1. 14-pin SOIC pinout CS 1 14 VDD SO 2 13 ACS CNT 3 12 SCK VBAK 4 11 SI X2 5 10 PFO X1 6 9 RST VSS 7 8 PFI Pin Definitions Pin Name I/O Type Description CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power standby mode, ignores SCK and SI inputs, and the SO output is tristated. When LOW, the device internally activates the SCK signal. A falling edge on CS must occur before every opcode. SCK Input Serial Clock. SI and SO activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may be any value between 0 and 16 MHz and may be interrupted at any time. SI [1] Input Serial Input. Data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet I specifications. DD SO [1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other times. Data transitions are driven on the falling edge of the serial clock. CNT Input Event Counter Input. This input increments the counter when an edge is detected on this pin. The polarity is programmable and the counter value is nonvolatile or battery-backed, depending on the mode. This pin should be tied to ground if unused. ACS Output Alarm/Calibration/SquareWave. This is an open-drain output that requires an external pull-up resistor. In normal operation, this pin acts as the active-low alarm output. In Calibration mode, a512Hz square-wave is driven out. In SquareWave mode, the user may select a frequency of 1, 512, 4096, or 32768 Hz to be used as a continuous output. The SquareWave mode is entered by clearing the AL/SW and CAL bits in the register 18h. X1, X2 Input/Output 32.768 kHz crystal connection. These pins should be left unconnected if RTC is not used. RST Input/Output Reset. This active-low output is open drain with weak pull-up. It is also an input when used as a manual reset. This pin should be left floating if unused. PFI Input Early Power-fail Input. Typically connected to an unregulated power supply to detect an early power failure. This pin must be tied to ground if unused. PFO Output Early Power-fail Output. This pin is the early power-fail output and is typically used to drive a micro- controller NMI pin. PFO drives LOW when the PFI voltage is < 1.5 V. V Power supply Backup supply voltage. Connected to a 3 V battery or a large value capacitor. If no backup supply BAK is used, this pin should be tied to V and the VBC bit should be cleared in the RTC register 18h. The SS trickle charger is UL recognized and ensures no excessive current when using a lithium battery. V Power supply Ground for the device. Must be connected to the ground of the system. SS V Power supply Power supply input to the device. DD Note 1. SI may be connected to SO for a single pin data interface. Document Number: 001-86213 Rev. *C Page 4 of 39

FM33256B Overview faults, power-up, and software lockups. It is an open drain output with a weak internal pull-up to V . This allows other reset DD The FM33256B device combines a serial nonvolatile RAM with sources to be wire-OR'd to the RST pin. When V is above the DD a real time clock (RTC) and a processor companion. The programmed trip point, RST output is pulled weakly to V . If DD companion is a highly integrated peripheral including a V drops below the reset trip point voltage level (V ), the RST DD TP processor supervisor, analog comparator, a nonvolatile counter, pin will be driven LOW. It will remain LOW until V falls too low DD and a serial number. The FM33256B integrates these for circuit operation which is the V level. When V rises RST DD complementary but distinct functions under a common interface again above V , RST continues to drive LOW for at least 30 ms TP in a single package. The product is organized as two logical (t ) to ensure a robust system reset at a reliable V level. RPU DD devices. The first is a memory and the second is the companion After t has been met, the RST pin will return to the weak RPU which includes all the remaining functions. From the system HIGH state. While RST is asserted, serial bus activity is locked perspective they appear to be two separate devices with unique out even if a transaction occurred as V dropped below V . A DD TP opcodes on the serial bus. memory operation started while V is above V will be DD TP completed internally. The memory is organized as a standalone nonvolatile SPI memory using standard opcodes. The real time clock and Table1 below shows how bits VTP(1:0) control the trip point of supervisor functions are accessed under their own opcodes. The the low-V reset. They are located in register 18h, bits 1 and 0. DD clock and supervisor functions are controlled by 30 special The reset pin will drive LOW when V is below the selected V DD TP function registers. The RTC alarm and some control registers are voltage, and the SPI interface and F-RAM array will be locked maintained by the power source on the VBAK pin, allowing them out. Figure 2 illustrates the reset operation in response to a low to operate from battery or backup capacitor power when VDD VDD. drops below a set threshold. Each functional block is described Table 1. VTP setting below. VTP Setting VTP1 VTP0 Memory Architecture 2.6 V 0 0 The FM33256B is available with 256-Kbit of memory. The device 2.75 V 0 1 uses two-byte addressing for the memory portion of the chip. 2.9 V 1 0 This makes the device software compatible with its standalone memory counterparts, such as the FM25W256. 3.0 V 1 1 The memory array is logically organized as 32,768 × 8 bits and Figure 2. Low V Reset is accessed using an industry-standard serial peripheral DD interface (SPI) bus. The memory is based on F-RAM technology. Therefore it can be treated as RAM and is read or written at the speed of the SPI bus with no delays for write operations. It also VDD t offers effectively unlimited write endurance unlike other RPU V TP nonvolatile memory technologies. The SPI protocol is described on page 23. The memory array can be write-protected by software. Two bits (BP1, BP0) in the Status Register control the protection setting. RST Based on the setting, the protected addresses cannot be written. The Status Register & Write Protection is described in more A watchdog timer can also be used to drive an active reset signal. detail on page 26. The watchdog is a free-running programmable timer. The timeout period can be software programmed from 60 ms to 1.8 Processor Companion seconds in 60 ms increments via a 5-bit nonvolatile setting In addition to nonvolatile RAM, the FM33256B incorporates a (register 0Ch). real time clock with alarm and highly integrated processor Figure 3. Watchdog Timer companion. The companion includes a low-V reset, a DD programmable watchdog timer, a 16-bit nonvolatile event counter, a comparator for early power-fail detection or other WR(3:0) = 1010bto restart purposes, and a 64-bit serial number. 100 ms clock Processor Supervisor Timebase Down Counter RST Supervisors provide a host processor two basic functions: Detection of power supply fault conditions and a watchdog timer Watchdog to escape a software lockup condition. The FM33256B has a Timer Settings WDE reset pin (RST) to drive a processor reset input during power Document Number: 001-86213 Rev. *C Page 5 of 39

FM33256B The watchdog also incorporates a window timer feature that The restart command in step 3 must be issued before t , DOG2 allows a delayed start. The starting time and ending time defines which was programmed in step 2. The window timer starts the window and each may be set independently. The starting counting when the restart command is issued. time has 25 ms resolution and 0 ms to 775 ms range. Manual Reset Figure 4. Window Timer The RST is a bi-directional signal allowing the FM33256B to filter and de-bounce a manual reset switch. The RST input detects an Watchdog Start End external low condition and responds by driving the RST signal Restart Time Time LOW for 100 ms (max). This effectively filters and de-bounces a reset switch. After this timeout (t ), the user may continue RPU pulling down on the RST pin, but SPI commands will not be locked out. Window Figure 5. Manual Reset RST 100 ms (max) MCU RST The watchdog EndTime value is located in register 0Ch, bits 4:0, FM33256B Reset the watchdog enable is bit 7. The watchdog is restarted by writing Switch the pattern 1010b to the lower nibble of register 0Ah. Writing the correct pattern will also cause the timer to load new timeout values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is free-running. Prior to enabling it, users should restart the timer as described above. FM33256B This assures that the full timeout is provided immediately after RST drives enabling. The watchdog is disabled when V drops below V . DD TP 100 ms (max.) Note setting the EndTime timeout setting to all zeroes (00000b) disables the timer to save power. The listing below summarizes Note The internal weak pull-up eliminates the need for additional the watchdog bits. external components. Watchdog Start Time WDST(4:0) 0Bh, bits 4:0 Watchdog EndTime WDET(4:0) 0Ch, bits 4:0 Reset Flags Watchdog Enable WDE 0Ch, bit 7 In case of a reset condition, a flag bit will be set to indicate the Watchdog Restart WR(3:0) 0Ah, bits 3:0 source of the reset. A low-V reset is indicated by the POR flag, Watchdog Flags EWDF 09h, bit 7 DD register 09h bit 5. There are two watchdog reset flags - one for LWDF 09h, bit 6 an early fault (EWDF) and the other for a late fault (LWDF), The programmed StartTime value is a guaranteed maximum located in register 09h bits 7 and 6. A manual reset will result in time while the EndTime value is a guaranteed minimum time, no flag being set, so the absence of a flag is a manual reset. Note and both vary with temperature and V voltage. The watchdog that the bits are set in response to reset sources but they must DD has two additional controls associated with its operation. The be cleared by the user. It is possible to read the register and have nonvolatile enable bit WDE allows the RST to go active if the both sources indicated if both have occurred since the user watchdog reaches the timeout without being restarted. If a reset cleared them. occurs, the timer will restart on the rising edge of the reset pulse. Power Fail Comparator If WDE is not enabled, the watchdog timer still runs but has no effect on RST. The second control is a nibble that restarts the An analog comparator compares the PFI input pin to an onboard timer, thus preventing a reset. The timer should be restarted after 1.5 V reference. When the PFI input voltage drops below this changing the timeout value. threshold, the comparator will drive the PFO pin to a LOW state. The comparator has 100 mV of hysteresis (rising voltage only) to This procedure must be followed to properly load the watchdog reduce noise sensitivity. The most common application of this registers: Address comparator is to create an early warning power fail interrupt 1.Write the StartTime value 0Bh (NMI). This can be accomplished by connecting the PFI pin to an 2.Write the EndTime value and WDE = ‘1’ 0Ch upstream power supply via a resistor divider. An application 3.Issue a Restart command 0Ah circuit is shown below. The comparator is a general purpose device and its application is not limited to the NMI function. Document Number: 001-86213 Rev. *C Page 6 of 39

FM33256B mode to battery-backed allows counter operation under V (as BAK well as V ) power. The lowest operating voltage for Figure 6. Comparator as a Power-Fail Warning DD battery-backed mode is 2.0 V. When set to "nonvolatile" mode, the counter operates only when V is applied and is above the DD V voltage. TP VDD Regulator The event counter may be programmed to detect a tamper event, such as the system's case or access door being opened. A normally closed switch is tied to the CNT pin and the other contact to the case chassis, usually ground. The typical solution uses a pull-up resistor on the CNT pin and will continuously draw battery current. The FM33256B chip allows the user to invoke a FM33256B polled mode, which occasionally samples the pin in order to minimize battery drain. It internally tries to pull the CNT pin up To MCU CAL/PFO + PFI and if open circuit will be pulled up to a VIH level, which will trip NMI input - 1.5 V ref the edge detector and increment the event counter value. Setting the POLL bit (register 0Dh, bit 1) places the CNT pin into this mode. This mode allows the event counter to detect a rising edge tamper event but the user is restricted to operating in If the power-fail comparator is not used, the PFI pin should be battery-backed mode (NVC = ‘0’) and using rising edge detection tied to either V or V . Note that the PFO output will drive to DD SS (CP = ‘1’). The CNT pin is polled once every 125 ms. The V or V as well. DD SS additional average I current is less than 20 nA. The polling BAK timer circuit operates from the RTC, so the oscillator must be Event Counter enabled for this to function properly. The FM33256B offers the user a nonvolatile 16-bit event counter. The input pin CNT has a programmable edge detector. The CNT Figure 8. Polled Mode on CNT pin Detects Tamper pin clocks the counter. The counter is located in registers 0E-0Fh. When the programmed edge polarity occurs, the counter will increment its count value. The register value is read VBAK by setting the RC bit (register 0Dh, bit 3) to ‘1’. This takes a < 100 pF FM33256B snapshot of the counter byte allowing a stable value even if a count occurs during the read. The register value can be written CNT by first setting the WC bit (register 0Dh, bit 2) to ‘1’. The user then 125 ms may clear or preset the counter by writing to registers 0E-0Fh. Counts are blocked when the WC bit is set, so the user must clear the bit to allow counts. The counter polarity control bit is CP (register 0Dh, bit 0). When In the polled mode, the internal pull-up circuit can source a CP is ‘0’, the counter increments on a falling edge of CNT, and limited amount of current. The maximum capacitance (switch when CP is set to ‘1’, the counter increments on a rising edge of open circuit) allowed on the CNT pin is 100 pF. CNT. The polarity bit CP is nonvolatile. Serial Number Figure 7. Event Counter A memory location to write a 64-bit serial number is provided. It is a writeable nonvolatile memory block that can be locked by the CP user once the serial number is set. The 8 bytes of data and the lock bit are all accessed via unique opcodes for the RTC and CNT 16-bit Counter Processor Companion registers. Therefore the serial number area is separate and distinct from the memory array. The serial number registers can be written an unlimited number of times, so these locations are general purpose memory. However once The counter does not wrap back to zero when it reaches the limit the lock bit is set, the values cannot be altered and the lock of 65,535 (FFFFh). Care must be taken prior to the rollover, and cannot be removed. Once locked the serial number registers can a subsequent counter reset operation must occur to continue still be read by the system. counting. The serial number is located in registers 10h to 17h. The lock bit There is also a control bit that allows the user to define the is SNL (register 18h, bit 7). Setting the SNL bit to a ‘1’ disables counter as nonvolatile or battery-backed. The counter is writes to the serial number registers, and the SNL bit cannot be nonvolatile when the NVC bit (register 0Dh, bit 7) is logic 1 and cleared. battery-backed when the NVC bit is logic 0. Setting the counter Document Number: 001-86213 Rev. *C Page 7 of 39

FM33256B Alarm flag and ACS pin will remain in this state until the AF bit is cleared by writing it to a '0'. Clearing the AEN bit will prevent further The alarm function compares user-programmed values to the matches from setting AF but will not automatically clear the AF corresponding time/date values and operates under V or V DD BAK flag. power. When a match occurs, an alarm event occurs. The alarm drives an internal flag AF (register 00h, bit 6) and may drive the The RTC alarm is integrated into the special function registers ACS pin, if desired, by setting the AL/SW bit (register 18h, bit 6) and shares its output pin with the 512 Hz calibration and square in the Companion Control register. The alarm condition is cleared wave outputs. When the RTC calibration mode is invoked by by writing a '0' to the AF bit. setting the CAL bit (register 00h, bit 2), the ACS output pin will be driven with a 512 Hz square wave and the alarm will continue There are five alarm match fields. They are Month, Date, Hours, to operate. Since most users only invoke the calibration mode Minutes, and Seconds. Each of these fields also has a Match bit during production this should have no impact on the otherwise that is used to determine if the field is used in the alarm match normal operation of the alarm. logic. Setting the Match bit to '0' indicates that the corresponding field will be used in the match process. The ACS output may also be used to drive the system with a frequency other than 512 Hz. The AL/SW bit (register 18h, bit 6) Depending on the Match bits, the alarm can occur as specifically must be '0'. A user-selectable frequency is provided by F0 and as one particular second on one day of the month, or as F1 (register 18h, bits 4 and 5). The other frequencies are 1, 4096, frequently as once per second continuously. The MSB of each and 32768 Hz. If a continuous frequency output is enabled with Alarm register is a Match bit. Examples of the Match bit settings CAL mode, the alarm function will not be available. are shown in Table 3. Selecting none of the match bits (all '1's) indicates that no match is required. The alarm occurs every Following is a summary table that shows the relationship second. Setting the match select bit for seconds to '0' causes the between register control settings and the state of the ACS pin. logic to match the seconds alarm value to the current time of day. Table 2. State of Register Bit Since a match will occur for only one value per minute, the alarm occurs once per minute. Likewise setting the seconds and State of Register Bit Function of minutes match select bits causes an exact match of these ACS pin CAL AEN AL/SW values. Thus, an alarm will occur once per hour. Setting seconds, minutes, and hours causes a match once per day. Lastly, 0 1 1 Alarm selecting all match-values causes an exact time and date match. Selecting other bit combinations will not produce meaningful 0 X 0 Square Wave out results, however the alarm circuit will follow the functions 1 X X 512 Hz out described. There are two ways a user can detect an alarm event, by reading 0 0 1 HI-Z the AF flag or monitoring the ACS pin. The interrupt pin on the host processor may be used to detect an alarm event. The AF flag in register 00h (bit 6) will indicate that a time/date match has occurred. The AF flag will be set to '1' when a match occurs. The AEN bit must be set to enable the AF flag on alarm matches. The Table 3. Alarm Match Bit Examples Seconds Minutes Hours Date Months Alarm condition 1 1 1 1 1 No match required = alarm 1/second 0 1 1 1 1 Alarm when seconds match = alarm 1/minute 0 0 1 1 1 Alarm when seconds, minutes match = alarm 1/hour 0 0 0 1 1 Alarm when seconds, minutes, hours match = alarm 1/date 0 0 0 0 1 Alarm when seconds, minutes, hours, date match = alarm 1/month Real-time Clock Operation Static registers provide the user with read/write access to the time values. It includes registers for seconds, minutes, hours, The real-time clock (RTC) is a timekeeping device that can be day-of-the-week, date, months, and years. A block diagram capacitor- or battery-backed for permanently-powered shown in Figure 9 illustrates the RTC function. operation. It offers a software calibration feature that allows high The user registers are synchronized with the timekeeper core accuracy. using R and W bits in register 00h. The R bit is used to read the The RTC consists of an oscillator, clock divider, and a register time. Changing the R bit from ‘0’ to ‘1’ transfers timekeeping system for user access. It divides down the 32.768 kHz information from the core into the user registers 02-08h that can time-base and provides a minimum resolution of seconds (1 Hz). be read by the user. If a timekeeper update is pending when R Document Number: 001-86213 Rev. *C Page 8 of 39

FM33256B is set, then the core will be updated prior to loading the user 8th clock of the write to register 00h (W = ‘0’), the RTC starts registers. The user registers are frozen and will not be updated counting with a timebase that has been reset to zero again until the R bit is cleared to a '0'. milliseconds. The W bit is used to write new time/date values. Setting the W Note: Users should be certain not to load invalid values, such as bit to a '1' stops the RTC and allows the timekeeping core to be FFh, to the timekeeping registers. Updates to the timekeeping written with new data. Clearing it to '0' causes the RTC to start core occur continuously except when locked. running based on the new values loaded in the timekeeper core. The RTC may be synchronized to another clock source. On the Figure 9. Real-time Clock Core Block Diagram 512 Hz or OSCEN Square Wa ve W 32c.r7y6s8ta klHz Oscillator DCivloidcekr 1 Hz ULpodgaicte Years Months Date CF 8 bits 5 bits 6 bits Hours MInutes Seconds 6 bits 7 bits 7 bits Days 3 bits User Interface Register s R Backup Power The I current varies with temperature and voltage (see DC BAK Electrical Characteristics table). Figure 10 shows I as a The real-time clock/calendar is intended to be permanently BAK function of V . These curves are useful for calculating backup powered. When the primary system power fails, the voltage on BAK time when a capacitor is used as the V source. the V pin will drop. When V is less than 2.5 V, the RTC (and BAK DD DD event counters) will switch to the backup power supply on V . The minimum V voltage varies linearly with temperature. The BAK BAK The clock operates at extremely low current in order to maximize user can expect the minimum V voltage to be 1.23 V at BAK battery or capacitor life. However, an advantage of combining a +85°C and 1.90 V at -40 °C. The tested limit is 1.55 V at +25 °C. clock function with FRAM memory is that data is not lost Note The minimum V voltage has been characterized at BAK regardless of the backup power source. -40°C and +85 °C but is not 100% tested. Figure 10. I vs. V Voltage BAK BAK Figure 11. V (min.) vs Temperature BAK V) μA) (min. (BAK VBAK I VBAK (V) Temperature (°C) Document Number: 001-86213 Rev. *C Page 9 of 39

FM33256B Trickle Charger calibration, the clock will have a maximum error of ±2.17 ppm or ±0.09 minutes per month at the calibrated temperature. To facilitate capacitor backup, the V pin can optionally BAK provide a trickle charge current. When the VBC bit (register 18h, The user will not be able to see the effect of the calibration setting bit 3) is set to a '1', the V pin will source approximately 80 µA on the 512 Hz output. The addition or subtraction of digital pulses BAK until V reaches V . This charges the capacitor to V occurs after the 512 Hz output. BAK DD DD without an external diode and resistor charger. There is also a The calibration setting is stored in F-RAM so it is not lost should Fast Charge mode which is enabled by the FC bit (register 18h, the backup source fail. It is accessed with bits CAL(4:0) in bit 2). In this mode the trickle charger current is set to register 01h. These bits can be written when the CAL bit is set to approximately 1mA, allowing a large backup capacitor to charge a ‘1’. To exit the calibration mode, the user must clear the CAL more quickly. bit to a logic ‘0’. When the CAL bit is ‘0’, the ACS pin will revert In the case where no backup supply is used, the V pin should to the function according to Table2. BAK be tied to V and VBC bit cleared. SS Crystal Type Note Systems using lithium batteries should clear the VBC bit to ‘0’ to prevent battery charging. The VBAK circuitry includes an The crystal oscillator is designed to use a 6 pF/12.5 pF crystal internal 1 KΩ series resistor as a safety element. The trickle without the need for external components, such as loading charger is UL Recognized. capacitors. The FM33256B device has built-in loading capacitors that are optimized for use with 6 pF crystals, but which work well Calibration with 12.5 pF crystals. For either crystal, no additional external When the CAL bit in register 00h is set to a '1', the clock enters loading capacitors are required nor suggested. calibration mode. The FM33256B employs a digital method for If a 32.768 kHz crystal is not used, an external oscillator may be calibrating the crystal oscillator frequency. The digital calibration connected to the FM33256B. scheme applies a digital correction to the RTC counters based on the calibration settings, CALS and CAL(4:0). In calibration Layout Recommendations mode (CAL = ‘1’), the ACS pin is driven with a 512 Hz (nominal) square wave and the alarm is temporarily unavailable. Any The X1 and X2 crystal pins employ very high impedance circuits measured deviation from 512 Hz translates into a timekeeping and the oscillator connected to these pins can be upset by noise error. The user measures the frequency and writes the or extra loading. To reduce RTC clock errors from signal appropriate correction value to the calibration register. The switching noise, a guard ring should be placed around these correction codes are listed in the table below. For convenience, pads and the guard ring grounded. High speed SPI traces should the table also shows the frequency error in ppm. Positive ppm be routed away from the X1/X2 pads. The X1 and X2 trace errors require a negative adjustment that removes pulses. lengths should be less than 5 mm. The use of a ground plane on Negative ppm errors require a positive correction that adds the backside or inner board layer is preferred. See layout pulses. Positive ppm adjustments have the CALS (sign) bit set example. Red is the top layer, green is the bottom layer. to ‘1’, whereas negative ppm adjustments have CALS = ‘0’. After Figure 12. Layout Recommendations CS CS SO SO CNT CNT VBAK VBAK X2 X2 X1 X1 V V SS SS Layout for Surface Mount Crystal Layout for Through Hole Crystal (red = top layer, green = bottom layer) (red = top layer, green = bottom layer) Document Number: 001-86213 Rev. *C Page 10 of 39

FM33256B Table 4. Digital Calibration Adjustments Positive Calibration for slow clocks: Calibration will achieve ± 2.17 PPM after calibration Measured Frequency Range Error Range (PPM) Min Max Min Max Program Calibration Register to: 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 Document Number: 001-86213 Rev. *C Page 11 of 39

FM33256B Table 4. Digital Calibration Adjustments (continued) Negative Calibration for fast clocks: Calibration will achieve ± 2.17 PPM after calibration Measured Frequency Range Error Range (PPM) Min Max Min Max Program Calibration Register to: 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111 Document Number: 001-86213 Rev. *C Page 12 of 39

FM33256B Register Map The RTC and processor companion functions are accessed via 30 special function registers, which are mapped to unique opcodes. The interface protocol is described on page 23. The registers contain timekeeping data, alarm settings, control bits, and information flags. A description of each register follows the summary table. Table 5. Register Map Summary Table Battery-backed = Nonvolatile = BB/NV User Programmable = Data Address Function Range D7 D6 D5 D4 D3 D2 D1 D0 1Dh M 0 0 Alarm 10 Alarm months Alarm Month 01-12 months 1Ch M 0 Alarm 10 date Alarm date Alarm Date 01-31 1Bh M 0 Alarm 10 hours Alarm hours Alarm Hours 00-23 1Ah M Alarm 10 minutes Alarm minutes Alarm Minutes 00-59 19h M Alarm 10 seconds Alarm seconds Alarm Seconds 00-59 18h SNL AL/SW F1 F0 VBC FC VTP1 VTP0 Companion Control 17h Serial Number Byte 7 Serial Number 7 FFh 16h Serial Number Byte 6 Serial Number 6 FFh 15h Serial Number Byte 5 Serial Number 5 FFh 14h Serial Number Byte 4 Serial Number 4 FFh 13h Serial Number Byte 3 Serial Number 3 FFh 12h Serial Number Byte 2 Serial Number 2 FFh 11h Serial Number Byte 1 Serial Number 1 FFh 10h Serial Number Byte 0 Serial Number 0 FFh 0Fh Event Counter Byte 1 Event Counter 1 FFh 0Eh Event Counter Byte 0 Event Counter 0 FFh 0Dh NVC - - - RC WC POLL CP EventCounter Control 0Ch WDE - - WDET4 WDET3 WDET2 WDET1 WDET0 Watchdog Control 0Bh - - - WDST4 WDST3 WDST2 WDST1 WDST0 Watchdog Control 0Ah - - - - WR3 WR2 WR1 WR0 Watchdog Restart 09h EWDF LWDF POR LB - - - - Watchdog Flags 08h 10 years years Years 00-99 07h 0 0 0 10 months months Month 01-12 06h 0 0 10 date date Date 01-31 05h 0 0 0 0 0 day Day 01-07 04h 0 0 10 hours hours Hours 00-23 03h 0 10 minutes minutes Minutes 00-59 02h 0 10 seconds seconds Seconds 00-59 01h - - CALS CAL4 CAL3 CAL2 CAL1 CAL0 CAL/Control 00h OSCEN AF CF AEN reserved CAL W R RTC/Alarm Control Note When the device is first powered up and programmed, all timekeeping registers must be written because the battery-backed register values cannot be guaranteed. The table below shows the default values of the non-volatile registers and some of the battery-backed bits. All other register values should be treated as unknown. Document Number: 001-86213 Rev. *C Page 13 of 39

FM33256B Table 6. Default Register Values Address Hex Value Address Hex Value Address Hex Value 1Dh 0x81 12h 0x00 05h 0x00 1Ch 0x81 11h 0x00 04h 0x00 1Bh 0x80 10h 0x00 03h 0x00 1Ah 0x80 0Fh 0x00 02h 0x00 19h 0x80 0Eh 0x00 01h 0x00 18h 0x40 0Dh 0x01 00h 0x80 17h 0x00 0Ch 0x00 16h 0x00 0Bh 0x00 15h 0x00 08h 0x00 14h 0x00 07h 0x00 13h 0x00 06h 0x00 Document Number: 001-86213 Rev. *C Page 14 of 39

FM33256B Table 7. Register Description Address Description 1Dh Alarm – Month D7 D6 D5 D4 D3 D2 D1 D0 M 0 0 10 Month Month.3 Month.2 Month.1 Month.0 Contains the alarm value for the month and the mask bit to select or deselect the Month value. M Match. Setting this bit to ‘0’ causes the Month value to be used in the alarm match logic. Setting this bit to ‘1’ causes the match circuit to ignore the Month value. Battery-backed, read/write. 1Ch Alarm – Date D7 D6 D5 D4 D3 D2 D1 D0 M 0 10 date.1 10 date.0 Date.3 Date.2 Date.1 Date.0 Contains the alarm value for the date and the mask bit to select or deselect the Date value. M Match: Setting this bit to ‘0’ causes the Date value to be used in the alarm match logic. Setting this bit to ‘1’ causes the match circuit to ignore the Date value. Battery-backed, read/write. 1Bh Alarm – Hours D7 D6 D5 D4 D3 D2 D1 D0 M 0 10 hours.1 10 hours.0 Hours.3 Hours.2 Hours.1 Hours.0 Contains the alarm value for the hours and the mask bit to select or deselect the Hours value. M Match: Setting this bit to ‘0’ causes the Hours value to be used in the alarm match logic. Setting this bit to ‘1’ causes the match circuit to ignore the Hours value. Battery-backed, read/write. 1Ah Alarm – Minutes D7 D6 D5 D4 D3 D2 D1 D0 M 10 min.2 10 min.1 10 min.0 Min.3 Min.2 Min.1 Min.0 Contains the alarm value for the minutes and the mask bit to select or deselect the Minutes value M Match: Setting this bit to ‘0’ causes the Minutes value to be used in the alarm match logic. Setting this bit to ‘1’ causes the match circuit to ignore the Minutes value. Battery-backed, read/write. 19h Alarm – Seconds D7 D6 D5 D4 D3 D2 D1 D0 M 10 sec.2 10 sec.1 10 sec.0 Seconds.3 Seconds.2 Seconds.1 Seconds.0 Contains the alarm value for the seconds and the mask bit to select or deselect the Seconds value. M Match: Setting this bit to ‘0’ causes the Seconds value to be used in the alarm match logic. Setting this bit to ‘1’ causes the match circuit to ignore the Seconds value. Battery-backed, read/write. 18h Companion Control D7 D6 D5 D4 D3 D2 D1 D0 SNL AL/SW F1 F0 VBC FC VTP1 VTP0 SNL Serial Number Lock: Setting to a ‘1’ makes registers 10h to 17h and SNL read-only. SNL cannot be cleared once set to ‘1’. Nonvolatile, read/write. AL/SW Alarm/Square Wave Select: When set to ‘1’, the alarm match drives the ACS pin as well as the AF flag. When set to ‘0’, the selected Square Wave Freq will be driven on the ACS pin, and an alarm match only sets the AF flag. Nonvolatile, read/write. Document Number: 001-86213 Rev. *C Page 15 of 39

FM33256B Table 7. Register Description (continued) Address Description F(1:0) Square Wave Frequency Select: These bits select the frequency on the ACS pin when the CAL and AL/SW bits are both ‘0’. Nonvolatile. Setting F(1:0) 1 Hz 00 (default) 512 Hz 01 4096 Hz 10 32768 Hz 11 VBC VBAK Charger Control: Setting VBC to ‘1’ (and FC = ‘0’) causes a 80 µA (1 mA if FC = ‘1’) trickle charge current to be supplied on V . Clearing VBC to ‘0’ disables the charge current. Battery-backed, read/write. BAK VBC FC Trickle charge current 0 X Disabled 1 0 80 µA 1 1 1 mA FC Fast Charge: Setting FC to ‘1’ (and VBC = ‘1’) causes a ~1 mA trickle charge current to be supplied on V . BAK Clearing VBC to ‘0’ disables the charge current. Battery-backed, read/write. VTP(1:0) VTP Select. These bits control the reset trip point for the low V reset function. Nonvolatile, read/write. DD VTP VTP1 VTP0 2.60 V 0 0 (factory default) 2.75 V 0 1 2.90 V 1 0 3.00 V 1 1 17h Serial Number Byte 7 D7 D6 D5 D4 D3 D2 D1 D0 SN.63 SN.62 SN.61 SN.60 SN.59 SN.58 SN.57 SN.56 16h Serial Number Byte 6 D7 D6 D5 D4 D3 D2 D1 D0 SN.55 SN.54 SN.53 SN.52 SN.51 SN.50 SN.49 SN.48 15h Serial Number Byte 5 D7 D6 D5 D4 D3 D2 D1 D0 SN.47 SN.46 SN.45 SN.44 SN.43 SN.42 SN.41 SN.40 14h Serial Number Byte 4 D7 D6 D5 D4 D3 D2 D1 D0 SN.39 SN.38 SN.37 SN.36 SN.35 SN.34 SN.33 SN.32 13h Serial Number Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 SN.31 SN.30 SN.29 SN.28 SN.27 SN.26 SN.25 SN.24 Document Number: 001-86213 Rev. *C Page 16 of 39

FM33256B Table 7. Register Description (continued) Address Description 12h Serial Number Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 SN.23 SN.22 SN.21 SN.20 SN.19 SN.18 SN.17 SN.16 11h Serial Number Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 SN.15 SN.14 SN.13 SN.12 SN.11 SN.10 SN.9 SN.8 10h Serial Number Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 SN.7 SN.6 SN.5 SN.4 SN.3 SN.2 SN.1 SN.0 All serial number bytes are read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 0Fh Event Counter Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 EC.15 EC.14 EC.13 EC.12 EC.11 EC.10 EC.9 EC.8 Event Counter Byte 1. Increments on programmed edge event on CNT input. Nonvolatile when NVC = ‘1’, Battery-backed when NVC = ‘0’, read/write. 0Eh Event Counter Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 EC.7 EC.6 EC.5 EC.4 EC.3 EC.2 EC.1 EC.0 Event Counter Byte 0. Increments on programmed edge event on CNT input. Nonvolatile when NVC = ‘1’, Battery-backed when NVC = ‘0’, read/write. 0Dh Event Counter Control D7 D6 D5 D4 D3 D2 D1 D0 NVC - - - RC WC POLL CP NVC Nonvolatile/Volatile Counter: Setting this bit to ‘1’ makes the counter nonvolatile and counter operates only when V is greater than V . Setting this bit to ‘0’ makes the counter volatile, which allows counter operation under DD TP V or V power. If the NVC bit is changed, the counter value is not valid. Nonvolatile, read/write. BAK DD RC Read Counter. Setting this bit to ‘1’ takes a snapshot of the two counter bytes allowing the system to read the values without missing count events. The RC bit will be automatically cleared. WC Write Counter. Setting this bit to a ‘1’ allows the user to write the counter bytes. While WC = ‘1’, the counter is blocked from count events on the CNT pin. The WC bit must be cleared by the user to activate the counter. POLL Polled Mode: When POLL = ‘1’, the CNT pin is sampled for 30 µs every 125 ms. If POLL is set, the NVC bit is internally cleared and the CP bit is set to detect a rising edge. The RTC oscillator must be enabled (OSCEN = ‘0’) to operate in polled mode. When POLL = ‘0’, CNT pin is continuously active. Nonvolatile, read/write. CP The CNT pin detects falling edges when CP = ‘0’, rising edges when CP = ‘1’. Nonvolatile, read/write. Document Number: 001-86213 Rev. *C Page 17 of 39

FM33256B Table 7. Register Description (continued) Address Description 0Ch Watchdog Control D7 D6 D5 D4 D3 D2 D1 D0 WDE - - WDET4 WDET3 WDET2 WDET1 WDET0 WDE Watchdog Enable: When WDE = ‘1’, a watchdog timer fault will cause the RST signal to go active. When WDE = ‘0’ the timer runs but has no effect on the RST pin. Nonvolatile, read/write. WDET(4:0) Watchdog EndTime: Sets the ending time for the watchdog window timer with 60 ms (min.) resolution. The window timer allows independent leading and trailing edges (start and end of window) to be set. New watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). To save power (disable timer circuit), the EndTime may be set to all zeroes. Nonvolatile, read/write. Watchdog EndTime WDET4 WDET3 WDET2 WDET1 WDET0 Disables Timer 0 0 0 0 0 (min.) (max.) 60 ms 200 ms 0 0 0 0 1 120 ms 400 ms 0 0 0 1 0 180 ms 600 ms 0 0 0 1 1 . . . . 1200 ms 4000 ms 1 0 1 0 0 1260 ms 4200 ms 1 0 1 0 1 1320 ms 4400 ms 1 0 1 1 0 . . . . 1740 ms 5800 ms 1 1 1 0 1 1800 ms 6000 ms 1 1 1 1 0 1860 ms 6200 ms 1 1 1 1 1 Document Number: 001-86213 Rev. *C Page 18 of 39

FM33256B Table 7. Register Description (continued) Address Description 0Bh Watchdog Control D7 D6 D5 D4 D3 D2 D1 D0 - - - WDST4 WDST3 WDST2 WDST1 WDST0 WDST(4:0) Watchdog StartTime. Sets the starting time for the watchdog window timer with 25 ms (max.) resolution. The window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog timer settings are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). Nonvolatile, read/write. Watchdog StartTime WDST4 WDST3 WDST2 WDST1 WDST0 0 ms (default) 0 0 0 0 0 (min.) (max.) 7.5 ms 25 ms 0 0 0 0 1 15 ms 50 ms 0 0 0 1 0 22.5 ms 75 ms 0 0 0 1 1 . . . . 150 ms 500 ms 1 0 1 0 0 157.5 ms 525 ms 1 0 1 0 1 165 ms 550 ms 1 0 1 1 0 . . . . 217.5 ms 725 ms 1 1 1 0 1 225 ms 750 ms 1 1 1 1 0 232.5 ms 775 ms 1 1 1 1 1 0Ah Watchdog Restart D7 D5 D4 D3 D2 D1 D0 - - - WR3 WR2 WR1 WR0 WR(3:0) Watchdog Restart. Writing a pattern 1010b to WR(3:0) restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR(3:0) has no effect on the watchdog. Write-only. 09h Watchdog Flags D7 D6 D5 D4 D3 D2 D1 D0 EWDF - POR LB - - - - EWDF Early Watchdog Timer Fault Flag: When a watchdog restart occurs too early (before the programmed watchdog StartTime), the RST pin is driven LOW and this flag is set. It must be cleared by the user. Note that both EWDF and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed, read/write. LWDF Late Watchdog Timer Fault Flag: When either a watchdog restart occurs too late (after the programmed watchdog EndTime) or no restart occurs, the RST pin is driven LOW and this flag is set. It must be cleared by the user. Note that both LWDF and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed, read/write. Document Number: 001-86213 Rev. *C Page 19 of 39

FM33256B Table 7. Register Description (continued) Address Description POR Power-On Reset: When the RST signal is activated by V < V , the POR bit will be set to ‘1’. A manual reset will DD TP not set this flag. Note that one or both of the watchdog flags and the POR flag could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed, read/write. (internally set, user must clear bit). LB Low Backup: If the V source drops to a voltage level insufficient to operate the RTC/alarm when V < V , BAK DD BAK this bit will be set to ‘1’. All registers need to be re-initialized since the battery-backed register values should be treated as unknown. The user should clear it to ‘0’ when initializing the system. Battery-backed. Read/Write (internally set, user must clear bit). 08h Timekeeping – Years D7 D6 D5 D4 D3 D2 D1 D0 10 year.3 10 year.2 10 year.1 10 year.0 Year.3 Year.2 Year.1 Year.0 Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Battery-backed, read/write. 07h Timekeeping – Months D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10 Month Month.3 Month.2 Month.1 Month.0 Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Battery-backed, read/write. 06h Timekeeping – Date of the month D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 date.1 10 date.0 Date.3 Date.2 Date.1 Date.0 Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Battery-backed, read/write. 05h Timekeeping – Day of the week D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day.2 Day.1 Day.0 Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date. Battery-backed, read/write. 04h Timekeeping – Hours D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 hours.1 10 hours.0 Hours.3 Hours.2 Hours.1 Hours.0 Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Battery-backed, read/write. Document Number: 001-86213 Rev. *C Page 20 of 39

FM33256B Table 7. Register Description (continued) Address Description 03h Timekeeping – Minutes D7 D6 D5 D4 D3 D2 D1 D0 0 10 min.2 10 min.1 10 min.0 Min.3 Min.2 Min.1 Min.0 Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. 02h Timekeeping - Seconds D7 D6 D5 D4 D3 D2 D1 D0 0 10 sec.2 10 sec.1 10 sec.0 Seconds.3 Seconds.2 Seconds.1 Seconds.0 Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. 01h CAL/Control D7 D6 D5 D4 D3 D2 D1 D0 - - CALS CAL.4 CAL.3 CAL.2 CAL.1 CAL.0 CALS Calibration Sign: Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. This bit can be written only when CAL = ‘1’. Nonvolatile, read/write. CAL(4:0) Calibration Code: These five bits control the calibration of the clock. These bits can be written only when CAL = ‘1’. Nonvolatile, read/write. 00h RTC/Alarm Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN AF CF AEN Reserved CAL W R OSCEN Oscillator Enable. When set to '1', the oscillator is halted. When set to '0', the oscillator runs. Disabling the oscillator can save battery power during storage. On a power-up without a V source or on a power-up after a BAK V source has been applied, this bit is internally set to '1', which turns off the oscillator. Battery-backed, BAK read/write. AF Alarm Flag: This bit is set to ‘1’ when the time and date match the values stored in the alarm registers with the Match bit(s) = ‘0’. The user must clear it to '0'. Battery-backed. (internally set, user must clear bit) CF Century Overflow Flag: This bit is set to a ‘1’ when the values in the years register overflows from 99 to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new century information as needed. The user must clear the CF bit to '0'. Battery-backed. (internally set, user must clear bit) AEN Alarm Enable: This bit enables the alarm function. When AEN is set (and CAL cleared), the ACS pin operates as an active-low alarm. The state of the ACS pin is detailed in Table2. When AEN is cleared, no new alarm events that set the AF bit will be generated. Clearing the AEN bit does not automatically clear AF. Battery-backed. CAL Calibration Setting: When CAL is set to ‘1’, the clock enters calibration mode. When CAL is set to ‘0’, the clock operates normally, and the ACS pin is controlled by the RTC alarm. Battery-backed, read/write. W Write Time. Setting the W bit to ‘1’ freezes updates of the user timekeeping registers. The user can then write them with updated values. Setting the W bit to ‘0’ causes the contents of the time registers to be transferred to the timekeeping counters. Battery-backed, read/write. Document Number: 001-86213 Rev. *C Page 21 of 39

FM33256B Table 7. Register Description (continued) Address Description R Read Time. Setting the R bit to '1' copies a static image of the timekeeping core and places it into the user registers. The user can then read them without concerns over changing values causing system errors. The R bit going from ‘0’ to ‘1’ causes the timekeeping capture, so the bit must be returned to ‘0’ prior to reading again. Battery-backed, read/write. Reserved Reserved bits. Do not use. Should remain set to ‘0’. Document Number: 001-86213 Rev. *C Page 22 of 39

FM33256B Serial Peripheral Interface – SPI Bus selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. The FM33256B employs a serial peripheral interface (SPI) bus. Note A new instruction must begin with the falling edge of CS. It is specified to operate at speeds up to 16 MHz. This high-speed Therefore, only one opcode can be issued for each active Chip serial bus provides high-performance serial communication to an Select cycle. SPI master. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the Serial Clock (SCK) port using ordinary port pins for microcontrollers that do not. The The Serial Clock is generated by the SPI master and the FM33256B operates in SPI Mode 0 and 3. communication is synchronized with this clock after CS goes SPI Overview LOW. The SPI is a four-pin interface with Chip Select (CS), Serial Input The FM33256B enables SPI modes 0 and 3 for data (SI), Serial Output (SO), and Serial Clock (SCK) pins. communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are The SPI is a synchronous serial interface, which uses clock and issued on the falling edge. Therefore, the first rising edge of SCK data pins for memory access and supports multiple devices on signifies the arrival of the first bit (MSB) of an SPI instruction on the data bus. A device on the SPI bus is activated using the CS the SI pin. Further, all data inputs and outputs are synchronized pin. with SCK. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In Data Transmission (SI/SO) both of these modes, data is clocked into the F-RAM on the rising The SPI data bus consists of two lines, SI and SO, for serial data edge of SCK starting from the first rising edge after CS goes communication. SI is also referred to as Master Out Slave In active. (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while The SPI protocol is controlled by opcodes. These opcodes the slave responds through the SO pin. Multiple slave devices specify the commands from the bus master to the slave device. may share the SI and SO lines as described earlier. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and The FM33256B has two separate pins for SI and SO, which can data are then transferred. The CS must go inactive after an be connected with the master as shown in Figure 13. operation is complete and before a new opcode can be issued. For a microcontroller that has no dedicated SPI bus, a The commonly used terms in the SPI protocol are as follows: general-purpose port may be used. To reduce hardware resources on the controller, it is possible to connect the two data SPI Master pins (SI, SO) together. Figure 14 shows such a configuration, The SPI master device controls the operations on an SPI bus. which uses only three pins. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the Most Significant Bit (MSB) master may select any of the slave devices using the CS pin. All The SPI protocol requires that the first bit to be transmitted is the of the operations must be initiated by the master activating a Most Significant Bit (MSB). This is valid for both address and slave device by pulling the CS pin of the slave LOW. The master data transmission. also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. The 256-Kbit serial F-RAM requires a 2-byte address for any read or write operation. Because the address is only 15 bits, the SPI Slave upper bit which is fed in is ignored by the device. Although this bit is ‘don’t care’, Cypress recommends that this bit be set to ‘0’ The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an input from the SPI to enable seamless transition to higher memory densities. master and all the communication is synchronized with this Serial Opcode clock. An SPI slave never initiates a communication on the SPI bus and acts only on the instruction from the master. After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. The FM33256B operates as an SPI slave and may share the SPI FM33256B uses the standard opcodes for memory accesses. bus with other SPI slave devices. Invalid Opcode Chip Select (CS) If an invalid opcode is received, the opcode is ignored and the To select any slave device, the master needs to pull down the device ignores any additional serial data on the SI pin until the corresponding CS pin. Any instruction can be issued to a slave next falling edge of CS, and the SO pin remains tristated. device only while the CS pin is LOW. When the device is not Document Number: 001-86213 Rev. *C Page 23 of 39

FM33256B Status Register The FM33256B has an 8-bit Status Register. The bits in the Status Register are used to configure the device. These bits are described in Table 10 on page 26. Figure 13. System Configuration with SPI Port SCK MOSI MISO SCK SI SO SCK SI SO SPI FM33256B FM33256B Microcontroller CS CS CS1 CS2 Figure 14. System Configuration without SPI Port P1.0 P1.1 SCK SI SO Microcontroller FM33256B CS P1.2 SPI Modes The FM33256B may be driven by a microcontroller with its SPI Figure 15. SPI Mode 0 peripheral running in either of the following two modes: CS ■SPI Mode 0 (CPOL = 0, CPHA = 0) 0 1 2 3 4 5 6 7 ■SPI Mode 3 (CPOL = 1, CPHA = 1) SCK For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first SI 7 6 5 4 3 2 1 0 rising edge after the clock toggles is considered. The output data is available on the falling edge of SCK. MSB LSB The two SPI modes are shown in Figure 15 on page 24 and Figure 16 on page 24. The status of the clock when the bus master is not transferring data is: Figure 16. SPI Mode 3 ■SCK remains at 0 for Mode 0 CS ■SCK remains at 1 for Mode 3 0 1 2 3 4 5 6 7 The device detects the SPI mode from the status of the SCK pin SCK when the device is selected by bringing the CS pin LOW. If the SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if the SCK pin is HIGH, it works in SPI Mode3. SI 7 6 5 4 3 2 1 0 MSB LSB Document Number: 001-86213 Rev. *C Page 24 of 39

FM33256B Power Up to First Access set this bit. The WEL bit will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, a WRPC or a WRITE The FM33256B is not accessible for a t time after power-up. PU operation. This prevents further writes to the Status Register or Users must comply with the timing parameter, t , which is the PU the F-RAM array without another WREN command. Figure 17 minimum time from V (min) to the first CS LOW. DD illustrates the WREN command bus configuration. Command Structure Figure 17. WREN Bus Configuration There are eight commands, called opcodes, that can be issued by the bus master to the FM33256B. They are listed in Table1. CS These opcodes control the functions performed by the memory and processor companion. 0 1 2 3 4 5 6 7 Table 8. Opcode Commands SCK Name Description Opcode SI 0 0 0 0 0 1 1 0 WREN Set write enable latch 0000 0110b WRDI Reset write enable latch 0000 0100b HI-Z SO RDSR Read Status Register 0000 0101b WRSR Write Status Register 0000 0001b WRDI - Reset Write Enable Latch READ Read memory data 0000 0011b The WRDI command disables all write activity by clearing the WRITE Write memory data 0000 0010b Write Enable Latch. The user can verify that writes are disabled RDPC Read Processor Companion 0001 0011b by reading the WEL bit in the Status Register and verifying that WRPC Write Processor Companion 0001 0010b WEL is equal to ‘0’. Figure 18 illustrates the WRDI command bus configuration. WREN - Set Write Enable Latch The FM33256B will power up with writes disabled. The WREN Figure 18. WRDI Bus Configuration command must be issued before any write operation. Sending the WREN opcode allows the user to issue subsequent opcodes CS for write operations. These include writing the Status Register 0 1 2 3 4 5 6 7 (WRSR) and writing the memory (WRITE). SCK Sending the WREN opcode causes the internal Write Enable Latch to be set. A flag bit in the Status Register, called WEL, SI 0 0 0 0 0 1 0 0 indicates the state of the latch. WEL = ’1’ indicates that writes are permitted. Attempting to write the WEL bit in the Status Register HI-Z has no effect on the state of this bit – only the WREN opcode can SO Document Number: 001-86213 Rev. *C Page 25 of 39

FM33256B Status Register and Write Protection is organized as follows. (The default value shipped from the factory for bits 0-4, bit 6 is ‘0’ and bit 5 is ‘1’ in the Status The write protection features of the FM33256B are multi-tiered Register). and are enabled through the status register. The Status Register Table 9. Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X (0) X (1) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0) Table 10. Status Register Bit Definition Bit Definition Description Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write Enable WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEL = '1' --> Write enabled WEL = '0' --> Write disabled Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 11 on page 26. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 11 on page 26. Bit 4-5 Don’t care These bits are non-writable and always return ‘0’ upon read. Bit 6 Don’t care This bit is non-writable and always returns ‘1’ upon read. Bit 7 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 0, bits 4-5 bit, bit 7 are fixed at ‘0’ and bit 6 is fixed at ‘1’; none The BP1 and BP0 bits and the Write Enable Latch are the only of these bits can be modified. Note that bit 0 (“Ready or Write in mechanisms that protect the memory from writes. The remaining progress” bit in serial flash and EEPROM) is unnecessary, as the write protection features protect inadvertent changes to the block F-RAM writes in real-time and is never busy, so it reads out as a protect bits. ‘0’. BP1 and BP0 control the software write-protection features RDSR - Read Status Register and are nonvolatile bits. The WEL flag indicates the state of the Write Enable Latch. Attempting to directly write the WEL bit in The RDSR command allows the bus master to verify the the Status Register has no effect on its state. This bit is internally contents of the Status Register. Reading the status register set and cleared via the WREN and WRDI commands, provides information about the current state of the respectively. write-protection features. Following the RDSR opcode, the BP1 and BP0 are memory block write protection bits. They FM33256B will return one byte with the contents of the Status specify portions of memory that are write-protected as shown in Register. Table4. WRSR - Write Status Register Table 11. Block Memory Write Protection The WRSR command allows the SPI bus master to write into the Status Register and change the write protect configuration by BP1 BP0 Protected Address Range setting the BP0 and BP1 bits as required. Before sending the 0 0 None WRSR command, the user must send a WREN command to 0 1 6000h to 7FFFh (upper 1/4) enable writes. Executing a WRSR command is a write operation 1 0 4000h to 7FFFh (upper 1/2) and therefore, clears the Write Enable Latch. 1 1 0000h to 7FFFh (all) Document Number: 001-86213 Rev. *C Page 26 of 39

FM33256B Figure 19. RDSR Bus Configuration CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode SI 0 0 0 0 0 1 0 1 0 Data HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Figure 20. WRSR Bus Configuration (WREN not shown) CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode Data SI 0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X MSB LSB HI-Z SO RDPC - Read Processor Companion WRPC - Write Processor Companion The RDPC command allows the bus master to verify the The WRPC command is used to set companion control settings. contents of the Processor Companion registers. Following the A WREN command is required prior to sending the WRPC RDPC opcode, a single-byte register address is sent. The command. Following the WRPC opcode, a single-byte register FM33256B will then return one or more bytes with the contents address is sent. The controller then drives one or more bytes to of the companion registers. When reading multiple data bytes, program the companion registers. When writing multiple data the internal register address will wrap around to 00h after 1Dh is bytes, the internal register address will wrap around to 00h after reached. 1Dh is reached. The rising edge of CS terminates a WRPC operation. See Figure 22. Figure 21. Processor Companion Read CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode SI 0 0 0 1 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB Data HI-Z SO D7 D6 D5 D4 D3 D2 D1D0 MSB LSB Document Number: 001-86213 Rev. *C Page 27 of 39

FM33256B Figure 22. Processor Companion Write (WREN not shown) CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode Data SI 0 0 0 1 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSBMSB LSB HI-Z SO Memory Operation operations. F-RAM memories do not have page buffers because each byte is written to the F-RAM array immediately after it is The SPI interface, which is capable of a high clock frequency, clocked in (after the eighth clock). This allows any number of highlights the fast write capability of the F-RAM technology. bytes to be written without page buffer delays. Unlike serial flash and EEPROMs, the FM33256B can perform Note If the power is lost in the middle of the write operation, only sequential writes at bus speed. No page register is needed and the last completed byte will be written. any number of sequential writes may be performed. Read Operation Write Operation After the falling edge of CS, the bus master can issue a READ All writes to the memory begin with a WREN opcode with CS opcode. Following the READ command is a two-byte address being asserted and deasserted. The next opcode is WRITE. The containing the 15-bit address (A14-A0) of the first byte of the WRITE opcode is followed by a two-byte address containing the read operation. The upper bit of the address is ignored. After the 15-bit address (A14-A0) of the first data byte to be written into opcode and address are issued, the device drives out the read the memory. The upper bit of the two-byte address is ignored. data on the next eight clocks. The SI input is ignored during read Subsequent bytes are data bytes, which are written sequentially. data bytes. Subsequent bytes are data bytes, which are read out Addresses are incremented internally as long as the bus master sequentially. Addresses are incremented internally as long as continues to issue clocks and keeps CS LOW. If the last address the bus master continues to issue clocks and CS is LOW. If the of 7FFFh is reached, the counter will roll over to 0000h. Data is last address of 7FFFh is reached, the counter will roll over to written MSB first. The rising edge of CS terminates a write 0000h. Data is read MSB first. The rising edge of CS terminates operation. A write operation is shown in Figure 23. a read operation and tristates the SO pin. A read operation is Note When a burst write reaches a protected block address, the shown in Figure 24. automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. EEPROMs use page buffers to increase their write throughput. This compensates for the technology's inherently slow write Figure 23. Memory Write (WREN not shown) Operation CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 ~~ SCK Opcode 15-bit Address Data ~~ SI 0 0 0 0 0 0 1 0 X A14A13A12A11A10A9 A8 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSBMSB LSB HI-Z SO Document Number: 001-86213 Rev. *C Page 28 of 39

FM33256B Figure 24. Memory Read Operation CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 ~~ SCK Opcode 15-bit Address ~~ SI 0 0 0 0 0 0 1 1 X A14A13A12A11A10 A9 A8 A3 A2 A1 A0 MSB LSB Data HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Document Number: 001-86213 Rev. *C Page 29 of 39

FM33256B Maximum Ratings Surface mount lead soldering temperature (3 seconds) .........................................+260 °C Exceeding maximum ratings may shorten the useful life of the DC output current device. These user guidelines are not tested. (1 output at a time, 1s duration) ..................................15 mA Storage temperature ................................–55 °C to +125 °C Electrostatic Discharge Voltage Maximum accumulated storage time Human Body Model (JEDEC Std JESD22-A114-E) ........... 4.5 kV At 125 °C ambient temperature .................................1000 h Charged Device Model (JEDEC Std JESD22-C101-C) .....1.25 kV At 85 °C ambient temperature ................................10 Years Machine Model (JEDEC Std JESD22-A115-A) .........................200 Ambient temperature with power applied .................................. –55 °C to +125 °C Latch-up current ..................................................> ±100 mA Operating Range Supply voltage on V relative to V .........–1.0 V to +5.0 V DD SS Input voltage ...........–1.0 V to +5.0 V and V < V + 1.0 V Range Ambient Temperature (T ) V IN DD A DD Backup supply voltage..................................–1.0 V to +4.5 V Industrial –40 °C to +85 °C 2.7 V to 3.6 V DC voltage applied to outputs in High-Z state ....................................–0.5 V to V + 0.5 V DD Transient voltage (< 20 ns) on any pin to ground potential .................–2.0 V to V + 2.0 V DD Package power dissipation capability (T = 25 °C) .................................................1.0 W A DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit V [3] Power supply 2.7 – 3.6 V DD I V supply current SCK toggling f = 1 MHz – – 1.1 mA DD DD SCK (VBC = ‘0’) between V – 0.3 DD f = 16 MHz – – 16.0 mA V and V , other SCK SS inputs V or V – 0.3 V. SS DD SO = Open I V standby current CS = V . All other inputs V or V . – – 150 μA SB DD DD SS DD Trickle Charger Off (VBC = ‘0’) V [4] RTC backup voltage T = +25 °C to +85 °C 1.55 – 3.75 V BAK A T = –40 °C to +25 °C 1.90 – 3.75 V A I RTC backup current V < V , oscil- T = +25 °C, V = 3.0 V – – 1.4 μA BAK DD SW A BAK lator running, CNT T = +85 °C, V = 3.0 V – – 2.0 μA at V . A BAK BAK T = +25 °C, V = 2.0 V – – 1.15 μA A BAK T = +85 °C, V = 2.0 V – – 1.65 μA A BAK I [5] Trickle Charge Current Fast Charge Off (FC = ‘0’) 50 – 200 μA BAKTC with V = 0 V BAK Fast Charge On (FC = ‘1’) 200 – 2500 μA Notes 2. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested. 3. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 4. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 5. VBAK will source current when trickle charge is enabled (VBC bit = ‘1’), VDD > VBAK, and VBAK < VBAK(max). Document Number: 001-86213 Rev. *C Page 30 of 39

FM33256B DC Electrical Characteristics (continued) Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit I [6] V Quiescent Current – – 70 μA QTC DD (VBC = ‘1’) I [7] V Quiescent Current – – 30 μA QWD DD (WDE = ‘1’) V V Trip Point Voltage, RST is asserted active when V < V . 2.53 2.6 2.72 V TP0 DD DD TP VTP(1:0) = 00b V V Trip Point Voltage, RST is asserted active when V < V . 2.68 2.75 2.87 V TP1 DD DD TP VTP(1:0) = 01b V V Trip Point Voltage, RST is asserted active when V < V . 2.78 2.9 2.99 V TP2 DD DD TP VTP(1:0) = 10b V V Trip Point Voltage, RST is asserted active when V < V . 2.91 3.0 3.15 V TP3 DD DD TP VTP(1:0) = 11b V [8] V for valid RST I = 80 μA at V V > V min 0 – – V RST DD OL OL BAK BAK V < V min 1.6 – – V BAK BAK V Battery Switchover voltage CS = V . 2.0 – 2.7 V SW DD All other inputs V or V . SS DD I Input leakage current V < V < V Does not apply to PFI, RST, – – ±1 μA LI SS IN DD. X1, or X2 I Output leakage current V < V < V . Does not apply to RST, X1, – – ±1 μA LO SS OUT DD or X2 V [9] Input LOW voltage All inputs except as listed – 0.3 – 0.3 × V V IL DD below CNT battery-backed – 0.3 – 0.5 V (V < V ) DD SW CNT (V > V ) – 0.3 – 0.8 V DD SW V Input HIGH voltage All inputs except as listed 0.7 × V – V + 0.3 V IH DD DD below CNT battery-backed V – 0.5 – V + 0.3 V BAK BAK (V < V ) DD SW CNT (V > V ) 0.7 × V – V + 0.3 V DD SW DD DD PFI – – V + 0.3 V DD Notes 6. This is the VDD supply current contributed by enabling the trickle charger circuit, and does not account for IBAKTC. 7. This is the VDD supply current contributed by enabling the watchdog circuit, WDE = ‘1’ and WDET set to a non-zero value. 8. The minimum VDD to guarantee the level of RST remains a valid VOL level. 9. Includes RST input detection of external reset condition to trigger driving of RST signal by FM33256B. Document Number: 001-86213 Rev. *C Page 31 of 39

FM33256B DC Electrical Characteristics (continued) Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit V Output HIGH voltage I = –2 mA V – 0.8 – – V OH OH DD (SO, PFO) V Output LOW voltage I = 3 mA – – 0.4 V OL OL R Pull-up resistance for RST 50 – 400 kΩ RST inactive V Power Fail Input Reference 1.475 1.50 1.525 V PFI Voltage V Power Fail Input (PFI) – – 100 mV HYS Hysteresis (Rising) Data Retention and Endurance Parameter Description Test condition Min Max Unit T Data retention T = 85 °C 10 – Years DR A T = 75 °C 38 – A T = 65 °C 151 – A NV Endurance Over operating temperature 1014 – Cycles C Capacitance Parameter [10] Description Test Conditions Typ Max Unit C Input/Output pin capacitance T = 25 °C, f = 1 MHz, V = V (typ) – 8 pF IO A DD DD C X1, X2 Crystal pin Capacitance 12 – pF XTL C [11] Max. Allowable Capacitance on – 100 pF CNT CNT (polled mode) Thermal Resistance Parameter Description Test Conditions 14-pin SOIC Unit Θ Thermal resistance Test conditions follow standard test methods 81 °C/W JA (junction to ambient) and procedures for measuring thermal Θ Thermal resistance impedance, per EIA / JESD51. 31 °C/W JC (junction to case) AC Test Conditions Input pulse levels .................................10% and 90% of V DD Input rise and fall times ...................................................5 ns Input and output timing reference levels ................0.5 × V DD Output load capacitance ..............................................30 pF Notes 10.This parameter is characterized and not 100% tested. 11.The crystal attached to the X1/X2 pins must be rated as 6 pF/12.5 pF. Document Number: 001-86213 Rev. *C Page 32 of 39

FM33256B Supervisor Timing Over the Operating Range Parameter Description Min Max Units tRPU[12] RST active (LOW) after VDD > VTP 30 100 ms tRNR[13] RST response time to VDD < VTP (noise filter) 7 25 μs tVR[13, 14] VDD power-up ramp rate 50 100,000 μs/V tVF[13, 14] VDD power-down ramp rate 100 - μs/V tWDST[15] Watchdog StartTime 0.3 × tDOG1 tDOG1 ms tWDET[15] Watchdog EndTime tDOG2 3.3 × tDOG2 ms f Frequency of event counter 0 1 kHz CNT Figure 25. RST Timing t t V VF VR DD V TP V RST t RNR t RPU RST Notes 12.The RST pin will drive LOW for this length of time after the internal reset circuit is activated due to a watchdog, low voltage, or manual reset event. 13.This parameter is characterized and not 100% tested. 14.Slope measured at any point on VDD waveform. 15.tDOG1 is the programmed StartTime and tDOG2 is the programmed EndTime in registers 0Bh and 0Ch, VDD > VTP, and tRPU satisfied. The StartTime has a resolution of 25 ms. The EndTime has a resolution of 60 ms. Document Number: 001-86213 Rev. *C Page 33 of 39

FM33256B AC Switching Characteristics Over the Operating Range Parameters [16] Description Min Max Unit Cypress Alt. Parameter Parameter f – SCK clock frequency 0 16 MHz SCK t – Clock HIGH time 28 – ns CH t – Clock LOW time 28 – ns CL t t Chip select setup 10 – ns CSU CSS t t Chip select hold 10 – ns CSH CSH t [17, 18] t Output disable time – 20 ns OD HZCS t t Output data valid time – 24 ns ODV CO t – Output hold time 0 – ns OH t – Deselect time 90 – ns D t [19] – Data in rise time – 50 ns R t [19] – Data in fall time – 50 ns F t t Data setup time 6 – ns SU SD t t Data hold time 6 – ns H HD Figure 26. Synchronous Data Timing (Mode 0) tD CS tCSU tCH tCL tCSH SCK tSU tH SI VALID IN VALID IN VALID IN tODV tOH tOD HI-Z HI-Z SO Notes 16.Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 32. 17.tOD is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state 18.This parameter is characterized and not 100% tested. 19.Rise and fall times measured between 10% and 90% of waveform. Document Number: 001-86213 Rev. *C Page 34 of 39

FM33256B Ordering Information Package Operating Ordering Code Package Type Diagram Range FM33256B-G 51-85067 14-pin SOIC Industrial FM33256B-GTR 51-85067 14-pin SOIC All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 33 256 B - G TR Option: blank = Standard; TR = Tape and Reel Package Type: G = 14-pin SOIC; Die Revision: B Density: 256 = 256-Kbit SPI Processor Companion Cypress Document Number: 001-86213 Rev. *C Page 35 of 39

FM33256B Package Diagram Figure 27. 14-pin SOIC (150 Mils) Package Outline, 51-85067 51-85067 *E Document Number: 001-86213 Rev. *C Page 36 of 39

FM33256B Acronyms Document Conventions Units of Measure Acronym Description CPHA Clock Phase Symbol Unit of Measure CPOL Clock Polarity °C degree Celsius EEPROM Electrically Erasable Programmable Read-Only Hz hertz Memory kHz kilohertz EIA Electronic Industries Alliance kΩ kiloohm F-RAM Ferroelectric Random Access Memory Mbit megabit I/O Input/Output MHz megahertz JEDEC Joint Electron Devices Engineering Council μA microampere μF microfarad JESD JEDEC Standards μs microsecond LSB Least Significant Bit mA milliampere MSB Most Significant Bit ms millisecond NMI Non Maskable interrupt ns nanosecond RoHS Restriction of Hazardous Substances Ω ohm SPI Serial Peripheral Interface % percent SOIC Small Outline Integrated Circuit pF picofarad V volt W watt Document Number: 001-86213 Rev. *C Page 37 of 39

FM33256B Document History Page Document Title: FM33256B, 256-Kbit (32 K × 8) Integrated Processor Companion with F-RAM Document Number: 001-86213 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 3912947 GVCH 02/25/2013 New spec *A 4333078 GVCH 05/05/2014 Converted to Cypress standard format Crystal Type: Added use of 6 pF crystal Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Changed C parameter typ value from 25 pF to 12 pF. XTL Added Thermal Resistance table Removed Package Marking Scheme (top mark) Removed Ramtron revision history *B 4563141 GVCH 11/06/2014 Added related documentation hyperlink in page 1. *C 4872944 ZSK / PSR 08/05/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated Package Diagram: spec 51-85067 – Changed revision from *D to *E. Updated to new template. Document Number: 001-86213 Rev. *C Page 38 of 39

FM33256B Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory cypress.com/go/memory Technical Support PSoC cypress.com/go/psoc cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-86213 Rev. *C Revised August 5, 2015 Page 39 of 39 All products and company names mentioned in this document may be the trademarks of their respective holders.

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