FM31276/FM31278 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM Features ■Restriction of hazardous substances (RoHS) compliant ■Underwriters laboratory (UL) recognized ■64-Kbit/256-Kbit ferroelectric random access memory (F-RAM) ❐Logically organized as 8K × 8 (FM31276)/32K × 8 (FM31278) Functional Description ❐High-endurance 100 trillion (1014) read/writes ❐151-year data retention (See Data Retention and Endurance The FM31276/FM31278 device integrates F-RAM memory with on page 28) the most commonly needed functions for processor-based ❐NoDelay™ writes systems. Major features include nonvolatile memory, real time ❐Advanced high-reliability ferroelectric process clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose ■High Integration Device Replaces Multiple Parts comparator that can be used for a power-fail (NMI) interrupt or ❐Serial nonvolatile memory any other purpose. ❐Real time clock (RTC) The FM31276/FM31278 is a 64-Kbit/256-Kbit nonvolatile ❐Low voltage reset memory employing an advanced ferroelectric process. A ❐Watchdog timer ferroelectric random access memory or F-RAM is nonvolatile ❐Early power-fail warning/NMI and performs reads and writes similar to a RAM. This memory is ❐Two 16-bit event counter truly nonvolatile rather than battery backed. It provides reliable ❐Serial number with write-lock for security data retention for 151 years while eliminating the complexities, ■Real-time Clock/Calendar overhead, and system-level reliability problems caused by other ❐Backup current at 2 V: 1.15 A at +25 C nonvolatile memories. The FM31276/FM31278 is capable of ❐Seconds through centuries in BCD format supporting 1014 read/write cycles, or 100 million times more write ❐Tracks leap years through 2099 cycles than EEPROM. ❐Uses standard 32.768 kHz crystal (6 pF/12.5 pF) The real time clock (RTC) provides time and date information in ❐Software calibration BCD format. It can be permanently powered from an external ❐Supports battery or capacitor backup backup voltage source, either a battery or a capacitor. The ■Processor Companion timekeeper uses a common external 32.768 kHz crystal and ❐Active-low reset output for V and watchdog provides a calibration mode that allows software adjustment of DD ❐Programmable low-V reset trip point timekeeping accuracy. DD ❐Manual reset filtered and debounced The processor companion includes commonly needed CPU ❐Programmable watchdog timer support functions. Supervisory functions include a reset output ❐Dual Battery-backed event counter tracks system intrusions signal controlled by either a low V condition or a watchdog DD or other events timeout. RST goes active when V drops below a DD ❐Comparator for power-fail interrupt programmable threshold and remains active for 100 ms after ❐64-bit programmable serial number with lock V rises above the trip point. A programmable watchdog timer DD ■Fast 2-wire serial interface (I2C) runs from 100 ms to 3 seconds. The watchdog timer is optional, but if enabled it will assert the reset signal for 100 ms if not ❐Up to 1-MHz frequency restarted by the host before the timeout. A flag-bit indicates the ❐Supports legacy timings for 100 kHz and 400 kHz source of the reset. ❐RTC, Supervisor controlled via I2C interface ❐Device select pins for up to 4 memory devices A comparator on PFI compares an external input pin to the onboard 1.2 V reference. This is useful for generating a ■Low power consumption power-fail interrupt (NMI) but can be used for any purpose. The ❐1.5 mA active current at 1 MHz family also includes a programmable 64-bit serial number that ❐150 A standby current can be locked making it unalterable. Additionally it offers a dual battery-backed event counter that tracks the number of rising or ■Operating voltage: V = 4.0 V to 5.5 V DD falling edges detected on a dedicated input pin. ■Industrial temperature: –40 C to +85 C For a complete list of related documentation, click here. ■14-pin small outline integrated circuit (SOIC) package CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-86393 Rev. *E Revised February 16, 2018

FM31276/FM31278 Logic Block Diagram Document Number: 001-86393 Rev. *E Page 2 of 35

FM31276/FM31278 Contents Pinout ................................................................................4 RTC/Companion Write Operation .............................25 Pin Definitions ..................................................................4 RTC/Companion Read Operation .............................25 Functional Overview ........................................................5 Addressing FRAM Array Memory Architecture ...................................................5 in the FM31276/FM31278 Family .....................................25 Processor Companion .....................................................5 Maximum Ratings ...........................................................26 Processor Supervisor ..................................................5 Operating Range .............................................................26 Manual Reset ..............................................................6 DC Electrical Characteristics ........................................26 Reset Flags .................................................................6 Data Retention and Endurance .....................................28 Early Power Fail Comparator ......................................6 Capacitance ....................................................................28 Event Counter .............................................................7 Thermal Resistance ........................................................28 Serial Number .............................................................7 AC Test Loads and Waveforms .....................................28 Real-time Clock Operation ...............................................7 AC Test Conditions ........................................................28 Backup Power .............................................................8 Supervisor Timing ..........................................................29 Trickle Charger ............................................................8 AC Switching Characteristics .......................................30 Calibration ...................................................................9 Ordering Information ......................................................31 Crystal Oscillator .........................................................9 Ordering Code Definitions .........................................31 Layout Recommendations .............................................10 Package Diagram ............................................................32 Register Map ...................................................................13 Acronyms ........................................................................33 I2C Interface ....................................................................20 Document Conventions .................................................33 STOP Condition (P) ...................................................20 Units of Measure .......................................................33 START Condition (S) .................................................20 Document History Page .................................................34 Data/Address Transfer ..............................................20 Sales, Solutions, and Legal Information ......................35 Acknowledge/No-acknowledge .................................21 Worldwide Sales and Design Support .......................35 Slave Address ...........................................................21 Products ....................................................................35 Addressing Overview - Memory ................................22 PSoC® Solutions ......................................................35 Addressing Overview - RTC & Companion ...............22 Cypress Developer Community .................................35 Data Transfer ............................................................22 Technical Support .....................................................35 Memory Operation ..........................................................23 Memory Write Operation ...........................................23 Memory Read Operation ...........................................24 Document Number: 001-86393 Rev. *E Page 3 of 35

FM31276/FM31278 Pinout Figure 1. 14-pin SOIC pinout CNT1 1 14 VDD CNT2 2 13 SCL A0 3 12 SDA A1 4 11 X2 CAL/PFO 5 10 X1 RST 6 9 PFI VSS 7 8 VBAK Pin Definitions Pin Name I/O Type Description A1–A0 Input Device Select Address 1–0. These pins are used to select one of up to 4 devices of the same type on the same I2C bus. To select the device, the address value on the three pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended to be wire-OR'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. CNT1, CNT2 Input Event Counter Inputs. These battery-backed inputs increment counters when an edge is detected on the corresponding CNT pin. The polarity is programmable. These pins should not be left floating. Tie to ground if these pins are not used. X1, X2 Input/Output 32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1 and a DC mid-level to X2. These pins should be left unconnected if RTC is not used. RST Input/Output Reset. This active-low output is open drain with weak pull-up. It is also an input when used as a manual reset. This pin should be left floating if unused. PFI Input Early Power-fail Input. Typically connected to an unregulated power supply to detect an early power failure. This pin must be tied to ground if unused. CAL/PFO Output Calibration/Early Power-fail Output. In calibration mode, this pin supplies a 512 Hz square-wave output for clock calibration. In normal operation, this is the early power-fail output. V Power supply Backup supply voltage. Connected to a 3 V battery or a large value capacitor. If no backup supply BAK is used, this pin should be tied to ground and the VBC bit should be cleared in the RTC register 0Bh. The trickle charger is UL recognized and ensures no excessive current when using a lithium battery. V Power supply Ground for the device. Must be connected to the ground of the system. SS V Power supply Power supply input to the device. DD Document Number: 001-86393 Rev. *E Page 4 of 35

FM31276/FM31278 Functional Overview Processor Companion The FM31276/FM31278 device combines a serial nonvolatile In addition to nonvolatile RAM, the FM31276/FM31278 RAM with a real time clock (RTC) and a processor companion. incorporates a real time clock and highly integrated processor The companion is a highly integrated peripheral including a companion. The companion includes a low-V reset, a DD processor supervisor, a comparator used for early power-fail programmable watchdog timer, a battery-backed event warning, nonvolatile event counters, and a 64-bit serial number. counters, a comparator for early power-fail detection or other The FM31276/FM31278 integrates these complementary but purposes, and a 64-bit serial number. distinct functions under a common interface in a single package. Processor Supervisor The product is organized as two logical devices. The first is a memory and the second is the companion which includes all the Supervisors provide a host processor two basic functions: remaining functions. From the system perspective they appear detection of power supply fault conditions and a watchdog timer to be two separate devices with unique IDs on the serial bus. to escape a software lockup condition. The FM31276/FM31278 The memory is organized as a standalone nonvolatile I2C has a reset pin (RST) to drive a processor reset input during memory using standard device ID value. The real time clock and power faults, power-up, and software lockups. It is an open drain supervisor functions are accessed with a separate I2C device ID. output with a weak internal pull-up to VDD. This allows other reset This allows clock/calendar data to be read while maintaining the sources to be wire-OR’d to the RST pin. When VDD is above the most recently used memory address. The clock and supervisor programmed trip point, RST output is pulled weakly to VDD. If functions are controlled by 25 special function registers. The VDD drops below the reset trip point voltage level (VTP), the RST RTC and event counter circuits are maintained by the power pin will be driven LOW. It will remain LOW until VDD falls too low source on the VBAK pin, allowing them to operate from battery or for circuit operation which is the VRST level. When VDD rises backup capacitor power when VDD drops below a set threshold. again above VTP, RST continues to drive LOW for at least 100 Each functional block is described below. ms (tRPU) to ensure a robust system reset at a reliable VDD level. After t has been met, the RST pin will return to the weak RPU Memory Architecture HIGH state. While RST is asserted, serial bus activity is locked out even if a transaction occurred as V dropped below V . A The FM31276/FM31278 device is available in memory size DD TP memory operation started while V is above V will be 64-Kbit/256-Kbit. The device uses two-byte addressing for the DD TP completed internally. memory portion of the chip. This makes the device software compatible with its standalone memory counterparts, but makes Table2 below shows how bit VTP controls the trip point of the them compatible within the entire family. low-V reset. They are located in register 0Bh, bits 1 and 0. The DD reset pin will drive LOW when V is below the selected V The memory array is logically organized as 8,192 × 8 bits/ DD TP 32,768 × 8 bits and is accessed using an industry-standard I2C voltage, and the I2C interface and F-RAM array will be locked out. Note that the bit 1 location is a don’t care. Figure2 illustrates interface. The memory is based on F-RAM technology. the reset operation in response to a low V . Therefore it can be treated as RAM and is read or written at the DD speed of the I2C bus with no delays for write operations. It also Table 2. VTP setting offers effectively unlimited write endurance unlike other nonvolatile memory technologies. The I2C protocol is described VTP Setting VTP in I2C Interface on page 20. 3.9 V 0 The memory array can be write-protected by software. Two bits 4.4 V 1 in the processor companion area (WP1, WP0 in register 0Bh) control the protection setting. Based on the setting, the protected addresses cannot be written and the I2C interface will not Figure 2. Low V Reset acknowledge any data to protected addresses. The special DD function registers containing these bits are described in detail V below. DD t RPU V TP Table 1. Block Memory Write Protection WP1 WP0 Protected Address Range 0 0 None RST 0 1 Bottom 1/4 1 0 Bottom 1/2 A watchdog timer can also be used to drive an active reset signal. 1 1 Full array The watchdog is a free-running programmable timer. The timeout period can be software programmed from 100 ms to 3seconds in 100 ms increments via a 5-bit nonvolatile register. Document Number: 001-86393 Rev. *E Page 5 of 35

FM31276/FM31278 All programmed settings are minimum values and vary with Manual Reset temperature according to the operating specifications. The The RST is a bi-directional signal allowing the watchdog has two additional controls associated with its FM31276/FM31278 to filter and de-bounce a manual reset operation, a watchdog enable bit (WDE) and timer restart bits switch. The RST input detects an external low condition and (WR). Both the enable bit must be set and the watchdog must responds by driving the RST signal LOW for 100 ms. timeout in order to drive RST active. If a reset event occurs, the timer will automatically restart on the rising edge of the reset pulse. If WDE = ‘0’, the watchdog timer runs but a watchdog fault Figure 4. Manual Reset will not cause RST to be asserted LOW. The WTR flag will be set, indicating a watchdog fault. This setting is useful during MCU RST software development if the developer does not want RST to FM31276/FM31278 Reset drive. Note that setting the maximum timeout setting (11111b) Switch disables the counter to save power. The second control is a nibble that restarts the timer preventing a reset. The timer should be restarted after changing the timeout value. The watchdog timeout value is located in register 0Ah, bits 4:0, and the watchdog enable is bit 7. The watchdog is restarted by FM31276/FM31278 writing the pattern 1010b to the lower nibble of register 09h. RST drives Writing this pattern will also cause the timer to load new timeout 100 ms (min.) values. Writing other patterns to this address will not affect its operation. Note the watchdog timer is free-running. Prior to Note The internal weak pull-up eliminates the need for additional enabling it, users should restart the timer as described above. external components. This assures that the full timeout period will be set immediately Reset Flags after enabling. The watchdog is disabled when V is below V . DD TP The following table summarizes the watchdog bits. A block In case of a reset condition, a flag bit will be set to indicate the diagram follows. source of the reset. A low-V reset is indicated by the POR flag, DD register 09h bit 6. A watchdog reset is indicated by the WTR flag, register 09h bit 7. Note that the flags are internally set in Watchdog Timeout WDT(4:0) 0Ah, bits 4:0 Watchdog Enable WDE 0Ah, bit 7 response to reset sources, but they must be cleared by the user. Watchdog Restart WR(3:0) 09h, bits 3:0 When the register is read, it is possible that both flags are set if both have occurred since the user last cleared them. Early Power Fail Comparator Figure 3. Watchdog Timer An early power fail warning can be provided to the processor well WR(3:0) = 1010b to restart before V drops out of spec. The comparator is used to create 100 ms DD clock a power fail interrupt (NMI). This can be accomplished by Timebase Down Counter RST connecting the PFI pin to the unregulated power supply via a resistor divider. An application circuit is shown below. Watchdog Timer Settings WDE Figure 5. Comparator as a Power-Fail Warning VDD Regulator FM31276/ FM31278 PFI To MCU CAL/PFO + NMI input - 1.2 V ref Document Number: 001-86393 Rev. *E Page 6 of 35

FM31276/FM31278 The voltage on the PFI input pin is compared to an onboard 1.2V 1; the Cascade Control is CC, bit 2; and the Read Counter bit is reference. When the PFI input voltage drops below this RC, bit 3. threshold, the comparator will drive the CAL/PFO pin to a LOW The polarity bits must be set prior to setting the counter value(s). state. The comparator has 100 mV (max) of hysteresis to reduce If a polarity bit is changed, the counter may inadvertently noise sensitivity, only for a rising PFI signal. For a falling PFI increment. If the counter pins are not being used, tie them to edge, there is no hysteresis. ground. The comparator is a general purpose device and its application Serial Number is not limited to the NMI function. A memory location to write a 64-bit serial number is provided. It The comparator is not integrated into the special function is a writeable nonvolatile memory block that can be locked by the registers except as it shares its output pin with the CAL output. user once the serial number is set. The 8 bytes of data and the When the RTC calibration mode is invoked by setting the CAL lock bit are all accessed via the device ID for the Processor bit (register 00h, bit 2), the CAL/PFO output pin will be driven with Companion. Therefore the serial number area is separate and a 512 Hz square wave and the comparator will be ignored. Since distinct from the memory array. The serial number registers can most users only invoke the calibration mode during production, be written an unlimited number of times, so these locations are this should have no impact on system operations using the general purpose memory. However, once the lock bit is set, the comparator. values cannot be altered and the lock cannot be removed. Once Note The maximum voltage on the comparator input PFI is locked the serial number registers can still be read by the limited to 3.75 V under normal operating conditions. system. Event Counter The serial number is located in registers 11h to 18h. The lock bit The FM31276/FM31278 offers the user two battery-backed is SNL (register 0Bh, bit 7). Setting the SNL bit to a ‘1’ disables event counters. Input pins CNT1 and CNT2 are programmable writes to the serial number registers, and the SNL bit cannot be edge detectors. Each clocks a 16-bit counter. When an edge cleared. occurs, the counters will increment their respective registers. Counter 1 is located in registers 0Dh and 0Eh, Counter 2 is Real-time Clock Operation located in registers 0Fh and 10h. These register values can be read anytime V is above V , and they will be incremented as DD TP The real-time clock (RTC) is a timekeeping device that can be long as a valid V power source is provided. To read, set the BAK RC bit, register 0Ch bit 3 to 1. This takes a snapshot of all four battery or capacitor backed for permanently-powered operation. counter bytes allowing a stable value even if a count occurs It offers a software calibration feature that allows high accuracy. during the read. The registers can be written by software allowing the counters to be cleared or initialized by the system. Counts The RTC consists of an oscillator, clock divider, and a register are blocked during a write operation. The two counters can be system for user access. It divides down the 32.768 kHz cascaded to create a single 32-bit counter by setting the CC time-base and provides a minimum resolution of seconds (1 Hz). control bit (register 0Ch, bit 2). When cascaded, the CNT1 input Static registers provide the user with read/write access to the will cause the counter to increment. CNT2 is not used in this time values. It includes registers for seconds, minutes, hours, mode and should be tied to ground. day-of-the-week, date, months, and years. A block diagram (Figure 7 on page 8) illustrates the RTC function. Figure 6. Event Counter The user registers are synchronized with the timekeeper core C1P using R and W bits in register 00h described below. Changing CNT1 16-bit Counter the R bit from ‘0’ to ‘1’ transfers timekeeping information from the core into holding registers that can be read by the user. If a timekeeper update is pending when R is set, then the core will C2P be updated prior to loading the user registers. The registers are frozen and will not be updated again until the R bit is cleared to CNT2 16-bit Counter ‘0’. R is used for reading the time. Setting the W bit to ‘1’ locks the user registers. Clearing it to ‘0’ CC causes the values in the user registers to be loaded into the timekeeper core. W bit is used for writing new time values. Users The control bits for event counting are located in register 0Ch. should be certain not to load invalid values, such as FFh, to the Counter 1 Polarity is bit C1P, bit 0; Counter 2 Polarity is C2P, bit timekeeping registers. Updates to the timekeeping core occur continuously except when locked. Document Number: 001-86393 Rev. *E Page 7 of 35

FM31276/FM31278 Figure 7. Real-time Clock Core Block Diagram 512 Hz or   OSCEN   Square Wa ve W 32c.r7y6s8ta klHz   Oscillator   DCivloidcekr   1 Hz  ULpodgaicte   Years  Months   Date  CF   8 bits  5 bits  6 bits  Hours  MInutes  Seconds  6 bits  7 bits  7 bits  Days  3 bits  User Interface Register s R Backup Power The minimum V voltage varies linearly with temperature. The BAK The real-time clock/calendar is intended to be permanently user can expect the minimum VBAK voltage to be 1.23 V at powered. When the primary system power fails, the voltage on +85°C and 1.90 V at -40 °C. The tested limit is 1.55 V at +25 °C. the VDD pin will drop. When VDD is less than 2.5 V, the RTC (and Note The minimum VBAK voltage has been characterized at event counters) will switch to the backup power supply on VBAK. -40°C and +85 °C but is not 100% tested. The clock operates at extremely low current in order to maximize battery or capacitor life. However, an advantage of combining a Figure 9. V (min.) vs Temperature clock function with F-RAM memory is that data is not lost BAK regardless of the backup power source. The I current varies with temperature and voltage (see DC BAK Electrical Characteristics on page 26). The following graph shows IBAK as a function of VBAK. These curves are useful for V) calculating backup time when a capacitor is used as the VBAK (n. source. Kmi A B V Figure 8. I vs. V Voltage BAK BAK Temperature (°C) Trickle Charger A) To facilitate capacitor backup the V pin can optionally provide  BAK (K a trickle charge current. When the VBC bit (register 0Bh, bit 2) is A IB set to ‘1’, the VBAK pin will source approximately 80 µA until VBAK reaches 3.75 V. In 5 V systems, this charges the capacitor to V DD without an externaldiodeandresistorcharger and also prevents the user from exceeding the V maximum voltage BAK VBAK (V) specification. There is a Fast Charge mode which is enabled by the FC bit (register 0Bh, bit 5). In this mode the trickle charger current is set to approximately 1 mA, allowing a large backup capacitor to charge more quickly. Document Number: 001-86393 Rev. *E Page 8 of 35

FM31276/FM31278 In the case where no battery is used, the V pin should be tied Crystal Oscillator BAK to V . V should not be tied to 5 V since the V (max) SS BAK BAK The crystal oscillator is designed to use a 6 pF/12.5 pF crystal specification will be exceeded. Be sure to turn off the trickle without the need for external components, such as loading charger (VBC = ‘0’), otherwise charger current will be shunted to capacitors. The FM31276/FM31278 device has built-in loading ground from V . DD capacitors that are optimized for use with 6 pF crystals, but which Note Systems using lithium batteries should clear the VBC bit to work well with 12.5 pF crystals. For either crystal, no additional ‘0’ to prevent battery charging. The V circuitry includes an external loading capacitors are required nor suggested. BAK internal 1 K series resistor as a safety element. The trickle If a 32.768 kHz crystal is not used, an external oscillator may be charger is UL Recognized. connected to the FM31276/FM31278. Apply the oscillator to the X1 pin. Its high and low voltage levels can be driven rail-to-rail or Calibration amplitudes as low as approximately 500 mV p-p. To ensure When the CAL bit in the register 00h is set to ‘1’, the clock enters proper operation, a DC bias must be applied to the X2 pin. It calibration mode. In calibration mode, the CAL/PFO output pin is should be centered between the high and low levels on the X1 dedicated to the calibration function and the power fail output is pin. This can be accomplished with a voltage divider. temporarily unavailable. Calibration operates by applying a digital correction to the counter based on the frequency error. In this mode, the CAL/PFO pin is driven with a 512 Hz (nominal) Figure 10. External Oscillator square wave. Any measured deviation from 512 Hz translates into a timekeeping error. The user converts the measured error in ppm and writes the appropriate correction value to the FM31276/FM31278 calibration register. The correction factors are listed in the table X1 X2 below. Positive ppm errors require a negative adjustment that removes pulses. Negative ppm errors require a positive VDD correction that adds pulses. Positive ppm adjustments have the R1 CALS (sign) bit set to ‘1’, whereas negative ppm adjustments have CALS = ‘0’. After calibration, the clock will have a maximum R2 error of ±2.17 ppm or ±0.09 minutes per month at the calibrated temperature. The calibration setting is stored in F-RAM so it is not lost should In the example, R1 and R2 are chosen such that the X2 voltage the backup source fail. It is accessed with bits CAL(4:0) in is centered around the X1 oscillator drive levels. If you wish to register 01h. This value can be written only when the CAL bit is avoid the DC current, you may choose to drive X1 with an set to a ‘1’. To exit the calibration mode, the user must clear the external clock and X2 with an inverted clock using a CMOS CAL bit to a ‘0’. When the CAL bit is ‘0’, the CAL/PFO pin will inverter. revert to the power fail output function. Document Number: 001-86393 Rev. *E Page 9 of 35

FM31276/FM31278 Layout Recommendations and the guard ring grounded. SDA and SCL traces should be routed away from the X1 / X2 pads. The X1 and X2 trace lengths The X1 and X2 crystal pins employ very high impedance circuits should be less than 5 mm. The use of a ground plane on the and the oscillator connected to these pins can be upset by noise backside or inner board layer is preferred. See layout example. or extra loading. To reduce RTC clock errors from signal Red is the top layer, green is the bottom layer. switching noise, a guard ring must be placed around these pads Figure 11. Layout Recommendations VDD VDD SCL SCL SDA SDA X2 X2 X1 X1 PFI PFI VBAK VBAK Layout for Surface Mount Crystal Layout for Through Hole Crystal (red = top layer, green = bottom layer) (red = top layer, green = bottom layer) Document Number: 001-86393 Rev. *E Page 10 of 35

FM31276/FM31278 Table 3. Digital Calibration Adjustments Measured Frequency Range Error Range (PPM) S.No. Program Calibration Register to: Min Max Min Max Positive Calibration for slow clocks: Calibration will achieve ±2.17 PPM after calibration 0 512.0000 511.9989 0 2.17 000000 1 511.9989 511.9967 2.18 6.51 100001 2 511.9967 511.9944 6.52 10.85 100010 3 511.9944 511.9922 10.86 15.19 100011 4 511.9922 511.9900 15.20 19.53 100100 5 511.9900 511.9878 19.54 23.87 100101 6 511.9878 511.9856 23.88 28.21 100110 7 511.9856 511.9833 28.22 32.55 100111 8 511.9833 511.9811 32.56 36.89 101000 9 511.9811 511.9789 36.90 41.23 101001 10 511.9789 511.9767 41.24 45.57 101010 11 511.9767 511.9744 45.58 49.91 101011 12 511.9744 511.9722 49.92 54.25 101100 13 511.9722 511.9700 54.26 58.59 101101 14 511.9700 511.9678 58.60 62.93 101110 15 511.9678 511.9656 62.94 67.27 101111 16 511.9656 511.9633 67.28 71.61 110000 17 511.9633 511.9611 71.62 75.95 110001 18 511.9611 511.9589 75.96 80.29 110010 19 511.9589 511.9567 80.30 84.63 110011 20 511.9567 511.9544 84.64 88.97 110100 21 511.9544 511.9522 88.98 93.31 110101 22 511.9522 511.9500 93.32 97.65 110110 23 511.9500 511.9478 97.66 101.99 110111 24 511.9478 511.9456 102.00 106.33 111000 25 511.9456 511.9433 106.34 110.67 111001 26 511.9433 511.9411 110.68 115.01 111010 27 511.9411 511.9389 115.02 119.35 111011 28 511.9389 511.9367 119.36 123.69 111100 29 511.9367 511.9344 123.70 128.03 111101 30 511.9344 511.9322 128.04 132.37 111110 31 511.9322 511.9300 132.38 136.71 111111 Document Number: 001-86393 Rev. *E Page 11 of 35

FM31276/FM31278 Table 3. Digital Calibration Adjustments (continued) Measured Frequency Range Error Range (PPM) S.No. Program Calibration Register to: Min Max Min Max Negative Calibration for fast clocks: Calibration will achieve ±2.17 PPM after calibration 0 512.0000 512.0011 0 2.17 000000 1 512.0011 512.0033 2.18 6.51 000001 2 512.0033 512.0056 6.52 10.85 000010 3 512.0056 512.0078 10.86 15.19 000011 4 512.0078 512.0100 15.20 19.53 000100 5 512.0100 512.0122 19.54 23.87 000101 6 512.0122 512.0144 23.88 28.21 000110 7 512.0144 512.0167 28.22 32.55 000111 8 512.0167 512.0189 32.56 36.89 001000 9 512.0189 512.0211 36.90 41.23 001001 10 512.0211 512.0233 41.24 45.57 001010 11 512.0233 512.0256 45.58 49.91 001011 12 512.0256 512.0278 49.92 54.25 001100 13 512.0278 512.0300 54.26 58.59 001101 14 512.0300 512.0322 58.60 62.93 001110 15 512.0322 512.0344 62.94 67.27 001111 16 512.0344 512.0367 67.28 71.61 010000 17 512.0367 512.0389 71.62 75.95 010001 18 512.0389 512.0411 75.96 80.29 010010 19 512.0411 512.0433 80.30 84.63 010011 20 512.0433 512.0456 84.64 88.97 010100 21 512.0456 512.0478 88.98 93.31 010101 22 512.0478 512.0500 93.32 97.65 010110 23 512.0500 512.0522 97.66 101.99 010111 24 512.0522 512.0544 102.00 106.33 011000 25 512.0544 512.0567 106.34 110.67 011001 26 512.0567 512.0589 110.68 115.01 011010 27 512.0589 512.0611 115.02 119.35 011011 28 512.0611 512.0633 119.36 123.69 011100 29 512.0633 512.0656 123.70 128.03 011101 30 512.0656 512.0678 128.04 132.37 011110 31 512.0678 512.0700 132.38 136.71 011111 Document Number: 001-86393 Rev. *E Page 12 of 35

FM31276/FM31278 Register Map The RTC and processor companion functions are accessed via 25 special function registers, which are mapped to a separate I2C device ID. The interface protocol is described on page 20. The registers contain timekeeping data, control bits, and information flags. A description of each register follows the summary table. Table 4. Register Map Summary Table Nonvolatile = Battery-backed = Data Address Function Range D7 D6 D5 D4 D3 D2 D1 D0 18h Serial Number Byte 7 Serial Number 7 FFh 17h Serial Number Byte 6 Serial Number 6 FFh 16h Serial Number Byte 5 Serial Number 5 FFh 15h Serial Number Byte 4 Serial Number 4 FFh 14h Serial Number Byte 3 Serial Number 3 FFh 13h Serial Number Byte 2 Serial Number 2 FFh 12h Serial Number Byte 1 Serial Number 1 FFh 11h Serial Number Byte 0 Serial Number 0 FFh 10h Counter 2 MSB Event Counter 2 MSB FFh 0Fh Counter 2 LSB Event Counter 2 LSB FFh 0Eh Counter 1 MSB Event Counter 1 MSB FFh 0Dh Counter 1 LSB Event Counter 1 LSB FFh 0Ch RC CC C2P C1P Event Count Control 0Bh SNL – FC WP1 WP0 VBC – VTP Companion Control 0Ah WDE – – WDT4 WDT3 WDT2 WDT1 WDT0 Watchdog Control 09h WTR POR LB – WR3 WR2 WR1 WR0 Watchdog Restart/Flags 08h 10 years years Years 00–99 07h 0 0 0 10 months Month 01–12 months 06h 0 0 10 date date Date 01–31 05h 0 0 0 0 0 day Day 01–07 04h 0 0 10 hours hours Hours 00–23 03h 0 10 minutes minutes Minutes 00–59 02h 0 10 seconds seconds Seconds 00–59 01h OSCEN reserved CALS CAL4 CAL3 CAL2 CAL1 CAL0 CAL Control 00h reserved CF reserved reserved reserved CAL W R RTC Control Note When the device is first powered up and programmed, all timekeeping registers must be written because the battery-backed register values cannot be guaranteed. The table below shows the default values of the non-volatile registers. All other register values should be treated as unknown. Document Number: 001-86393 Rev. *E Page 13 of 35

FM31276/FM31278 Table 5. Default Register Values Address Hex Value Address Hex Value 18h 0x00 0Ah 0x1F 17h 0x00 08h 0x00 16h 0x00 07h 0x01 15h 0x00 06h 0x01 14h 0x00 05h 0x01 13h 0x00 04h 0x00 12h 0x00 03h 0x01 11h 0x00 02h 0x00 0Bh 0x00 01h 0x80 Document Number: 001-86393 Rev. *E Page 14 of 35

FM31276/FM31278 Table 6. Register Description Address Description 18h Serial Number Byte 7 D7 D6 D5 D4 D3 D2 D1 D0 SN.63 SN.62 SN.61 SN.60 SN.59 SN.58 SN.57 SN.56 Upper byte of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 17h Serial Number Byte 6 D7 D6 D5 D4 D3 D2 D1 D0 SN.55 SN.54 SN.53 SN.52 SN.51 SN.50 SN.49 SN.48 16h Byte 6 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. Serial Number Byte 5 D7 D6 D5 D4 D3 D2 D1 D0 SN.47 SN.46 SN.45 SN.44 SN.43 SN.42 SN.41 SN.40 Byte 5 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 15h Serial Number Byte 4 D7 D6 D5 D4 D3 D2 D1 D0 SN.39 SN.38 SN.37 SN.36 SN.35 SN.34 SN.33 SN.32 Byte 4 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 14h Serial Number Byte 3 D7 D6 D5 D4 D3 D2 D1 D0 SN.31 SN.30 SN.29 SN.28 SN.27 SN.26 SN.25 SN.24 Byte 3 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 13h Serial Number Byte 2 D7 D6 D5 D4 D3 D2 D1 D0 SN.23 SN.22 SN.21 SN.20 SN.19 SN.18 SN.17 SN.16 Byte 2 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 12h Serial Number Byte 1 D7 D6 D5 D4 D3 D2 D1 D0 SN.15 SN.14 SN.13 SN.12 SN.11 SN.10 SN.9 SN.8 Byte 1 of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 11h Serial Number Byte 0 D7 D6 D5 D4 D3 D2 D1 D0 SN.7 SN.6 SN.5 SN.4 SN.3 SN.2 SN.1 SN.0 LSB of the serial number. Read/write when SNL = ‘0’, read-only when SNL = ‘1’. Nonvolatile. 10h Counter 2 MSB D7 D6 D5 D4 D3 D2 D1 D0 C2.15 C2.14 C2.13 C2.12 C2.11 C2.10 C2.9 C2.8 Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write. Document Number: 001-86393 Rev. *E Page 15 of 35

FM31276/FM31278 Table 6. Register Description (continued) Address Description 0Fh Counter 2 LSB D7 D6 D5 D4 D3 D2 D1 D0 C2.7 C2.6 C2.5 C2.4 C2.3 C2.2 C2.1 C2.0 Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB when CC = ‘1’. Battery-backed, read/write. 0Eh Counter 1 MSB D7 D6 D5 D4 D3 D2 D1 D0 C1.15 C1.14 C1.13 C1.12 C1.11 C1.10 C1.9 C1.8 Event Counter 1MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write. 0Dh Counter 1 LSB D7 D6 D5 D4 D3 D2 D1 D0 C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write. 0Ch Event Counter Control D7 D6 D5 D4 D3 D2 D1 D0 – – – – RC CC C2P C1P RC Read Counter. Setting this bit to ‘1’ takes a snapshot of the four counters bytes allowing the system to read the values without missing count events. The RC bit will be automatically cleared. CC Counter Cascade. When CC = ‘0’, the event counters operate independently according to the edge programmed by C1P and C2P respectively. When CC = ‘1’, the counters are cascaded to create one 32-bit counter. The registers of Counter 2 represent the most significant 16-bits of the counter and CNT1 is the controlling input. Bit C2P is don’t care when CC = ‘1’. Battery-backed, read/write. C2P CNT2 detects falling edges when C2P = ‘0’, rising edges when C2P = ‘1’. C2P is “don't care” when CC = ‘1’. The value of Event Counter 2 may inadvertently increment if C2P is changed. Battery-backed, read/write. C1P CNT1 detects falling edges when C1P = ‘0’, rising edges when C1P = ‘1’. The value of Event Counter 1 may inadvertently increment if C1P is changed. Battery-backed, read/write. 0Bh Companion Control D7 D6 D5 D4 D3 D2 D1 D0 SNL – FC WP1 WP0 VBC – VTP SNL Serial Number Lock: Setting to a ‘1’ makes registers 11h to 18h and SNL permanently read-only. SNL cannot be cleared once set to ‘1’. Nonvolatile, read/write. FC Fast Charge: Setting FC to '1' (and VBC = ‘1’) causes a ~1 mA trickle charge current to be supplied on V . Clearing BAK VBC to '0' disables the charge current. Nonvolatile, read/write. WP(1:0) Write Protect. These bits control the write protection of the memory array. Nonvolatile, read/write. Write protect address WP1 WP0 None 0 0 Bottom 1/4 0 1 Bottom 1/2 1 0 Full array 1 1 VBC V Charger Control. Setting VBC to ‘1’ (and FC = ‘0’) causes a 80 µA (1 mA if FC = ‘1’) trickle charge current to BAK be supplied on V . Clearing VBC to ‘0’ disables the charge current. Nonvolatile, read/write. BAK Document Number: 001-86393 Rev. *E Page 16 of 35

FM31276/FM31278 Table 6. Register Description (continued) Address Description VTP VTP Select. This bit control the reset trip point for the low V reset function. Nonvolatile, read/write. DD Trip Voltage VTP 3.9 V 0 4.4 V 1 0Ah Watchdog Control D7 D6 D5 D4 D3 D2 D1 D0 WDE – – WDT4 WDT3 WDT2 WDT1 WDT0 WDE Watchdog Enable. When WDE = ‘1’, a watchdog timer fault will cause the RST signal to go active. When WDE = ‘0’ the timer runs but has no effect on RST, however the WTR flag will be set when a fault occurs. Note as the timer is free-running, users should restart the timer using WR(3:0) prior to setting WDE = ‘1’. This assures a full watchdog timeout interval occurs. Nonvolatile, read/write. WDT(4:0) Watchdog Timeout. Indicates the minimum watchdog timeout interval with 100 ms resolution. New watchdog timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). Nonvolatile, read/write. Watchdog Timeout WDT4 WDT3 WDT2 WDT1 WDT0 Invalid - default 100 ms 0 0 0 0 0 100 ms 0 0 0 0 1 200 ms 0 0 0 1 0 300 ms 0 0 0 1 1 . . 2000 ms 1 0 1 0 0 2100 ms 1 0 1 0 1 2200 ms 1 0 1 1 0 . . 2900 ms 1 1 1 0 1 3000 ms 1 1 1 1 0 Disable Counter 1 1 1 1 1 09h Watchdog Restart and Flags D7 D6 D5 D4 D3 D2 D1 D0 WTR POR LB – WR3 WR2 WR1 WR0 WTR Watchdog Timer Reset Flag: When a watchdog timer fault occurs, the WTR bit will be set to ‘1’. It must be cleared by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). POR Power-on Reset Flag: When the RST pin is activated by V < V , the POR bit will be set to ‘1’. It must be cleared DD TP by the user. Note that both WTR and POR could be set if both reset sources have occurred since the flags were cleared by the user. Battery-backed. Read/Write (internally set, user can clear bit). LB Low Backup Flag: On power up, if the V source is below the minimum voltage to operate the RTC and event BAK counters, this bit will be set to ‘1’. The user should clear it to ‘0’ when initializing the system. Battery-backed. Read/Write (internally set, user can clear bit). WR(3:0) Watchdog Restart: Writing a pattern 1010b to WR(3:0) restarts the watchdog timer. The upper nibble contents do not affect this operation. Writing any pattern other than 1010b to WR(3:0) has no effect on the timer. This allows users to clear the WTR, POR, and LB flags without affecting the watchdog timer. Battery-backed, Write-only. Document Number: 001-86393 Rev. *E Page 17 of 35

FM31276/FM31278 Table 6. Register Description (continued) Address Description 08h Timekeeping – Years D7 D6 D5 D4 D3 D2 D1 D0 10 year.3 10 year.2 10 year.1 10 year.0 Year.3 Year.2 Year.1 Year.0 Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. Battery-backed, read/write. 07h Timekeeping – Months D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 10 Month Month.3 Month.2 Month.1 Month.0 Contains the BCD digits for the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12. Battery-backed, read/write. 06h Timekeeping – Date of the month D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 date.1 10 date.0 Date.3 Date.2 Date.1 Date.0 Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1–31. Battery-backed, read/write. 05h Timekeeping – Day of the week D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 Day.2 Day.1 Day.0 Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, as the day is not integrated with the date. Battery-backed, read/write. 04h Timekeeping – Hours D7 D6 D5 D4 D3 D2 D1 D0 0 0 10 hours.1 10 hours.0 Hours.3 Hours.2 Hours.1 Hours.0 Contains the BCD value of hours in 24-hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23. Battery-backed, read/write. 03h Timekeeping – Minutes D7 D6 D5 D4 D3 D2 D1 D0 0 10 min.2 10 min.1 10 min.0 Min.3 Min.2 Min.1 Min.0 Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Battery-backed, read/write. Document Number: 001-86393 Rev. *E Page 18 of 35

FM31276/FM31278 Table 6. Register Description (continued) Address Description 02h Timekeeping – Seconds D7 D6 D5 D4 D3 D2 D1 D0 0 10 sec.2 10 sec.1 10 sec.0 Seconds.3 Seconds.2 Seconds.1 Seconds.0 Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0–59. Battery-backed, read/write. 01h CAL/Control D7 D6 D5 D4 D3 D2 D1 D0 OSCEN Reserved CALS CAL.4 CAL.3 CAL.2 CAL.1 CAL.0 OSCEN Oscillator Enable. When set to ‘1’, the oscillator is halted. When set to ‘0’, the oscillator runs after t time. Disabling OSC the oscillator can save battery power during storage. On a power-up without battery, this bit is set to ‘1’. Battery-backed, read/write. Reserved Reserved bits. Do not use. Should remain set to ‘0’. CALS Calibration Sign: Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. This bit can be written only when CAL = ‘1’. Nonvolatile, read/write. CAL(4:0) Calibration Setting: These five bits control the calibration of the clock. These bits can be written only when CAL = ‘1’. Nonvolatile, read/write. 00h RTC Control D7 D6 D5 D4 D3 D2 D1 D0 Reserved CF Reserved Reserved Reserved CAL W R CF Century Overflow Flag. This bit is set to a ‘1’ when the values in the years register overflows from 99 to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user should record the new century information as needed. This bit is cleared to ‘0’ when the Flag register is read. It is read-only for the user. Battery-backed. CAL Calibration Setting. When set to ‘1’, the clock enters calibration mode. When CAL is set to ‘0’, the clock operates normally, and the CAL/PFO pin is controlled by the power fail comparator. Battery-backed, read/write. W Write Time. Setting the W bit to ‘1’ freezes the clock. The user can then write the timekeeping registers with updated values. Resetting the W bit to ‘0’ causes the contents of the time registers to be transferred to the timekeeping counters and restarts the clock. Battery-backed, read/write. R Read Time. Setting the R bit to ‘1’ copies a static image of the timekeeping core and place it into the user registers. The user can then read them without concerns over changing values causing system errors. The R bit going from ‘0’ to ‘1’ causes the timekeeping capture, so the bit must be returned to ‘0’ prior to reading again. Battery-backed, read/write. Reserved Reserved bits. Do not use. Should remain set to ‘0’. Document Number: 001-86393 Rev. *E Page 19 of 35

FM31276/FM31278 I2C Interface signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. The FM31276/FM31278 employs an industry standard I2C bus that is familiar to many users. This product is unique since it STOP Condition (P) incorporates two logical devices in one chip. Each logical device A STOP condition is indicated when the bus master drives SDA can be accessed individually. Although monolithic, it appears to from LOW to HIGH while the SCL signal is HIGH. All operations the system software to be two separate products. One is a using the FM31276/FM31278 should end with a STOP condition. memory device. It has a Slave Address (Slave ID = 1010b) that If an operation is in progress when a STOP is asserted, the operates the same as a stand-alone memory device. The second operation will be aborted. The master must have control of SDA device is a real-time clock and processor companion which have in order to assert a STOP condition. a unique Slave Address (Slave ID = 1101b). START Condition (S) By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. A START condition is indicated when the bus master drives SDA The device that is controlling the bus is the master. The master from HIGH to LOW while the SCL signal is HIGH. All commands is responsible for generating the clock signal for all operations. should be preceded by a START condition. An operation in Any device on the bus that is being controlled is a slave. The progress can be aborted by asserting a START condition at any FM31276/FM31278 is always a slave device. time. Aborting an operation using the START condition will ready the FM31276/FM31278 for a new operation. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including START, STOP, If during operation the power supply drops below the specified data bit, or acknowledge. Figure 12 and Figure 13 illustrates the VTP minimum, any I2C transaction in progress will be aborted and the system should issue a START condition prior to performing another operation. Figure 12. START and STOP Conditions full pagewidth SDA SDA SCL SCL S P START Condition STOP Condition Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is HIGH. Except under the three conditions described above, the SDA signal should not change while SCL is HIGH. Figure 13. Data Transfer on the I2C Bus handbook, full pagewidth P SDA MSB Acknowledgement Acknowledgement S signal from slave signal from receiver SCL S S 1 2 7 8 9 1 2 3 4 - 8 9 or P ACK ACK START STOP or condition Byte complete START condition Document Number: 001-86393 Rev. *E Page 20 of 35

FM31276/FM31278 Acknowledge/No-acknowledge addressed again. This allows the last byte to be recovered in the event of a communication error. The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter Second and most common, the receiver does not acknowledge should release the SDA bus to allow the receiver to drive it. The to deliberately end an operation. For example, during a read receiver drives the SDA signal LOW to acknowledge receipt of operation, the FM31276/FM31278 will continue to place data the byte. If the receiver does not drive SDA LOW, the condition onto the bus as long as the receiver sends acknowledges (and is a no-acknowledge and the operation is aborted. clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the The receiver would fail to acknowledge for two distinct reasons. receiver acknowledges the last byte, this will cause the First is that a byte transfer fails. In this case, the no-acknowledge FM31276/FM31278 to attempt to drive the bus on the next clock ceases the current operation so that the device can be while the master is sending a new command such as STOP. Figure 14. Acknowledge on the I2C Bus handbook, full pagewidth DATA OUTPUT BY MASTER No Acknowledge DATA OUTPUT BY SLAVE Acknowledge SCL FROM 1 2 8 9 MASTER S Clock pulse for START acknowledgement Condition Slave Address same I2C bus by assigning a different address to each. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a read operation and The first byte that the FM31276/FM31278 expects after a START R/W = ‘0’ indicates a write operation. condition is the slave address. As shown in Figure 15 and Figure 16, the slave address contains the device type or slave ID, the device select address bits, and a bit that specifies if the Figure 15. Memory Slave Device Address transaction is a read or a write. MSB LSB handbook, halfpage The FM31276/FM31278 has two Slave Addresses (Slave IDs) 1 0 1 0 X A1 A0 R/W associated with two logical devices. Bits 7–4 are the device type (slave ID) and should be set to 1010b for the memory device. The other logical device within the FM31276/FM31278 is the Slave ID Device Select real-time clock and companion. Bits 7–4 are the device type (slave ID) and should be set to 1101b for the RTC and Figure 16. Companion Slave Device Address companion. A bus transaction with this slave address will not affect the memory in any way. The figures below illustrate the two handbook, halfpMagSeB LSB Slave Addresses. 1 1 0 1 X A1 A0 R/W Bits 2–1 are the device select address bits. They must match the corresponding value on the external address pins to select the Slave ID Device device. Up to four FM31276/FM31278 devices can reside on the Select Document Number: 001-86393 Rev. *E Page 21 of 35

FM31276/FM31278 Addressing Overview - Memory Addressing Overview - RTC & Companion After the FM31276/FM31278 (as receiver) acknowledges the The RTC and Processor Companion operate in a similar manner slave address, the master can place the memory address on the to the memory, except that it uses only one byte of address. bus for a write operation. The address requires two bytes. The Addresses 00h to 18h correspond to special function registers. complete 15-bit address is latched internally. Each access Attempting to load addresses above 18h is an illegal condition; causes the latched address value to be incremented the FM31276/FM31278 will return a NACK and abort the I2C automatically. The current address is the value that is held in the transaction. latch; either a newly written value or the address following the Data Transfer last access. The current address will be held for as long asVDD>VTP or until a new value is written. Reads always use After the address bytes have been transmitted, data transfer the current address. A random read address can be loaded by between the bus master and the FM31276/FM31278 can begin. beginning a write operation as explained below. For a read operation the FM31276/FM31278 will place 8 data After transmission of each data byte, just prior to the bits on the bus then wait for an acknowledge from the master. If acknowledge, the FM31276/FM31278 increments the internal the acknowledge occurs, the FM31276/FM31278 will transfer address latch. This allows the next sequential byte to be the next sequential byte. If the acknowledge is not sent, the FM31276/FM31278 will end the read operation. For a write accessed with no additional addressing. After the last address operation, the FM31276/FM31278 will accept 8 data bits from (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed the master then send an acknowledge. All data transfer occurs with a single read or write operation. MSB (most significant bit) first. Document Number: 001-86393 Rev. *E Page 22 of 35

FM31276/FM31278 Memory Operation bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFFh to 0000h. The FM31276/FM31278 is designed to operate in a manner very Unlike other nonvolatile memory technologies, there is no similar to other I2C interface memory products. The major effective write delay with F-RAM. Since the read and write differences result from the higher performance write capability of access times of the underlying memory are the same, the user F-RAM technology. These improvements result in some experiences no delay through the bus. The entire memory cycle differences between the FM31276/FM31278 and a similar occurs in less time than a single bus clock. Therefore, any configuration EEPROM during writes. The complete operation operation including read or write can occur immediately following for both writes and reads is explained below. a write. Acknowledge polling, a technique used with EEPROMs The memory address for FM31276 range from 0x0000 to to determine if a write is complete is unnecessary and will always 0x1FFFF, and for FM31278, they range from 0x0000 to 0x7FFF. return a ready condition. Memory functionality is described with respect to FM31278 in the Internally, an actual memory write occurs after the 8th data bit is following sections. transferred. It will be complete before the acknowledge is sent. Memory Write Operation Therefore, if the user desires to abort a write without altering the memory contents, this should be done using START or STOP All writes begin with a slave address, then a memory address. condition prior to the 8th data bit. The FM31276/FM31278 uses The bus master indicates a write operation by setting the LSB of no page buffering. the slave address (R/W bit) to a ‘0’. After addressing, the bus Figure 17 and Figure 18 below illustrate a single-byte and master sends each byte of data to the memory and the memory multiple-byte write cycles. generates an acknowledge condition. Any number of sequential Figure 17. Single-Byte Write Start Address & Data Stop By Master S Slave Address 0 A Address MSB A Address LSB A Data Byte A P By F-RAM Acknowledge Figure 18. Multi-Byte Write Start Stop Address & Data By Master S Slave Address 0 A Address MSB A Address LSB A Data Byte A Data Byte A P By F-RAM Acknowledge Document Number: 001-86393 Rev. *E Page 23 of 35

FM31276/FM31278 Memory Read Operation address read with multiple byte transfers. After each byte the internal address counter will be incremented. There are two basic types of read operations. They are current address read and selective address read. In a current address Note Each time the bus master acknowledges a byte, this read, the FM31276/FM31278 uses the internal address latch to indicates that the FM31276/FM31278 should read out the next supply the address. In a selective read, the user performs a sequential byte. procedure to set the address to a specific value. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus Current Address & Sequential Read contention as the FM31276/FM31278 attempts to read out As mentioned above the FM31276/FM31278 uses an internal additional data onto the bus. The four valid methods are: latch to supply the address for a read operation. A current 1.The bus master issues a no-acknowledge in the 9th clock address read uses the existing value in the address latch as a cycle and a STOP in the 10th clock cycle. This is illustrated in starting place for the read operation. The system reads from the the diagrams below. This is preferred. address immediately following that of the last operation. 2.The bus master issues a no-acknowledge in the 9th clock To perform a current address read, the bus master supplies a cycle and a START in the 10th. slave address with the LSB set to a ‘1’. This indicates that a read 3.The bus master issues a STOP in the 9th clock cycle. operation is requested. After receiving the complete slave address, the FM31276/FM31278 will begin shifting out data from 4.The bus master issues a START in the 9th clock cycle. the current address on the next clock. The current address is the If the internal address reaches 7FFFh, it will wrap around to value held in the internal address latch. 0000h on the next read cycle. Figure 19 and Figure 20 below Beginning with the current address, the bus master can read any show the proper operation for current address reads. number of bytes. Thus, a sequential read is simply a current Figure 19. Current Address Read No By Master Start Address Acknowledge Stop S Slave Address 1 A Data Byte 1 P By F-RAM Acknowledge Data Figure 20. Sequential Read No Start Address Acknowledge Acknowledge By Master Stop S Slave Address 1 A Data Byte A Data Byte 1 P By F-RAM Acknowledge Data Document Number: 001-86393 Rev. *E Page 24 of 35

FM31276/FM31278 Selective (Random) Read operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address There is a simple technique that allows a user to select a random latch. After the FM31276/FM31278 acknowledges the address, address location as the starting point for a read operation. This the bus master issues a START condition. This simultaneously involves using the first three bytes of a write operation to set the aborts the write operation and allows the read command to be internal address followed by subsequent read operations. issued with the slave address LSB set to a '1'. The operation is To perform a selective read, the bus master sends out the slave now a current address read. address with the LSB (R/W) set to ‘0’. This specifies a write Figure 21. Selective (Random) Read Start No By Master Address Start Address Acknowledge Stop S Slave Address 0 A Address MSB A Address LSB A S Slave Address 1 A Data Byte 1 P By F-RAM Data Acknowledge RTC/Companion Write Operation Note Although not required, it is recommended that A5-A7 in the register address byte are zeros in order to preserve compatibility All RTC and Companion writes operate in a similar manner to with future devices. memory writes. The distinction is that a different device ID is used and only one byte address is needed instead of two byte address. Figure22 illustrates a single byte write to this device. Figure 22. Single Byte Write Start Address & Data Stop By Master S Slave Address 0 A 0 0 0 Address A Data Byte A P By F-RAM Acknowledge RTC/Companion Read Operation register to be modified without affecting the current address of the other register. For example, this would allow an interrupted As with writes, a read operation begins with the Slave Address. read to the memory while still providing fast access to an RTC To perform a register read, the bus master supplies a Slave register. A subsequent memory read will then continue from the Address with the LSB set to ‘1’. This indicates that a read memory address where it previously left off, without requiring the operation is requested. After receiving the complete Slave load of a new memory address. However, a write sequence Address, the FM31276/FM31278 will begin shifting data out from always requires an address to be supplied. the current register address on the next clock. Auto-increment operates for the special function registers as with the memory Addressing FRAM Array in the FM31276/FM31278 address. A current address read for the registers look exactly like Family the memory except that the device ID is different. The FM31276/FM31278 family includes 64-Kbit and 256-Kbit The FM31276/FM31278 contains two separate address memory densities. The following 2-byte address field is shown registers, one for the memory address and the other for the for each density. register address. This allows the contents of one address Part Number 1st Address Byte 2nd Address Byte FM31276 X X X A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FM31278 X A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Document Number: 001-86393 Rev. *E Page 25 of 35

FM31276/FM31278 Maximum Ratings Surface mount lead soldering temperature (3 seconds) ..............................................................+260 C Exceeding maximum ratings may shorten the useful life of the DC output current device. These user guidelines are not tested. (1 output at a time, 1s duration) ..................................15 mA Storage temperature ................................–55 C to +125 C Electrostatic Discharge Voltage Ambient Temperature Human Body Model (AEC-Q100-002 Rev. D) ..................... 2 kV with power applied ...................................–55 C to +125 C Charged Device Model (AEC-Q100-011 Rev. B) .............1.25 kV Supply voltage on V relative to V .........–1.0 V to +7.0 V Machine Model (AEC-Q100-003 Rev. E) ............................100 V DD SS Input voltage ...........–1.0 V to +7.0 V and V < V + 1.0 V Latch-up current ..................................................> ±100 mA IN DD Backup supply voltage .................................–1.0 V to +4.5 V Note PFI input voltage must not exceed 4.5 V. The “V < V + 1.0 V” restriction does not apply to the SCL and IN DD DC voltage applied to outputs SDA inputs which do not employ a diode to V . DD in High-Z state ....................................–0.5 V to V + 0.5 V DD Operating Range Transient voltage (< 20 ns) on any pin to ground potential ............–2.0 V to V + 2.0 V DD Range Ambient Temperature (T ) V A DD Package power dissipation capability Industrial –40 C to +85 C 4.0 V to 5.5 V (T = 25 °C) .................................................................1.0 W A DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [1] Max Unit V [2] Power supply 4.0 – 5.5 V DD I Average V current SCL toggling f = 100 kHz – – 500 A DD DD SCL between f = 400 kHz – – 900 A V – 0.3 V and V , SCL DD SS other inputs f = 1 MHz – – 1500 A SCL V or V – 0.3 V. SS DD I V standby current SCL = SDA = V . – – 150 A SB DD DD All other inputs V or V . Stop SS DD command issued. V [3] RTC backup voltage T = +25 C to +85 C 1.55 – 3.75 V BAK A T = –40 C to +25 C 1.90 – 3.75 V A I RTC backup current V = 3.0 V, T = +25 C, – – 1.4 A BAK BAK A V < 2.4 V, V = 3.0 V DD BAK oscillator running, T = +85 C, – – 2.1 A A CNT1, CNT2 at V = 3.0 V BAK V . BAK T = +25 C, – – 1.15 A A V = 2.0 V BAK T = +85 C, – – 1.75 A A V = 2.0 V BAK I [4] Trickle charge current Fast Charge Off 50 – 120 A BAKTC with V = 0 V (FC = ‘0’) BAK Fast Charge On 200 – 2500 A (FC = ‘1’) Notes 1. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested. 2. Full complete operation. Supervisory circuits, RTC, etc operate to lower voltages as specified. 3. The VBAK trickle charger automatically regulates the maximum voltage on this pin for capacitor backup applications. 4. VBAK will source current when trickle charge is enabled (VBC bit = ‘1’), VDD > VBAK, and VBAK < VBAK max. Document Number: 001-86393 Rev. *E Page 26 of 35

FM31276/FM31278 DC Electrical Characteristics (continued) Over the Operating Range Parameter Description Test Conditions Min Typ [1] Max Unit V V trip point voltage, VTP = 0 RST is asserted active when V < V . 3.75 3.90 4.00 V TP1 DD DD TP V V trip point voltage, VTP = 1 RST is asserted active when V < V . 4.20 4.40 4.50 V TP2 DD DD TP V [5] V for valid RST I = 80 A at V V > V min 0 – – V RST DD OL OL BAK BAK V < V min 1.6 – – V BAK BAK I Input leakage current V < V < V Does not apply to A0, A1, – – ±1 A LI SS IN DD. X1, PFI, RST, or X2 I Output leakage current V < V < V . Does not apply to RST, – – ±1 A LO SS OUT DD X1, or X2 V [6] Input LOW voltage All inputs except as – 0.3 – 0.3 × V V IL DD listed below CNT1, CNT2 – 0.3 – 0.5 V battery-backed (V < 2.5 V) DD CNT1, CNT2 – 0.3 – 0.8 V (V > 2.5 V) DD V Input HIGH voltage All inputs except as 0.7 × V – V + 0.3 V IH DD DD listed below CNT1, CNT2 V – 0.5 – V + 0.3 V BAK BAK battery-backed (V < 2.5 V) DD CNT1, CNT2 0.7 × V – V + 0.3 V DD DD (V > 2.5 V) DD PFI (comparator – – 3.75 V input) V Output HIGH voltage I = –2 mA 2.4 – – V OH OH V Output LOW voltage I = 3 mA – – 0.4 V OL OL R Pull-up resistance for RST 50 – 400 k RST inactive R Input resistance (A1–A0) For V = V (Max) 20 – – k in IN IL For V = V (Min) 1 – – M IN IH V Power fail input reference voltage 1.140 1.20 1.225 V PFI V Power fail input (PFI) hysteresis – – 100 mV HYS (rising) Notes 5. The minimum VDD to guarantee the level of RST remains a valid VOL level. 6. Includes RST input detection of external reset condition to trigger driving of RST signal by FM31276/FM31278. Document Number: 001-86393 Rev. *E Page 27 of 35

FM31276/FM31278 Data Retention and Endurance Parameter Description Test condition Min Max Unit T Data retention T = 85 C 10 – Years DR A T = 75 C 38 – A T = 65 C 151 – A NV Endurance Over operating temperature 1014 – Cycles C Capacitance Parameter [7] Description Test Conditions Typ Max Unit C Input/Output pin capacitance T = 25 C, f = 1 MHz, V = V (typ) – 8 pF IO A DD DD C [8] X1, X2 crystal pin capacitance 12 – pF XTL Thermal Resistance Parameter [7] Description Test Conditions 14-pin SOIC Unit  Thermal resistance Test conditions follow standard test methods and 80 C/W JA (junction to ambient) procedures for measuring thermal impedance, per EIA /  Thermal resistance JESD51. 29 C/W JC (junction to case) AC Test Loads and Waveforms Figure 23. AC Test Loads and Waveforms 5.5V 1.7 k OUTPUT 100 pF AC Test Conditions Input pulse levels .................................10% and 90% of V DD Input rise and fall times .................................................10 ns Input and output timing reference levels ................0.5 × V DD Output load capacitance ............................................100 pF Notes 7. This parameter is characterized and not 100% tested. 8. The crystal attached to the X1/X2 pins must be rated as 6 pF/12.5 pF. Document Number: 001-86393 Rev. *E Page 28 of 35

FM31276/FM31278 Supervisor Timing Over the Operating Range Parameter Description Min Max Units t RST active (LOW) after V > V 100 200 ms RPU DD TP t [9] RST response time to V < V (noise filter) 10 25 s RNR DD TP t [9, 10] V power-up ramp rate 50 – s/V VR DD t [9, 10] V power-down ramp rate 100 – s/V VF DD t [11] Pulse width of RST for watchdog reset 100 200 ms WDP t [11] Timeout of watchdog t 2 × t ms WDOG DOG DOG f Frequency of event counters 0 10 MHz CNT t RTC Oscillator time to start – 2 s OSC Figure 24. RST Timing V t VF tVR DD VTP V RST t RNR t RPU RST Notes 9. This parameter is characterized and not 100% tested. 10.Slope measured at any point on VDD waveform. 11.tDOG is the programmed time in register in register 0Ah, VDD > VTP, and tRPU satisfied. Document Number: 001-86393 Rev. *E Page 29 of 35

FM31276/FM31278 AC Switching Characteristics Over the Operating Range Parameter [12] Cypress Alt. Description Min Max Min Max Min Max Unit Parameter Parameter f SCL clock frequency 0 100 0 400 0 1000 kHz SCL t Start condition setup for repeated Start 4.7 – 0.6 – 0.25 – s SU; STA t Start condition hold time 4.0 – 0.6 – 0.25 – s HD;STA t Clock LOW period 4.7 – 1.3 – 0.6 – s LOW t Clock HIGH period 4.0 – 0.6 – 0.4 – s HIGH t t Data in setup 250 – 100 – 100 – ns SU;DAT SU;DATA t t Data in hold 0 – 0 – 0 – ns HD;DAT HD;DATA t Data output hold (from SCL @ V ) 0 – 0 – 0 – ns DH IL t [13] t Input rise time – 1000 – 300 – 300 ns R r t [13] t Input fall time – 300 – 300 – 100 ns F f t STOP condition setup 4 – 0.6 0.25 – s SU;STO t t SCL LOW to SDA Data Out Valid – 3 0.9 – 0.55 s AA VD;DATA t Bus free before new transmission 4.7 – 1.3 – 0.5 – s BUF t Noise suppression time constant on SCL, SDA – 50 50 – 50 ns SP Figure 25. Read Bus Timing Diagram t tR ` tF HIGH tLOW tSP tSP SCL tSU:SDA tBUF 1/fSCL tHD:DAT t SU:DAT SDA tAA tDH Start Stop Start Acknowledge Figure 26. Write Bus Timing Diagram t HD:DAT SCL tHD:STA tSU:DAT tAA tSU:STO SDA Start Stop Start Acknowledge Notes 12.Test conditions assume a signal transition time of 10 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 100 pF load capacitance shown in Figure 23 on page 28. 13.This parameter is characterized and not 100% tested. Document Number: 001-86393 Rev. *E Page 30 of 35

FM31276/FM31278 Ordering Information Package Operating Ordering Code Package Type Diagram Range FM31276-G 51-85067 14-pin SOIC Industrial FM31276-GTR 51-85067 14-pin SOIC FM31278-G 51-85067 14-pin SOIC FM31278-GTR 51-85067 14-pin SOIC All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 31 XXX - G XX Option: XX = blank or TR blank = Standard; TR = Tape and Reel Package Type: G = 14-pin SOIC Density: XXX = 276 or 278 276 = 64-Kbit; 278 = 256-Kbit I2C Processor Companion Cypress Document Number: 001-86393 Rev. *E Page 31 of 35

FM31276/FM31278 Package Diagram Figure 27. 14-pin SOIC (150 Mils) Package Outline, 51-85067 51-85067 *E Document Number: 001-86393 Rev. *E Page 32 of 35

FM31276/FM31278 Acronyms Document Conventions Units of Measure Acronym Description EEPROM Electrically Erasable Programmable Read-Only Symbol Unit of Measure Memory °C degree Celsius EIA Electronic Industries Alliance Hz hertz F-RAM Ferroelectric Random Access Memory kHz kilohertz I2C Inter-Integrated Circuit k kilohm I/O Input/Output Mbit megabit JEDEC Joint Electron Devices Engineering Council MHz megahertz JESD JEDEC Standards A microampere LSB Least Significant Bit F microfarad s microsecond MSB Most Significant Bit mA milliampere NMI Non Maskable interrupt ms millisecond RoHS Restriction of Hazardous Substances ns nanosecond SOIC Small Outline Integrated Circuit  ohm % percent pF picofarad V volt W watt Document Number: 001-86393 Rev. *E Page 33 of 35

FM31276/FM31278 Document History Page Document Title: FM31276/FM31278, 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM Document Number: 001-86393 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 3916896 GVCH 02/28/2013 New data sheet. *A 3924836 GVCH 03/07/2013 Changed status to Production. Removed FM31274, FM31272 parts related information in all instances across the document. Removed 4Kb and 8Kb memory size related information in all instances across the document. Updated formatting. *B 3985209 GVCH 05/02/2013 Updated DC Electrical Characteristics: Changed minimum value of V parameter from 3.80 V to 3.75 V. TP1 Changed minimum value of V parameter from 4.25 V to 4.20 V. TP2 Changed minimum value of V parameter from 1.175 V to 1.140 V. PFI *C 4333096 GVCH 05/05/2014 Updated Real-time Clock Operation: Updated Crystal Oscillator: Updated description (Added use of 6 pF crystal). Updated Maximum Ratings: Added “Maximum junction temperature” and its details. Added “DC voltage applied to outputs in High-Z state” and its details. Added “Transient voltage (< 20 ns) on any pin to ground potential” and its details. Added “Package power dissipation capability (T = 25 °C)” and its details. A Added “DC output current (1 output at a time, 1s duration)” and its details. Added “Latch-up current” and its details. Removed “Package Moisture Sensitivity Level” and its details. Updated Data Retention and Endurance: Updated details corresponding to T parameter. DR Added NV parameter and its details. C Updated Capacitance: Changed typical value of C parameter from 25 pF to 12 pF. XTL Added Thermal Resistance. Updated Package Diagram: Removed SOIC Package Marking Scheme. Updated to Cypress template. *D 4562106 GVCH 11/05/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *E 6072167 GVCH 02/16/2018 Updated Register Map: Updated Table6: Removed “VTP1” bit from bit 1 corresponding to address “0Bh”. Replaced “VTP0” with “VTP” in bit 0 corresponding to address “0Bh”. Updated details in “Description” column corresponding to OSCEN (to add t OSC time in the 01h register). Updated DC Electrical Characteristics: Changed typical value of V parameter from 4.00 V to 4.40 V. TP2 Updated Supervisor Timing: Added t parameter and its details. OSC Updated Package Diagram: spec 51-85067 – Changed revision from *D to *E. Updated to new template. Document Number: 001-86393 Rev. *E Page 34 of 35

FM31276/FM31278 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Arm® Cortex® Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Automotive cypress.com/automotive Cypress Developer Community Clocks & Buffers cypress.com/clocks Community | Projects | Video | Blogs | Training | Components Interface cypress.com/interface Technical Support Internet of Things cypress.com/iot cypress.com/support Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless © Cypress Semiconductor Corporation, 2013-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-86393 Rev. *E Revised February 16, 2018 Page 35 of 35

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: C ypress Semiconductor: FM31276-GTR FM31278-G FM31276-G FM31278-GTR