FM25640B 64-Kbit (8 K × 8) Serial (SPI) Automotive F-RAM 64-Kbit (8 K × 8) Serial (SPI) Automotive F-RAM Features Functional Description ■64-Kbit ferroelectric random access memory (F-RAM) logically The FM25640B is a 64-Kbit nonvolatile memory employing an organized as 8 K × 8 advanced ferroelectric process. A ferroelectric random access ❐High-endurance 10 trillion (1013) read/writes memory or F-RAM is nonvolatile and performs reads and writes ❐121-year data retention (See the Data Retention and similar to a RAM. It provides reliable data retention for 121 years Endurance table) while eliminating the complexities, overhead, and system level ❐NoDelay™ writes reliability problems caused by serial flash, EEPROM, and other ❐Advanced high-reliability ferroelectric process nonvolatile memories. ■Very fast serial peripheral interface (SPI) Unlike serial flash and EEPROM, the FM25640B performs write ❐Up to 4 MHz frequency operations at bus speed. No write delays are incurred. Data is ❐Direct hardware replacement for serial flash and EEPROM written to the memory array immediately after each byte is ❐Supports SPI mode 0 (0, 0) and mode 3 (1, 1) successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the ■Sophisticated write protection scheme product offers substantial write endurance compared with other ❐Hardware protection using the Write Protect (WP) pin nonvolatile memories. The FM25640B is capable of supporting ❐Software protection using Write Disable instruction 1013 read/write cycles, or 10 million times more write cycles than ❐Software block protection for 1/4, 1/2, or entire array EEPROM. ■Low power consumption These capabilities make the FM25640B ideal for nonvolatile ❐300 A active current at 1 MHz memory applications requiring frequent or rapid writes. ❐10 A (typ) standby current at +85 C Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the ■Voltage operation: VDD = 4.5 V to 5.5 V long write time of serial flash or EEPROM can cause data loss. ■Automotive-E temperature: –40 C to +125 C The FM25640B provides substantial benefits to users of serial ■8-pin small outline integrated circuit (SOIC) package EEPROM or flash as a hardware drop-in replacement. The FM25640B uses the high-speed SPI bus, which enhances the ■AEC Q100 Grade 1 compliant high-speed write capability of F-RAM technology. The device ■Restriction of hazardous substances (RoHS) compliant specifications are guaranteed over an automotive-e temperature range of –40 C to +125 C. For a complete list of related resources, click here. Logic Block Diagram WP Instruction Decoder CS Clock Generator HOLD Control Logic Write Protect SCK 8 K x 8 F-RAM Array Instruction Register Address Register 13 8 Counter SI SO Data I /O Register 3 Nonvolatile Status Register CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-86148 Rev. *C Revised August 14, 2015

FM25640B Contents Pinout ................................................................................3 Data Retention and Endurance .....................................12 Pin Definitions ..................................................................3 Example of an F-RAM Life Time Functional Overview ........................................................4 in an AEC-Q100 Automotive Application .....................12 Memory Architecture ........................................................4 Capacitance ....................................................................12 Serial Peripheral Interface – SPI Bus ..............................4 Thermal Resistance ........................................................12 SPI Overview ...............................................................4 AC Test Conditions ........................................................12 SPI Modes ...................................................................5 AC Switching Characteristics .......................................13 Power Up to First Access ............................................6 Power Cycle Timing .......................................................15 Command Structure ....................................................6 Ordering Information ......................................................16 WREN - Set Write Enable Latch .................................6 Ordering Code Definitions .........................................16 WRDI - Reset Write Enable Latch ...............................6 Package Diagram ............................................................17 Status Register and Write Protection .............................6 Acronyms ........................................................................18 RDSR - Read Status Register .....................................7 Document Conventions .................................................18 WRSR - Write Status Register ....................................7 Units of Measure .......................................................18 Memory Operation ............................................................8 Document History Page .................................................19 Write Operation ...........................................................8 Sales, Solutions, and Legal Information ......................20 Read Operation ...........................................................8 Worldwide Sales and Design Support .......................20 HOLD Pin Operation ...................................................9 Products ....................................................................20 Endurance .................................................................10 PSoC® Solutions ......................................................20 Maximum Ratings ...........................................................11 Cypress Developer Community .................................20 Operating Range .............................................................11 Technical Support .....................................................20 DC Electrical Characteristics ........................................11 Document Number: 001-86148 Rev. *C Page 2 of 20

FM25640B Pinout Figure 1. 8-pin SOIC pinout CS 1 8 VDD SO 2 Top View 7 HOLD not to scale WP 3 6 SCK VSS 4 5 SI Pin Definitions Pin Name I/O Type Description CS Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power standby mode, ignores other inputs, and tristates the output. When LOW, the device internally activates the SCK signal. A falling edge on CS must occur before every opcode. SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may be any value between 0 and 4 MHz and may be interrupted at any time. SI[1] Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. SO[1] Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all other times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock. WP Input Write Protect. This active LOW pin prevents write operation to the Status Register when WPEN is set to ‘1’. This is critical because other write protection features are controlled through the Status Register. A complete explanation of write protection is provided in Status Register and Write Protection on page 7. This pin must be tied to V if not used. Note that the function of WP is different from the DD FM25040 where it prevents all writes to the part. HOLD Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for another task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must be tied to V if not DD used. V Power supply Ground for the device. Must be connected to the ground of the system. SS V Power supply Power supply input to the device. DD Note 1. SI may be connected to SO for a single pin data interface. Document Number: 001-86148 Rev. *C Page 3 of 20

FM25640B Functional Overview edge of SCK starting from the first rising edge after CS goes active. The FM25640B is a serial F-RAM memory. The memory array is The SPI protocol is controlled by opcodes. These opcodes logically organized as 8,192 × 8 bits and is accessed using an specify the commands from the bus master to the slave device. industry standard serial peripheral interface (SPI) bus. The After CS is activated, the first byte transferred from the bus functional operation of the F-RAM is similar to serial flash and master is the opcode. Following the opcode, any addresses and serial EEPROMs. The major difference between the FM25640B data are then transferred. The CS must go inactive after an and a serial flash or EEPROM with the same pinout is the operation is complete and before a new opcode can be issued. F-RAM's superior write performance, high endurance, and low The commonly used terms in the SPI protocol are as follows: power consumption. SPI Master Memory Architecture The SPI master device controls the operations on a SPI bus. An When accessing the FM25640B, the user addresses 8K SPI bus may have only one master with one or more slave locations of eight data bits each. These eight data bits are shifted devices. All the slaves share the same SPI bus lines and the in or out serially. The addresses are accessed using the SPI master may select any of the slave devices using the CS pin. All protocol, which includes a chip select (to permit multiple devices of the operations must be initiated by the master activating a on the bus), an opcode, and a two-byte address. The upper 3 bits slave device by pulling the CS pin of the slave LOW. The master of the address range are 'don't care' values. The complete also generates the SCK and all the data transmission on SI and address of 13 bits specifies each byte address uniquely. SO lines are synchronized with this clock. Most functions of the FM25640B are either controlled by the SPI SPI Slave interface or handled by on-board circuitry. The access time for The SPI slave device is activated by the master through the Chip the memory operation is essentially zero, beyond the time Select line. A slave device gets the SCK as an input from the SPI needed for the serial protocol. That is, the memory is read or master and all the communication is synchronized with this written at the speed of the SPI bus. Unlike a serial flash or clock. An SPI slave never initiates a communication on the SPI EEPROM, it is not necessary to poll the device for a ready bus and acts only on the instruction from the master. condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write operation The FM25640B operates as an SPI slave and may share the SPI is complete. This is explained in more detail in the interface bus with other SPI slave devices. section. Chip Select (CS) Note The FM25640B contains no power management circuits To select any slave device, the master needs to pull down the other than a simple internal power-on reset circuit. It is the user’s corresponding CS pin. Any instruction can be issued to a slave responsibility to ensure that V is within datasheet tolerances DD device only while the CS pin is LOW. When the device is not to prevent incorrect operation. It is recommended that the part is selected, data through the SI pin is ignored and the serial output not powered down with chip enable active. pin (SO) remains in a high-impedance state. Serial Peripheral Interface – SPI Bus Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each active Chip The FM25640B is a SPI slave device and operates at speeds up Select cycle. to 4 MHz. This high-speed serial bus provides high-performance serial communication to a SPI master. Many common Serial Clock (SCK) microcontrollers have hardware SPI ports allowing a direct The Serial Clock is generated by the SPI master and the interface. It is quite simple to emulate the port using ordinary port communication is synchronized with this clock after CS goes pins for microcontrollers that do not. The FM25640B operates in LOW. SPI Mode 0 and 3. The FM25640B enables SPI modes 0 and 3 for data SPI Overview communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are The SPI is a four-pin interface with Chip Select (CS), Serial Input issued on the falling edge. Therefore, the first rising edge of SCK (SI), Serial Output (SO), and Serial Clock (SCK) pins. signifies the arrival of the first bit (MSB) of a SPI instruction on The SPI is a synchronous serial interface, which uses clock and the SI pin. Further, all data inputs and outputs are synchronized data pins for memory access and supports multiple devices on with SCK. the data bus. A device on the SPI bus is activated using the CS pin. Data Transmission (SI/SO) The relationship between chip select, clock, and data is dictated The SPI data bus consists of two lines, SI and SO, for serial data by the SPI mode. This device supports SPI modes 0 and 3. In communication. SI is also referred to as Master Out Slave In both of these modes, data is clocked into the F-RAM on the rising (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while Document Number: 001-86148 Rev. *C Page 4 of 20

FM25640B the slave responds through the SO pin. Multiple slave devices these three bits are ‘don’t care’, Cypress recommends that these may share the SI and SO lines as described earlier. bits be set to 0s to enable seamless transition to higher memory densities. The FM25640B has two separate pins for SI and SO, which can be connected with the master as shown in Figure 2. Serial Opcode For a microcontroller that has no dedicated SPI bus, a After the slave device is selected with CS going LOW, the first general-purpose port may be used. To reduce hardware byte received is treated as the opcode for the intended operation. resources on the controller, it is possible to connect the two data FM25640B uses the standard opcodes for memory accesses. pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins. Figure 3 shows such a configuration, which uses only three pins. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the Most Significant Bit (MSB) device ignores any additional serial data on the SI pin until the The SPI protocol requires that the first bit to be transmitted is the next falling edge of CS, and the SO pin remains tristated. Most Significant Bit (MSB). This is valid for both address and data transmission. Status Register The 64-Kbit serial F-RAM requires a 2-byte address for any read FM25640B has an 8-bit Status Register. The bits in the Status or write operation. Because the address is only 13 bits, the first Register are used to configure the device. These bits are three bits which are fed in are ignored by the device. Although described in Table 3 on page 7. Figure 2. System Configuration with SPI port SCK MOSI MISO SCK SI SO SCK SI SO SPI FM25640B FM25640B Microcontroller CS HOLD WP CS HOLD WP CS1 HOLD1 WP1 CS2 HOLD2 WP2 Figure 3. System Configuration without SPI port P1.0 P1.1 SCK SI SO Microcontroller FM25640B CS HOLD WP P1.2 ■SPI Mode 3 (CPOL = 1, CPHA = 1) SPI Modes For both these modes, the input data is latched in on the rising FM25640B may be driven by a microcontroller with its SPI edge of SCK starting from the first rising edge after CS goes peripheral running in either of the following two modes: active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles is considered. The output data ■SPI Mode 0 (CPOL = 0, CPHA = 0) is available on the falling edge of SCK. Document Number: 001-86148 Rev. *C Page 5 of 20

FM25640B The two SPI modes are shown in Figure 4 on page 6 and Figure WREN - Set Write Enable Latch 5 on page 6. The status of the clock when the bus master is not The FM25640B will power up with writes disabled. The WREN transferring data is: command must be issued before any write operation. Sending ■SCK remains at 0 for Mode 0 the WREN opcode allows the user to issue subsequent opcodes for write operations. These include writing the Status Register ■SCK remains at 1 for Mode 3 (WRSR) and writing the memory (WRITE). The device detects the SPI mode from the status of the SCK pin Sending the WREN opcode causes the internal Write Enable when the device is selected by bringing the CS pin LOW. If the Latch to be set. A flag bit in the Status Register, called WEL, SCK pin is LOW when the device is selected, SPI Mode 0 is indicates the state of the latch. WEL = ’1’ indicates that writes are assumed and if the SCK pin is HIGH, it works in SPI Mode3. permitted. Attempting to write the WEL bit in the Status Register has no effect on the state of this bit – only the WREN opcode can Figure 4. SPI Mode 0 set this bit. The WEL bit will be automatically cleared on the rising edge of CS following a WRDI, a WRSR, or a WRITE operation. CS This prevents further writes to the Status Register or the F-RAM array without another WREN command. Figure 6 illustrates the 0 1 2 3 4 5 6 7 WREN command bus configuration. SCK Figure 6. WREN Bus Configuration SI 7 6 5 4 3 2 1 0 CS MSB LSB 0 1 2 3 4 5 6 7 SCK Figure 5. SPI Mode 3 SI 0 0 0 0 0 1 1 0 CS HI-Z SO 0 1 2 3 4 5 6 7 WRDI - Reset Write Enable Latch SCK The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled SI 7 6 5 4 3 2 1 0 by reading the WEL bit in the Status Register and verifying that MSB LSB WEL is equal to ‘0’. Figure 7 illustrates the WRDI command bus configuration. Power Up to First Access The FM25640B is not accessible for a t time after power up. Figure 7. WRDI Bus Configuration PU Users must comply with the timing parameter t , which is the PU minimum time from V (min) to the first CS LOW. CS DD 0 1 2 3 4 5 6 7 Command Structure SCK There are six commands, called opcodes, that can be issued by the bus master to the FM25640B. They are listed in Table1. These opcodes control the functions performed by the memory. SI 0 0 0 0 0 1 0 0 Table 1. Opcode commands HI-Z SO Name Description Opcode WREN Set write enable latch 0000 0110b WRDI Write disable 0000 0100b RDSR Read Status Register 0000 0101b WRSR Write Status Register 0000 0001b READ Read memory data 0000 0011b WRITE Write memory data 0000 0010b Document Number: 001-86148 Rev. *C Page 6 of 20

FM25640B Status Register and Write Protection is organized as follows. (The default value shipped from the factory for bits in the Status Register is ‘0’.) The write protection features of the FM25640B are multi-tiered and are enabled through the status register. The Status Register Table 2. Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN (0) X (0) X (0) X (0) BP1 (0) BP0 (0) WEL (0) X (0) Table 3. Status Register Bit Definition Bit Definition Description Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write Enable Latch WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEL = '1' --> Write enabled WEL = '0' --> Write disabled Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7. Bit 4-6 Don’t care These bits are non-writable and always return ‘0’ upon read. Bit 7 (WPEN) Write Protect Enable bit Used to enable the function of Write Protect Pin (WP). For details, see Table 5 on page 7. Bits 0 and 4-6 are fixed at ‘0’; none of these bits can be modified. write to the Status Register. Thus the Status Register is Note that bit 0 (“Ready or Write in progress” bit in serial flash and write-protected only when WPEN = '1' and WP = '0'. EEPROM) is unnecessary, as the F-RAM writes in real-time and Table5 summarizes the write protection conditions. is never busy, so it reads out as a ‘0’. The BP1 and BP0 control the software write-protection features and are nonvolatile bits. Table 5. Write Protection The WEL flag indicates the state of the Write Enable Latch. Protected Unprotected Status Attempting to directly write the WEL bit in the Status Register has WEL WPEN WP Blocks Blocks Register no effect on its state. This bit is internally set and cleared via the 0 X X Protected Protected Protected WREN and WRDI commands, respectively. 1 0 X Protected Unprotected Unprotected BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write-protected as shown in 1 1 0 Protected Unprotected Protected Table4. 1 1 1 Protected Unprotected Unprotected Table 4. Block Memory Write Protection RDSR - Read Status Register BP1 BP0 Protected Address Range The RDSR command allows the bus master to verify the 0 0 None contents of the Status Register. Reading the status register provides information about the current state of the 0 1 1800h to 1FFFh (upper 1/4) write-protection features. Following the RDSR opcode, the 1 0 1000h to 1FFFh (upper 1/2) FM25640B will return one byte with the contents of the Status 1 1 0000h to 1FFFh (all) Register. WRSR - Write Status Register The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining The WRSR command allows the SPI bus master to write into the write protection features protect inadvertent changes to the block Status Register and change the write protect configuration by protect bits. setting the WPEN, BP0 and BP1 bits as required. Before issuing a WRSR command, the WP pin must be HIGH or inactive. Note The write protect enable bit (WPEN) in the Status Register that on the FM25640B, WP only prevents writing to the Status controls the effect of the hardware write protect (WP) pin. When Register, not the memory array. Before sending the WRSR the WPEN bit is set to '0', the status of the WP pin is ignored. command, the user must send a WREN command to enable When the WPEN bit is set to '1', a LOW on the WP pin inhibits a writes. Executing a WRSR command is a write operation and therefore, clears the Write Enable Latch. Document Number: 001-86148 Rev. *C Page 7 of 20

FM25640B Figure 8. RDSR Bus Configuration CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode SI 0 0 0 0 0 1 0 1 0 Data HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Figure 9. WRSR Bus Configuration (WREN not shown) CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Opcode Data SI 0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X MSB LSB HI-Z SO Memory Operation EEPROMs use page buffers to increase their write throughput. This compensates for the technology's inherently slow write The SPI interface, which is capable of a high clock frequency, operations. F-RAM memories do not have page buffers because highlights the fast write capability of the F-RAM technology. each byte is written to the F-RAM array immediately after it is Unlike serial flash and EEPROMs, the FM25640B can perform clocked in (after the eighth clock). This allows any number of sequential writes at bus speed. No page register is needed and bytes to be written without page buffer delays. any number of sequential writes may be performed. Note If the power is lost in the middle of the write operation, only Write Operation the last completed byte will be written. All writes to the memory begin with a WREN opcode. The WRITE Read Operation opcode is followed by a two-byte address containing the 13-bit After the falling edge of CS, the bus master can issue a READ address (A12-A0) of the first data byte to be written into the opcode. Following the READ command is a two-byte address memory. The upper three bits of the two-byte address are containing the 13-bit address (A12-A0) of the first byte of the ignored. Subsequent bytes are data bytes, which are written read operation. The upper three bits of the address are ignored. sequentially. Addresses are incremented internally as long as After the opcode and address are issued, the device drives out the bus master continues to issue clocks and keeps CS LOW. If the read data on the next eight clocks. The SI input is ignored the last address of 1FFFh is reached, the counter will roll over to during read data bytes. Subsequent bytes are data bytes, which 0000h. Data is written MSB first. The rising edge of CS are read out sequentially. Addresses are incremented internally terminates a write operation. A write operation is shown in Figure as long as the bus master continues to issue clocks and CS is 10. LOW. If the last address of 1FFFh is reached, the counter will roll Note When a burst write reaches a protected block address, the over to 0000h. Data is read MSB first. The rising edge of CS automatic address increment stops and all the subsequent data terminates a read operation and tristates the SO pin. A read bytes received for write will be ignored by the device. operation is shown in Figure 11. Document Number: 001-86148 Rev. *C Page 8 of 20

FM25640B Figure 10. Memory Write (WREN not shown) CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 ~~ SCK Opcode 13-bit Address Data ~~ SI 0 0 0 0 0 0 1 0 X X X A12A11A10A9 A8 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSBMSB LSB HI-Z SO Figure 11. Memory Read CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 ~~ SCK Opcode 13-bit Address ~~ SI 0 0 0 0 0 0 1 1 X X X A12A11A10 A9 A8 A3 A2 A1 A0 MSB LSB Data HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB HOLD Pin Operation HIGH while SCK is LOW will resume an operation. The transitions of HOLD must occur while SCK is LOW, but the SCK The HOLD pin can be used to interrupt a serial operation without and CS pin can toggle during a hold state. aborting it. If the bus master pulls the HOLD pin LOW while SCK is LOW, the current operation will pause. Taking the HOLD pin Figure 12. HOLD Operation[2] ~~ CS ~~ SCK HOLD ~~ ~~ SI VALID IN VALID IN ~~ SO Note 2. Figure shows HOLD operation for input mode and output mode. Document Number: 001-86148 Rev. *C Page 9 of 20

FM25640B Endurance F-RAM read and write endurance is virtually unlimited even at a 4 MHz clock rate. The FM25640B devices are capable of being accessed at least 1013 times, reads or writes. An F-RAM memory operates with a Table 6. Time to Reach Endurance Limit for Repeating read and restore mechanism. Therefore, an endurance cycle is 64-byte Loop applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of SCK Freq Endurance Endurance Years to Reach (MHz) Cycles/sec Cycles/year Limit rows and columns of 1K rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes 4 7,480 2.36 × 1011 42.3 are read or written. Each byte in the row is counted only once in 1 1,870 5.88 × 1010 170.1 an endurance calculation. Table6 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. Document Number: 001-86148 Rev. *C Page 10 of 20

FM25640B Maximum Ratings Package power dissipation capability (T = 25 °C) .................................................1.0 W A Exceeding maximum ratings may shorten the useful life of the Surface mount lead soldering device. These user guidelines are not tested. temperature (3 seconds) .........................................+260 C Storage temperature ................................–55 C to +150 C DC output current (1 output at a time, 1s duration) ....15 mA Maximum accumulated storage time Electrostatic Discharge Voltage At 150 °C ambient temperature .................................1000 h Human Body Model (AEC-Q100-002 Rev. E) ....................... 4 kV At 125 °C ambient temperature ................................11000 h At 85 °C ambient temperature ..............................121 Years Charged Device Model (AEC-Q100-011 Rev. B) ..............1.25 kV Ambient temperature Machine Model (AEC-Q100-003 Rev. E) ..............................300 V with power applied ...................................–55 °C to +125 °C Latch up current .....................................................> 140 mA Supply voltage on V relative to V .........–1.0 V to +7.0 V DD SS Operating Range Input voltage .............–1.0 V to +7.0 V and V < V +1.0 V IN DD DC voltage applied to outputs Range Ambient Temperature (T ) V A DD in High Z state ....................................–0.5 V to V + 0.5 V DD Automotive-E –40 C to +125 C 4.5 V to 5.5 V Transient voltage (< 20 ns) on any pin to ground potential .................–2.0 V to V + 2.0 V DD DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [3] Max Unit V Power supply 4.5 5.0 5.5 V DD I V supply current SCK toggling between f = 1 MHz – – 0.3 mA DD DD SCK V – 0.3 V and V , DD SS f = 4 MHz – – 1.2 mA other inputs SCK V or V – 0.3 V. SS DD SO = Open. I V standby current CS = V . All other T = 85 °C – – 10 A SB DD DD A inputs V or V . SS DD T = 125 °C – – 30 A A I Input leakage current V < V < V – – ±1 A LI SS IN DD I Output leakage current V < V < V – – ±1 A LO SS OUT DD V Input HIGH voltage 0.75 × V – V + 0.3 V IH DD DD V Input LOW voltage – 0.3 – 0.25 × V V IL DD V Output HIGH voltage I = –2 mA V – 0.8 – – V OH OH DD V Output LOW voltage I = 2 mA – – 0.4 V OL OL V [4] Input Hysteresis (CS and SCK pin) 0.05 × V – – V HYS DD Notes 3. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested. 4. This parameter is characterized but not 100% tested. Document Number: 001-86148 Rev. *C Page 11 of 20

FM25640B Data Retention and Endurance Parameter Description Test condition Min Max Unit T Data retention T = 125 C 11000 – Hours DR A T = 105 C 11 – Years A T = 85 C 121 – A NV Endurance Over operating temperature 1013 – Cycles C Example of an F-RAM Life Time in an AEC-Q100 Automotive Application An application does not operate under a steady temperature for the entire usage life time of the application. Instead, it is often expected to operate in multiple temperature environments throughout the application’s usage life time. Accordingly, the retention specification for F-RAM in applications often needs to be calculated cumulatively. An example calculation for a multi-temperature thermal profiles is given below. Acceleration Factor with respect to Tmax Profile Factor Profile Life Time A [5] P L (P) Tempeature Time Factor T t LT E---k--a--T-1--–T-----m--1---a----x-- P = ---------------------------1----------------------------- LP = PLTmax A = L-------T----m-----a----x---- = e --t--1---+--t--2---+--t--3---+--t--4--- A1 A2 A3 A4 T1 = 125 C t1 = 0.1 A1 = 1 T2 = 105 C t2 = 0.15 A2 = 8.67 8.33 > 10.46 Years T3 = 85 C t3 = 0.25 A3 = 95.68 T4 = 55 C t4 = 0.50 A4 = 6074.80 Capacitance Parameter [6] Description Test Conditions Max Unit C Output pin capacitance (SO) T = 25 C, f = 1 MHz, V = V (typ) 8 pF O A DD DD C Input pin capacitance 6 pF I Thermal Resistance Parameter Description Test Conditions 8-pin SOIC Unit  Thermal resistance Test conditions follow standard test methods and 147 C/W JA (junction to ambient) procedures for measuring thermal impedance, per EIA /  Thermal resistance JESD51. 47 C/W JC (junction to case) AC Test Conditions Input pulse levels .................................10% and 90% of V DD Input rise and fall times ...................................................5 ns Input and output timing reference levels ................0.5 × V DD Output load capacitance ..............................................30 pF Notes 5. Where k is the Boltzmann constant 8.617 × 10-5 eV/K, Tmax is the highest temperature specified for the product, and T is any temperature within the F-RAM product specification. All temperatures are in Kelvin in the equation. 6. This parameter is characterized but not 100% tested. Document Number: 001-86148 Rev. *C Page 12 of 20

FM25640B AC Switching Characteristics Over the Operating Range Parameters [7] Description Min Max Unit Cypress Alt. Parameter Parameter f – SCK Clock frequency 0 4 MHz SCK t – Clock HIGH time 100 – ns CH t – Clock LOW time 100 – ns CL t t Chip select setup 100 – ns CSU CSS t t Chip select hold 100 – ns CSH CSH t [8, 9] t Output disable time – 100 ns OD HZCS t t Output data valid time – 75 ns ODV CO t – Output hold time 0 – ns OH t – Deselect time 100 – ns D t [10, 11] – Data in rise time – 50 ns R t [10, 11] – Data in fall time – 50 ns F t t Data setup time 30 – ns SU SD t t Data hold time 20 – ns H HD t t HOLD setup time 70 – ns HS SH t t HOLD hold time 40 – ns HH HH t [8, 9] t HOLD LOW to HI-Z – 100 ns HZ HHZ t [9] t HOLD HIGH to data active – 50 ns LZ HLZ Notes 7. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 12. 8. tOD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 9. This parameter is characterized but not 100% tested. 10.Rise and fall times measured between 10% and 90% of waveform. 11.These parameters are guaranteed by design and are not tested. Document Number: 001-86148 Rev. *C Page 13 of 20

FM25640B Figure 13. Synchronous Data Timing (Mode 0) tD CS tCSU tCH tCL tCSH SCK tSU tH SI VALID IN VALID IN VALID IN tODV tOH tOD HI-Z HI-Z SO Figure 14. HOLD Timing ~~ CS ~~ SCK tHH tHH tHS tHS HOLD ~~ tSU ~~ SI VALID IN VALID IN tHZ tLZ ~~ SO Document Number: 001-86148 Rev. *C Page 14 of 20

FM25640B Power Cycle Timing Over the Operating Range Parameter Description Min Max Unit tPU Power-up VDD(min) to first access (CS LOW) 1 – ms tPD Last access (CS HIGH) to power-down (VDD(min)) 0 – µs tVR [12] VDD power-up ramp rate 30 – µs/V tVF [12] VDD power-down ramp rate 20 – µs/V Figure 15. Power Cycle Timing ~~ VDD(min) VDD(min) VDD tVR tVF tPU tPD CS ~~ Note 12.Slope measured at any point on VDD waveform. Document Number: 001-86148 Rev. *C Page 15 of 20

FM25640B Ordering Information Package Operating Ordering Code Package Type Diagram Range FM25640B-GA 51-85066 8-pin SOIC Automotive-E FM25640B-GATR 51-85066 8-pin SOIC All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 25 640 B - G A TR Option: blank = Standard; TR = Tape and Reel Temperature Range: A = Automotive-E (–40 C to +125 C) Package Type: G = 8-pin SOIC Die revision: B Density: 640 = 64-Kbit SPI F-RAM Cypress Document Number: 001-86148 Rev. *C Page 16 of 20

FM25640B Package Diagram Figure 16. 8-pin SOIC (150 Mils) Package Outline, 51-85066 51-85066 *G Document Number: 001-86148 Rev. *C Page 17 of 20

FM25640B Acronyms Document Conventions Acronym Description Units of Measure AEC Automotive Electronics Council Symbol Unit of Measure CPHA Clock Phase °C degree Celsius CPOL Clock Polarity Hz hertz EEPROM Electrically Erasable Programmable Read-Only kHz kilohertz Memory K kilohm EIA Electronic Industries Alliance Kbit kilobit I/O Input/Output kV kilovolt JEDEC Joint Electron Devices Engineering Council MHz megahertz JESD JEDEC Standards A microampere LSB Least Significant Bit s microsecond MSB Most Significant Bit mA milliampere F-RAM Ferroelectric Random Access Memory ms millisecond RoHS Restriction of Hazardous Substances ns nanosecond SPI Serial Peripheral Interface  ohm SOIC Small Outline Integrated Circuit % percent pF picofarad V volt W watt Document Number: 001-86148 Rev. *C Page 18 of 20

FM25640B Document History Page Document Title: FM25640B, 64-Kbit (8 K × 8) Serial (SPI) Automotive F-RAM Document Number: 001-86148 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 3912930 GVCH 02/25/2013 New data sheet. *A 4227122 GVCH 01/24/2014 Converted to Cypress standard format Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Added “Example of an F-RAM Life Time in an AEC-Q100 Automotive Applica- tion” table Added footnote 5 Added Thermal Resistance table Removed Package Marking Scheme (top mark) Removed Ramtron revision history Completing Sunset Review. *B 4724164 PSR 04/14/2015 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Package Diagram: spec 51-85066 – Changed revision from *F to *G. Updated to new template. *C 4884720 ZSK / PSR 08/14/2015 Updated Maximum Ratings: Updated ratings of “Storage temperature” (Replaced “+125 °C” with “+150 C”). Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Document Number: 001-86148 Rev. *C Page 19 of 20

FM25640B Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products PSoC® Solutions Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Interface cypress.com/go/interface Cypress Developer Community Lighting & Power Control cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training Memory cypress.com/go/memory Technical Support PSoC cypress.com/go/psoc cypress.com/go/support Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-86148 Rev. *C Revised August 14, 2015 Page 20 of 20 All products and company names mentioned in this document may be the trademarks of their respective holders.