FM24V10 2 1-Mbit (128K × 8) Serial (I C) F-RAM 1-Mbit (128K × 8) Serial (I2C) F-RAM Features Functional Description ■1-Mbit ferroelectric random access memory (F-RAM) logically The FM24V10 is a 1-Mbit nonvolatile memory employing an organized as 128K × 8 advanced ferroelectric process. A ferroelectric random access ❐High-endurance 100 trillion (1014) read/writes memory or F-RAM is nonvolatile and performs reads and writes ❐151-year data retention (See Data Retention and Endurance similar to a RAM. It provides reliable data retention for 151 years on page 13) while eliminating the complexities, overhead, and system-level ❐NoDelay™ writes reliability problems caused by EEPROM and other nonvolatile ❐Advanced high-reliability ferroelectric process memories. ■Fast two-wire Serial interface (I2C) Unlike EEPROM, the FM24V10 performs write operations at bus speed. No write delays are incurred. Data is written to the ❐Up to 3.4-MHz frequency memory array immediately after each byte is successfully ❐Direct hardware replacement for serial (I2C) EEPROM transferred to the device. The next bus cycle can commence ❐Supports legacy timings for 100 kHz and 400 kHz without the need for data polling. In addition, the product offers ■Device ID and Serial Number substantial write endurance compared with other nonvolatile ❐Manufacturer ID and Product ID memories. Also, F-RAM exhibits much lower power during writes ❐Unique Serial Number (FM24VN10) than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. The FM24V10 is ■Low power consumption capable of supporting 1014 read/write cycles, or 100 million times ❐175 A active current at 100 kHz more write cycles than EEPROM. ❐90 A (typ) standby current These capabilities make the FM24V10 ideal for nonvolatile ❐5 A (typ) sleep mode current memory applications, requiring frequent or rapid writes. ■Low-voltage operation: V = 2.0 V to 3.6 V Examples range from data logging, where the number of write DD cycles may be critical, to demanding industrial controls where the ■Industrial temperature: –40 C to +85 C long write time of EEPROM can cause data loss. The ■8-pin small outline integrated circuit (SOIC) package combination of features allows more frequent data writing with less overhead for the system. ■Restriction of hazardous substances (RoHS) compliant The FM24V10 provides substantial benefits to users of serial (I2C) EEPROM as a hardware drop-in replacement. The FM24VN10 is offered with a unique serial number that is read-only and can be used to identify a board or system. Both devices incorporate a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The device specifications are guaranteed over an industrial temperature range of –40 C to +85 C. For a complete list of related documentation, click here. Logic Block Diagram Address 128 K x 8 Counter Latch F-RAM Array 17 8 Serial to Parallel SDA Data Latch Converter 8 8 SCL WP Control Logic Device ID and Serial Number A2-A1 Errata: STOP condition is optional for sleep mode entry. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. CypressSemiconductorCorporation • 198 Champion Court • SanJose, CA 95134-1709 • 408-943-2600 Document Number: 001-84463 Rev. *J Revised December 26, 2018

FM24V10 Contents Pinout ................................................................................3 Capacitance ....................................................................13 Pin Definitions ..................................................................3 Thermal Resistance ........................................................13 Functional Overview ........................................................4 AC Test Loads and Waveforms .....................................13 Memory Architecture ........................................................4 AC Test Conditions ........................................................13 I2C Interface ......................................................................4 AC Switching Characteristics .......................................14 STOP Condition (P) .....................................................4 Power Cycle Timing .......................................................15 START Condition (S) ...................................................4 Ordering Information ......................................................16 Data/Address Transfer ................................................5 Ordering Code Definitions .........................................16 Acknowledge/No-acknowledge ...................................5 Package Diagram ............................................................17 Slave Device Address .................................................6 Acronyms ........................................................................18 High Speed Mode (Hs-mode) ......................................6 Document Conventions .................................................18 Addressing Overview ..................................................6 Units of Measure .......................................................18 Data Transfer ..............................................................6 Errata ...............................................................................19 Memory Operation ............................................................6 Part Numbers Affected ..............................................19 Write Operation ...........................................................6 FM24V10/FM24VN10 I2C F-RAM Read Operation ...........................................................7 Qualification Status ...........................................................19 Sleep Mode .................................................................9 FM24V10/FM25VN10 Errata Summary ....................19 Device ID ...........................................................................9 Document History Page .................................................21 Unique Serial Number (FM24VN10 only) ......................10 Sales, Solutions, and Legal Information ......................23 Function to Calculate CRC ........................................11 Worldwide Sales and Design Support .......................23 Maximum Ratings ...........................................................12 Products ....................................................................23 Operating Range .............................................................12 PSoC® Solutions ......................................................23 DC Electrical Characteristics ........................................12 Cypress Developer Community .................................23 Data Retention and Endurance .....................................13 Technical Support .....................................................23 Document Number: 001-84463 Rev. *J Page 2 of 23

FM24V10 Pinout Figure 1. 8-pin SOIC pinout NC 1 8 VDD A1 2 Top View 7 WP not to scale A2 3 6 SCL VSS 4 5 SDA Pin Definitions Pin Name I/O Type Description A2–A1 Input Device Select Address 2–1. These pins are used to select one of up to 4 devices of the same type on the same I2C bus. To select the device, the address value on the three pins must match the corre- sponding bits contained in the slave address. The address pins are pulled down internally. SDA Input/Output Serial Data/Address. This is a bi-directional pin for the I2C interface. It is open-drain and is intended to be wire-AND'd with other devices on the I2C bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. SCL Input Serial Clock. The serial clock pin for the I2C interface. Data is clocked out of the device on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. WP Input Write Protect. When tied to V , addresses in the entire memory map will be write-protected. When DD WP is connected to ground, all addresses are write enabled. This pin is pulled down internally. V Power supply Ground for the device. Must be connected to the ground of the system. SS V Power supply Power supply input to the device. DD NC No connect No connect. This pin is not connected to the die. Document Number: 001-84463 Rev. *J Page 3 of 23

FM24V10 Functional Overview ready condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write The FM24V10 is a serial F-RAM memory. The memory array is operation is complete. This is explained in more detail in the logically organized as 131,072 × 8 bits and is accessed using an interface section. industry-standard I2C interface. The functional operation of the F-RAM is similar to serial (I2C) EEPROM. The major difference I2C Interface between the FM24V10 and a serial (I2C) EEPROM with the same pinout is the F-RAM’s superior write performance, high The FM24V10 employs a bi-directional I2C bus protocol using endurance, and low power consumption. few pins or board space. Figure2 illustrates a typical system configuration using the FM24V10 in a microcontroller-based Memory Architecture system. The industry standard I2C bus is familiar to many users but is described in this section. When accessing the FM24V10, the user addresses 128K By convention, any device that is sending data onto the bus is locations of eight data bits each. These eight data bits are shifted the transmitter while the target device for this data is the receiver. in or out serially. The addresses are accessed using the I2C The device that is controlling the bus is the master. The master protocol, which includes a slave address (to distinguish other is responsible for generating the clock signal for all operations. non-memory devices), a page select bit, and a two-byte address. Any device on the bus that is being controlled is a slave. The The 17-bit address consists of a page select bit followed by FM24V10 is always a slave device. 16-bits. The complete address of 17-bits specifies each byte The bus protocol is controlled by transition states in the SDA and address uniquely. SCL signals. There are four conditions including START, STOP, data bit, or acknowledge. Figure 3 on page 5 and Figure 4 on The access time for the memory operation is essentially zero, page 5 illustrates the signal conditions that specify the four beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the I2C bus. Unlike a states. Detailed timing diagrams are shown in the electrical serial (I2C) EEPROM, it is not necessary to poll the device for a specifications section. Figure 2. System Configuration using Serial (I2C) nvSRAM Vcc R = (V - V max) / I Pmin DD OL OL R = t / (0.8473 * C ) Pmax r b SDA Microcontroller SCL Vcc Vcc A1 SCL A1 SCL A1 SCL A2 SDA A2 SDA A2 SDA WP WP WP #0 #1 #3 STOP Condition (P) START Condition (S) A STOP condition is indicated when the bus master drives SDA A START condition is indicated when the bus master drives SDA from LOW to HIGH while the SCL signal is HIGH. All operations from HIGH to LOW while the SCL signal is HIGH. All commands using the FM24V10 should end with a STOP condition. If an should be preceded by a START condition. An operation in operation is in progress when a STOP is asserted, the operation progress can be aborted by asserting a START condition at any will be aborted. The master must have control of SDA in order to time. Aborting an operation using the START condition will ready assert a STOP condition. the FM24V10 for a new operation. If during operation the power supply drops below the specified V minimum, the system should issue a START condition prior DD to performing another operation. Document Number: 001-84463 Rev. *J Page 4 of 23

FM24V10 Figure 3. START and STOP Conditions full pagewidth SDA SDA SCL SCL S P START Condition STOP Condition Figure 4. Data Transfer on the I2C Bus handbook, full pagewidth P SDA MSB Acknowledgement Acknowledgement S signal from slave signal from receiver SCL S S 1 2 7 8 9 1 2 3 4 - 8 9 or P ACK ACK START STOP or condition Byte complete START condition Data/Address Transfer The receiver would fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the no-acknowledge All data transfers (including addresses) take place while the SCL ceases the current operation so that the device can be signal is HIGH. Except under the three conditions described addressed again. This allows the last byte to be recovered in the above, the SDA signal should not change while SCL is HIGH. event of a communication error. Acknowledge/No-acknowledge Second and most common, the receiver does not acknowledge The acknowledge takes place after the 8th data bit has been to deliberately end an operation. For example, during a read transferred in any transaction. During this state the transmitter operation, the FM24V10 will continue to place data onto the bus should release the SDA bus to allow the receiver to drive it. The as long as the receiver sends acknowledges (and clocks). When receiver drives the SDA signal LOW to acknowledge receipt of a read operation is complete and no more data is needed, the the byte. If the receiver does not drive SDA LOW, the condition receiver must not acknowledge the last byte. If the receiver is a no-acknowledge and the operation is aborted. acknowledges the last byte, this will cause the FM24V10 to attempt to drive the bus on the next clock while the master is sending a new command such as STOP. Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth DATA OUTPUT BY MASTER No Acknowledge DATA OUTPUT BY SLAVE Acknowledge SCL FROM 1 2 8 9 MASTER S Clock pulse for START acknowledgement Condition Document Number: 001-84463 Rev. *J Page 5 of 23

FM24V10 Slave Device Address The first byte that the FM24V10 expects after a START condition Figure 6. Memory Slave Device Address is the slave address. As shown in Figure6, the slave address MSB LSB contains the device type or slave ID, the device select address handbook, halfpage bits, a page select bit, and a bit that specifies if the transaction is 1 0 1 0 A2 A1 A16 R/W a read or a write. Bits 7–4 are the device type (slave ID) and should be set to Slave ID Device Page 1010b for the FM24V10. These bits allow other function types to Select select reside on the I2C bus within an identical address range. Bits 3–2 High Speed Mode (Hs-mode) are the device select address bits. They must match the corre- sponding value on the external address pins to select the device. The FM24V10 supports a 3.4-MHz high speed mode. A master Up to four FM24V10 devices can reside on the same I2C bus by code (00001XXXb) must be issued to place the device into high assigning a different address to each. Bit 1 is the page select bit speed mode. Communication between master and slave will and is effectively the address MSB, A16. It specifies the then be enabled for speeds up to 3.4-MHz. A STOP condition will 64K-byte block of memory that is targeted for the current exit Hs-mode. Single- and multiple-byte reads and writes are operation. Bit 0 is the read/write bit (R/W). R/W = ‘1’ indicates a supported. read operation and R/W = ‘0’ indicates a write operation. Figure 7. Data transfer format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode S MASTER CODE 1 S SLAVE ADD. R/W 0 DATA A /1 P n (bytes+ ack.) Hs-mode continues Acknowledge or No Acknowledge No Acknowledge S SLAVE ADD. Addressing Overview bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. After the FM24V10 (as receiver) acknowledges the slave address, the master can place the memory address on the bus Memory Operation for a write operation. The address requires a 1-bit page select and two bytes. Since the device uses 17-bit address, the page The FM24V10 is designed to operate in a manner very similar to select bit is the MSB of the address followed by the remaining other I2C interface memory products. The major differences 16-bit address. The complete 17-bit address is latched internally. result from the higher performance write capability of F-RAM Each access causes the latched address value to be incre- technology. These improvements result in some differences mented automatically. The current address is the value that is between the FM24V10 and a similar configuration EEPROM held in the latch; either a newly written value or the address during writes. The complete operation for both writes and reads following the last access. The current address will be held for as is explained below. long as power remains or until a new value is written. Reads always use the current address. A random read address can be Write Operation loaded by beginning a write operation as explained below. All writes begin with a slave address, then a memory address. After transmission of each data byte, just prior to the The bus master indicates a write operation by setting the LSB of acknowledge, the FM24V10 increments the internal address the slave address (R/W bit) to a ‘0’. After addressing, the bus latch. This allows the next sequential byte to be accessed with master sends each byte of data to the memory and the memory no additional addressing. After the last address (1FFFFh) is generates an acknowledge condition. Any number of sequential reached, the address latch will roll over to 00000h. There is no bytes may be written. If the end of the address range is reached limit to the number of bytes that can be accessed with a single internally, the address counter will wrap from 1FFFFh to 00000h. read or write operation. Unlike other nonvolatile memory technologies, there is no Data Transfer effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user After the address bytes have been transmitted, data transfer experiences no delay through the bus. The entire memory cycle between the bus master and the FM24V10 can begin. For a read occurs in less time than a single bus clock. Therefore, any operation the FM24V10 will place 8 data bits on the bus then wait operation including read or write can occur immediately following for an acknowledge from the master. If the acknowledge occurs, a write. Acknowledge polling, a technique used with EEPROMs the FM24V10 will transfer the next sequential byte. If the to determine if a write is complete is unnecessary and will always acknowledge is not sent, the FM24V10 will end the read return a ready condition. operation. For a write operation, the FM24V10 will accept 8 data Document Number: 001-84463 Rev. *J Page 6 of 23

FM24V10 Internally, an actual memory write occurs after the 8th data bit is all addresses. The FM24V10 will not acknowledge data bytes transferred. It will be complete before the acknowledge is sent. that are written to protected addresses. In addition, the address Therefore, if the user desires to abort a write without altering the counter will not increment if writes are attempted to these memory contents, this should be done using START or STOP addresses. Setting WP to a LOW state (V ) will disable the write SS condition prior to the 8th data bit. The FM24V10 uses no page protect. WP is pulled down internally. buffering. Figure8 and Figure9 below illustrate a single-byte and The memory array can be write-protected using the WP pin. multiple-byte write cycles in F/S mode. Figure10 below illustrate Setting the WP pin to a HIGH condition (V ) will write-protect a single-byte write cycles in Hs mode. DD Figure 8. Single-Byte Write Start Address & Data Stop By Master P S Slave Address 0 A Address MSB A Address LSB A Data Byte A P S By F-RAM Acknowledge Figure 9. Multi-Byte Write Start Stop Address & Data By Master P S Slave Address 0 A Address MSB A Address LSB A Data Byte A Data Byte A P S By F-RAM Acknowledge Figure 10. Hs-mode Byte Write Start Start & Stop & HS-mode command Enter HS-mode Address & Data Exit HS-mode By Master S 0 0 0 0 1 X X X 1 S Slave AddressP 0 A Address MSB A Address LSB A Data Byte A P S By F-RAM No Acknowledge Acknowledge Read Operation To perform a current address read, the bus master supplies a slave address with the LSB set to a ‘1’. This indicates that a read There are two basic types of read operations. They are current operation is requested. After receiving the complete slave address read and selective address read. In a current address address, the FM24V10 will begin shifting out data from the read, the FM24V10 uses the internal address latch to supply the current address on the next clock. The current address is the address. In a selective read, the user performs a procedure to value held in the internal address latch. set the address to a specific value. Beginning with the current address, the bus master can read any Current Address & Sequential Read number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the As mentioned above the FM24V10 uses an internal latch to internal address counter will be incremented. supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place Note Each time the bus master acknowledges a byte, this for the read operation. The system reads from the address indicates that the FM24V10 should read out the next sequential immediately following that of the last operation. byte. Document Number: 001-84463 Rev. *J Page 7 of 23

FM24V10 There are four ways to properly terminate a read operation. 2.The bus master issues a no-acknowledge in the 9th clock Failing to properly terminate the read will most likely create a bus cycle and a START in the 10th. contention as the FM24V10 attempts to read out additional data 3.The bus master issues a STOP in the 9th clock cycle. onto the bus. The four valid methods are: 4.The bus master issues a START in the 9th clock cycle. 1.The bus master issues a no-acknowledge in the 9th clock cycle and a STOP in the 10th clock cycle. This is illustrated in If the internal address reaches 1FFFFh, it will wrap around to the diagrams below. This is preferred. 00000h on the next read cycle. Figure11 and Figure12 below show the proper operation for current address reads. Figure 11. Current Address Read No By Master Start Address Acknowledge Stop S Slave Address X 1 A Data Byte 1 P By F-RAM Acknowledge Data Figure 12. Sequential Read No Start Address Acknowledge Acknowledge By Master Stop S Slave Address X 1 A Data Byte A Data Byte 1 P By F-RAM Acknowledge Data Figure 13. Hs-mode Current Address Read Start Start & No By Master HS-mode command Enter HS-mode Address Acknowledge Stop & Exit HS-mode S 0 0 0 0 1 X X X 1 S Slave Address X 1 A Data Byte 1 P By F-RAM No Data Acknowledge Acknowledge Document Number: 001-84463 Rev. *J Page 8 of 23

FM24V10 Selective (Random) Read operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address There is a simple technique that allows a user to select a random latch. After the FM24V10 acknowledges the address, the bus address location as the starting point for a read operation. This master issues a START condition. This simultaneously aborts involves using the first three bytes of a write operation to set the the write operation and allows the read command to be issued internal address followed by subsequent read operations. with the slave address LSB set to a ‘1’. The operation is now a To perform a selective read, the bus master sends out the slave current address read. address with the LSB (R/W) set to 0. This specifies a write Figure 14. Selective (Random) Read Start No By Master Address Start Address Acknowledge Stop P S Slave Address 0 A Address MSB A Address LSB A S Slave Address X 1 A Data Byte 1 P S By F-RAM Data Acknowledge Sleep Mode 8.The FM24V10 sends an ACK. A low power mode called Sleep Mode is implemented on the 9.The master sends STOP to ensure the device enters sleep FM24V10 device. The device will enter this low power state when mode. the Sleep command 86h is clocked-in. Sleep Mode entry can be Note Errata: Step 9 - Sending STOP is an optional step for entered as follows: FM24V10. The FM24V10 starts entering the Sleep mode from 1.The master sends a START command. step 8 and releases the SDA line when in the Sleep mode. The LOW to HIGH transition on the SDA line when I2C clock is HIGH 2.The master sends Reserved Slave ID F8h. generates an unintended STOP. For more information, see 3.The FM24V10 sends an ACK. Errata on page 19. 4.The master sends the I2C-bus slave address of the slave Once in sleep mode, the device draws I current, but the device device it needs to identify. The last bit is a ‘Don’t care’ value continues to monitor the I2C pins. OnZcZe the master sends a (page select and R/W bits). Only one device must Slave Address that the FM24V10 identifies, it will “wakeup” and acknowledge this byte (the one that has the I2C-bus slave be ready for normal operation within t time. As an alternative address). REC method of determining when the device is ready, the master can 5.The FM24V10 sends an ACK. send read or write commands and look for an ACK. While the 6.The master sends a Re-START command. device is waking up, it will NACK the master until it is ready. 7.The master sends Reserved Slave ID 86h. Figure 15. Sleep Mode Entry Start Address Start Address Stop By Master S Rsvd Slave ID (F8) A Slave Address X X A S Rsvd Slave ID (86) A P By F-RAM Acknowledge Device ID 5.The FM24V10 sends an ACK. 6.The master sends a Re-START command. The FM24V10 device incorporates a means of identifying the 7.The master sends Reserved Slave ID F9h. device by providing three bytes of data, which are manufacturer ID, product ID, and die revision. The Device ID is read-only. It 8.The FM24V10 sends an ACK. can be accessed as follows: 9.The Device ID Read can be done, starting with the 12 1.The master sends a START command. manufacturer bits, followed by the 9 device identification bits, and then the 3 die revision bits. 2.The master sends Reserved Slave ID F8h. 10.The master ends the Device ID read sequence by NACKing 3.The FM24V10 sends an ACK. the last byte, thus resetting the slave device state machine 4.The master sends the I2C-bus slave address of the slave and allowing the master to send the STOP command. device it needs to identify. The last bit is a ‘Don’t care’ value Note The reading of the Device ID can be stopped anytime by (page select and R/W bits). Only one device must acknowledge this byte (the one that has the I2C-bus slave sending a NACK command. address). Document Number: 001-84463 Rev. *J Page 9 of 23

FM24V10 Table 1. Device ID Device ID Description 23–12 11–8 7–3 2–0 Device Device ID (12 bits) (4 bits) (5 bits) (3 bits) (3 bytes) Product ID Manufacturer ID Density Variation Die Rev FM24V10 004400h 000000000100 0100 N0000 000 FM24VN10 004480h 000000000100 0100 10000 000 Note Product ID bit 4 = S/N, Product ID bit 0 = reserved. Figure 16. Read Device ID Start No By Master Address Start Address Acknowledge Acknowledge Stop S Rsvd Slave ID (F8) A Slave Address X X A S Rsvd Slave ID (F9) A Data Byte A Data Byte A Data Byte 1 P By F-RAM Acknowledge Data Unique Serial Number (FM24VN10 only) 6.The master sends a Re-START command 7.The master sends Reserved Slave ID CDh to read the serial The FM24VN10 device also incorporates a read-only 8-byte number. serial number. It can be used to uniquely identify a pc board or 8.The FM24VN10 sends an ACK. system. The serial number includes a 40-bit unique number, an 8-bit CRC, and a 16-bit number that can be defined upon request 9.The master ends the serial number read sequence by by the customer. If a customer-specific number is not requested, NACKing the last byte, thus resetting the slave device state the 16-bit Customer Identifier is 0000h. The 8 bytes of data are machine and allowing the master to send the STOP accessed via a slave address sequence similar to the Device ID. command. The serial number can be read by the system as follows: The 8-bit CRC value can be used to compare to the value calcu- 1.The master sends a START command lated by the controller. If the two values match, then the commu- nication between slave and master was performed without 2.The master sends Reserved Slave ID F8h errors. The function (shown in Function to Calculate CRC on 3.The FM24VN10 sends an ACK. page 11) is used to calculate the CRC value. To perform the 4.The master sends the I2C-bus slave address of the slave calculation, 7 bytes of data are filled into a memory buffer in the device it needs to identify. The last two bits are ‘Don’t care’ same order as they are read from the part - i.e. byte7, byte6, values. Only one device must acknowledge this byte (the one byte5, byte4, byte3, byte2, byte1 of the serial number. The calcu- that has the I2C-bus slave address). lation is performed on the 7 bytes, and the result should match the final byte out from the part which is byte0, the 8-bit CRC 5.The FM24VN10 sends an ACK. value. Table 2. 8-Byte Serial Number (read-only) Customer IDENTIFIER 40-bit UNIQUE NUMBER 8-bit CRC SN(63–56) SN(55–48) SN(47–40) SN(39–32) SN(31–24) SN(23–16) SN(15–8) SN(7–0) Note Contact factory for requesting a customer identifier number. Figure 17. 8-byte Serial Number (read-only) Start No By Master Address Start Address Acknowledge Acknowledge Stop S Rsvd Slave ID (F8) A Slave Address X X A S Rsvd Slave ID (CD) A Data Byte 7 A A Data Byte 0 1 P By F-RAM Acknowledge Data Document Number: 001-84463 Rev. *J Page 10 of 23

FM24V10 Function to Calculate CRC BYTE calcCRC8( BYTE* pData, int nBytes ) { static BYTE crctable[256] = { 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15, 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D, 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65, 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D, 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5, 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA,0xCD, 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85, 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD, 0xC7, 0xC0, 0xC9, 0xCE,0xDB,0xDC,0xD5, 0xD2, 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED,0xEA, 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC,0xA5, 0xA2, 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A, 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32, 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A, 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42, 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A, 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C, 0xB1, 0xB6, 0xBF, 0xB8, 0xAD,0xAA, 0xA3, 0xA4, 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC, 0xC1, 0xC6, 0xCF, 0xC8, 0xDD,0xDA,0xD3, 0xD4, 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C, 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44, 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C, 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34, 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B, 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63, 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B, 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13, 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC,0xBB, 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83, 0xDE,0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC,0xCB, 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3 }; BYTE crc = 0; ....................while( nBytes-- ) crc = crctable[crc ^ *pData++]; return crc; } Document Number: 001-84463 Rev. *J Page 11 of 23

FM24V10 Maximum Ratings Package power dissipation capability (T = 25 °C) .................................................................1.0 W A Exceeding maximum ratings may shorten the useful life of the Surface mount lead soldering temperature device. These user guidelines are not tested. (10 seconds) ............................................................+260 °C Storage temperature ................................–65 °C to +125 °C Electrostatic Discharge Voltage Maximum accumulated storage time Human Body Model (AEC-Q100-002 Rev. E) .................. 2.5 kV At 125 °C ambient temperature .................................1000 h Charged Device Model (AEC-Q100-011 Rev. B) .............1.25 kV At 85 °C ambient temperature ................................10 Years Machine Model (AEC-Q100-003 Rev. E) ............................200 V Ambient temperature Latch-up current ....................................................> 140 mA with power applied ...................................–55 °C to +125 °C * Exception: The “V < V + 1.0 V” restriction does not apply IN DD Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V to the SCL and SDA inputs. Input voltage ..........–1.0 V to + 4.5 V and V < V + 1.0 V IN DD Operating Range DC voltage applied to outputs in High-Z state ....................................–0.5 V to VDD + 0.5 V Range Ambient Temperature (TA) VDD Transient voltage (< 20 ns) Industrial –40 C to +85 C 2.0 V to 3.6 V on any pin to ground potential ............–2.0 V to V + 2.0 V DD DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [1] Max Unit V Power supply 2.0 3.3 3.6 V DD I Average V current SCL toggling f = 100 kHz – – 175 A DD DD SCL between f = 1 MHz – – 400 A V – 0.2 V and V , SCL DD SS other inputs V or f = 3.4 MHz – – 1000 A SS SCL V – 0.2 V. DD I Standby current SCL = SDA = V . All other inputs V – 90 150 A SB DD SS or V .Stop command issued. DD I Sleep mode current SCL = SDA = V . All other inputs V – 5 8 A ZZ DD SS or V .Stop command issued. DD I Input leakage current V < V < V –1 – +1 A LI SS IN DD (Except WP and A2–A1) Input leakage current V < V < V –1 – +100 A SS IN DD (for WP and A2–A1) I Output leakage current V < V < V –1 – +1 A LO SS IN DD V Input HIGH voltage 0.7 × V – V + 0.3 V IH DD DD V Input LOW voltage –0.3 – 0.3 × V V IL DD V Output LOW voltage I = 2 mA, V > 2.7 V – – 0.4 V OL1 OL DD V Output LOW voltage I = 150 A – – 0.2 V OL2 OL R [2] Input resistance (WP, A2–A1) For V = V 50 – – k in IN IL (Max) For V = V 1 – – M IN IH (Min) Notes 1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested. 2. The input pull-down circuit is strong (50 k) when the input voltage is below VIL and weak (1 M) when the input voltage is above VIH. Document Number: 001-84463 Rev. *J Page 12 of 23

FM24V10 Data Retention and Endurance Parameter Description Test condition Min Max Unit T Data retention T = 85 C 10 – Years DR A T = 75 C 38 – A T = 65 C 151 – A NV Endurance Over operating temperature 1014 – Cycles C Capacitance Parameter [3] Description Test Conditions Max Unit C Output pin capacitance (SDA) T = 25 C, f = 1 MHz, V = V (typ) 8 pF O A DD DD C Input pin capacitance 6 pF I Thermal Resistance Parameter [3] Description Test Conditions 8-pin SOIC Unit  Thermal resistance Test conditions follow standard test methods and 138 C/W JA (junction to ambient) procedures for measuring thermal impedance, per  Thermal resistance EIA/JESD51. 40 C/W JC (junction to case) AC Test Loads and Waveforms Figure 18. AC Test Loads and Waveforms 3.6 V 1.8 k OUTPUT 100 pF AC Test Conditions Input pulse levels .................................10% and 90% of V DD Input rise and fall times .................................................10 ns Input and output timing reference levels ................0.5 × V DD Output load capacitance ............................................100 pF Note 3. These parameters are guaranteed by design and are not tested. Document Number: 001-84463 Rev. *J Page 13 of 23

FM24V10 AC Switching Characteristics Over the Operating Range Parameter [4] F/S-mode [5] Hs-mode[5] Cypress Alt. Description Unit Min Max Min Max Parameter Parameter f [6] SCL clock frequency – 1.0 – 3.4 MHz SCL t Start condition setup for repeated Start 260 – 160 – ns SU; STA t Start condition hold time 260 – 160 – ns HD;STA t Clock LOW period 500 – 160 – ns LOW t Clock HIGH period 260 – 60 – ns HIGH t [7] t Data in setup 50 – 10 – ns SU;DAT SU;DATA t t Data in hold 0 – 0 – ns HD;DAT HD;DATA t Data output hold (from SCL @ V ) 0 – 0 – ns DH IL t [8] t Input rise time – 120 – 80 ns R r t [8] t Input fall time – 120 – 80 ns F f t STOP condition setup 260 – 160 – ns SU;STO t t SCL LOW to SDA Data Out Valid – 450 – 130 ns AA VD;DATA t Bus free before new transmission 500 – 300 – ns BUF t Noise suppression time constant on SCL, SDA – 50 – 5 ns SP Figure 19. Read Bus Timing Diagram t tR ` tF HIGH tLOW tSP tSP SCL tSU:SDA tBUF 1/fSCL tHD:DAT t SU:DAT SDA tAA tDH Start Stop Start Acknowledge Figure 20. Write Bus Timing Diagram t HD:DAT SCL tHD:STA tSU:DAT tAA tSU:STO SDA Start Stop Start Acknowledge Notes 4. Test conditions assume signal transition time of 10 ns or less, timing reference levels of VDD/2, input pulse levels of 0 to VDD(typ), and output loading of the specified IOL and load capacitance shown in Figure 18 on page 13. 5. Bus Load (Cb) considerations; Cb < 500 pF for I2C clock frequency (SCL) 1 MHz; Cb < 100 pF for SCL at 3.4 MHz. 6. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max). 7. In Hs-mode and VDD < 2.7 V, the tSU:DAT (min.) spec is 15 ns. 8. These parameters are guaranteed by design and are not tested. Document Number: 001-84463 Rev. *J Page 14 of 23

FM24V10 Power Cycle Timing Over the Operating Range Parameter Description Min Max Unit tPU Power-up VDD(min) to first access (START condition) 250 – µs tPD Last access (STOP condition) to power-down (VDD(min)) 0 – µs tVR [9, 10] VDD power-up ramp rate 50 – µs/V tVF [9, 10] VDD power-down ramp rate 100 – µs/V t [10] Recovery time from sleep mode – 400 µs REC Figure 21. Power Cycle Timing ~~ VDD(min) VDD(min) VDD tVR tVF tPU tPD SDA ~~ 2 2 I C START I C STOP Notes 9. Slope measured at any point on the VDD waveform. 10.Guaranteed by design. Document Number: 001-84463 Rev. *J Page 15 of 23

FM24V10 Ordering Information Package Operating Ordering Code Package Type Diagram Range FM24V10-G 51-85066 8-pin SOIC Industrial FM24V10-GTR FM24VN10-G 8-pin SOIC, Serial Number FM24VN10-GTR All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions FM 24 V N 10 - G X Option: X = Blank or TR Blank = Standard; TR = Tape and Reel Package Type: G = 8-pin SOIC Density: 10 = 1-Mbit N = Serial Number Voltage: V = 2.0 V to 3.6 V I2C F-RAM Cypress Document Number: 001-84463 Rev. *J Page 16 of 23

FM24V10 Package Diagram Figure 22. 8-pin SOIC (150 Mils) Package Outline, 51-85066 51-85066 *I Document Number: 001-84463 Rev. *J Page 17 of 23

FM24V10 Acronyms Document Conventions Units of Measure Acronym Description ACK Acknowledge Symbol Unit of Measure CMOS Complementary Metal Oxide Semiconductor °C degree Celsius EIA Electronic Industries Alliance Hz hertz I2C Inter-Integrated Circuit Kb 1024 bit I/O Input/Output kHz kilohertz k kilohm JEDEC Joint Electron Devices Engineering Council MHz megahertz LSB Least Significant Bit M megaohm MSB Most Significant Bit A microampere NACK No Acknowledge s microsecond RoHS Restriction of Hazardous Substances mA milliampere R/W Read/Write ms millisecond SCL Serial Clock Line ns nanosecond SDA Serial Data Access  ohm SOIC Small Outline Integrated Circuit % percent WP Write Protect pF picofarad V volt W watt Document Number: 001-84463 Rev. *J Page 18 of 23

FM24V10 Errata This document describes the errata for the serial I2C F-RAM FM24V10/FM24VN10 (1-Mbit) product. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s datasheet for a complete functional description. Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to cypressfram@cypress.com. Part Numbers Affected Part Number Device Characteristics FM24V10 1-Mbit (128K × 8) Serial (I2C) F-RAM with Device ID, 2.0 V to 3.6 V, Industrial temperature FM24VN10 1-Mbit (128K × 8) Serial (I2C) F-RAM with Device ID and Unique Serial Number, 2.0 V to 3.6 V, Industrial temperature FM24V10/FM24VN10 I2C F-RAM Qualification Status Production parts. FM24V10/FM25VN10 Errata Summary The following table defines the errata applicability to available FM24V10/FM24VN10 devices. Items Part Number Silicon Revision Fix Status 1.The I2C F-RAM enters Sleep mode without the FM24V10-G Rev A None. STOP condition FM24V10-GTR FM24VN10-G FM24VN10-GTR 1.The I2C F-RAM enters Sleep mode without the STOP condition ■Problem Definition When the I2C master sends the last Reserved Slave ID (86h) of the Sleep command sequence, as shown in Figure 23, the I2C F-RAM returns an acknowledgement (ACK) and releases the SDA line after the rising edge of the 9th clock. If this LOW to HIGH transition on the SDA line happens when the I2C clock is HIGH, it artificially generates an unintended STOP. Figure 23. I2C F-RAM Sleep Cycle Document Number: 001-84463 Rev. *J Page 19 of 23

FM24V10 ■Parameters Affected None of the existing parameters are affected. ■Trigger Condition(S) The I2C master sends the last Reserved Slave ID (86h) of the Sleep command and receives an ACK from the I2C F-RAM. The I2C F-RAM starts entering the Sleep mode from the 9th rising edge of the I2C clock and releases the SDA line when in the Sleep mode. The LOW to HIGH transition on the SDA line when I2C clock is HIGH generates an unintended STOP. ■Scope of Impact The ongoing I2C communication can be disrupted due to unintended STOP generated by the I2C F-RAM slave. ■Workaround This issue can be mitigated by implementing one of the following two methods: ❐The I2C master ignores any unintended STOP generated by the I2C F-RAM slave. ❐The I2C master latches the ACK on the 9th rising edge of the I2C clock and starts driving the SDA line LOW. This will ensure when the I2C F-RAM enters Sleep and releases the SDA line; it still remains LOW driven by the I2C master. This will prevent unintended LOW to HIGH transition when SCL is LOW. ■Fix Status This issue is applicable to all the existing I2C F-RAM parts shown in this errata. The existing parts are in production status and will continue serving with errata. There is no plan to fix this issue in the existing silicon. Document Number: 001-84463 Rev. *J Page 20 of 23

FM24V10 Document History Page Document Title: FM24V10, 1-Mbit (128K × 8) Serial (I2C) F-RAM Document Number: 001-84463 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 3902204 GVCH 02/25/2013 New spec *A 3996669 GVCH 05/13/2013 Added Appendix A - Errata for FM24V10 and FM24VN10 *B 4045469 GVCH 06/30/2013 All errata items are fixed and the errata is removed. *C 4283424 GVCH 02/18/2014 Updated Maximum Ratings: Added “Maximum junction temperature” and its corresponding details. Added “DC voltage applied to outputs in High-Z state” and its corresponding details. Added “Transient voltage (< 20 ns) on any pin to ground potential” and its corresponding details. Added “Package power dissipation capability (T = 25 °C)” and its A corresponding details. Removed “Package Moisture Sensitivity Level (MSL)” and its corresponding details. Added “Latch-up current” and its corresponding details. Updated DC Electrical Characteristics: Removed existing details of I parameter and splitted I parameter into two LI LI rows namely “Input leakage current (Except WP and A2–A1)” and “Input leakage current (for WP and A2–A1)” and added corresponding values. Updated Data Retention and Endurance: Removed existing details of T parameter. DR Added details of T parameter corresponding to “T = 85 °C”, “T = 75 °C” DR A A and “T = 65 °C”. A Added NV parameter and its corresponding details. C Added Thermal Resistance. Updated Package Diagram: Removed Package Marking Scheme (top mark). Removed “Ramtron Revision History”. Updated to Cypress template. Completing Sunset Review. *D 4564960 GVCH 11/10/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *E 4700243 GVCH 03/26/2015 Updated Package Diagram: spec 51-85066 – Changed revision from *F to *G. Added Errata. *F 4781095 GVCH 05/29/2015 Updated Ordering Information: No change in part numbers. Fixed Typo (Replaced “001-85066” with “51-85066” in “Package Diagram” column). Updated to new template. *G 4874648 ZSK / PSR 08/06/2015 Updated Maximum Ratings: Removed “Maximum junction temperature” and its corresponding details. Added “Maximum accumulated storage time” and its corresponding details. Added “Ambient temperature with power applied” and its corresponding details. Document Number: 001-84463 Rev. *J Page 21 of 23

FM24V10 Document History Page (continued) Document Title: FM24V10, 1-Mbit (128K × 8) Serial (I2C) F-RAM Document Number: 001-84463 Orig. of Submission Rev. ECN No. Description of Change Change Date *H 5366088 GVCH 07/22/2016 Updated Pin Definitions: Added details corresponding to “NC” pin. Updated Package Diagram: spec 51-85066 – Changed revision from *G to *H. Updated to new template. *I 5738855 GNKK 05/16/2017 Updated Cypress logo and copyright. *J 6422002 GVCH 12/26/2018 Updated Maximum Ratings: Replaced “–55 °C to +125 °C” with “–65 °C to +125 °C” in ratings corresponding to “Storage temperature”. Updated Package Diagram: spec 51-85066 – Changed revision from *H to *I. Updated to new template. Completing Sunset Review. Document Number: 001-84463 Rev. *J Page 22 of 23

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Document Number: 001-84463 Rev. *J Revised December 26, 2018 Page 23 of 23