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F D P 7 N December 2013 6 0 N FDP7N60NZ / FDPF7N60NZ Z / N-Channel UniFETTM II MOSFET F D 600 V, 6.5 A, 1.25 Ω P F 7 Features Description N 6 0 • RDS(on) = 1.05 Ω (Typ.) @ VGS = 10 V, ID = 3.25 A UniFETTM II MOSFET is Fairchild Semiconductor’s high voltage N • Low Gate Charge (Typ. 13 nC) MOSFET family based on advanced planar stripe and DMOS Z technology. This advanced MOSFET family has the smallest — • Low C (Typ. 7 pF) rss on-state resistance among the planar MOSFET, and also pro- N • 100% Avalanche Tested vides superior switching performance and higher avalanche - • Improved dv/dt Capability energy strength. In addition, internal gate-source ESD diode C h allows UniFET II MOSFET to withstand over 2kV HBM surge • ESD Improved Capability a stress. This device family is suitable for switching power con- n • RoHS Compliant verter applications such as power factor correction (PFC), flat n e panel display (FPD) TV power, ATX and electronic lamp bal- l Applications lasts. U n • LCD/ LED/ PDP TV i F • Lighting E T • Uninterruptible Power Supply T M • AC-DC Power Supply I I D M O S F E T G G D G S TO-220 DS TO-220F S MOSFET Maximum Ratings TC = 25oC unless otherwise noted. FDPF7N60NZ / Symbol Parameter FDP7N60NZ Unit FDPF7N60NZT V Drain to Source Voltage 600 V DSS V Gate to Source Voltage ±30 V GSS - Continuous (T = 25oC) 6.5 6.5* I Drain Current C A D - Continuous (T = 100oC) 3.9 3.9* C I Drain Current - Pulsed (Note 1) 26 26* A DM E Single Pulsed Avalanche Energy (Note 2) 275 mJ AS I Avalanche Current (Note 1) 6.5 A AR E Repetitive Avalanche Energy (Note 1) 14.7 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) 10 V/ns (T = 25oC) 147 33 W P Power Dissipation C D - Derate Above 25oC 1.2 0.26 W/oC T , T Operating and Storage Temperature Range -55 to +150 oC J STG T Maximum Lead Temperature for Soldering, 1/8” from Case for 5 Seconds 300 oC L *Drain current limited by maximum junction temperature. Thermal Characteristics FDPF7N60NZ / Symbol Parameter FDP7N60NZ Unit FDPF7N60NZT RθJC Thermal Resistance, Junction to Case, Max. 0.85 3.8 oC/W RθJA Thermal Resistance, Junction to Ambient, Max. 62.5 62.5 ©2010 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D Package Marking and Ordering Information P 7 N Part Number Top Mark Package Packing Method Reel Size Tape Width Quantity 6 FDP7N60NZ FDP7N60NZ TO-220 Tube N/A N/A 50 units 0 N FDPF7N60NZ FDPF7N60NZ TO-220F Tube N/A N/A 50 units Z FDPF7N60NZT FDPF7N60NZ TO-220F Tube N/A N/A 50 units / F D Electrical Characteristics TC = 25oC unless otherwise noted. P F Symbol Parameter Test Conditions Min. Typ. Max. Unit 7 N Off Characteristics 6 0 BV Drain to Source Breakdown Voltage I = 250 μA, V = 0 V, T = 25oC 600 - - V N DSS D GS J Z ΔBVDSS Breakdown Voltage Temperature I = 250 μA, Referenced to 25oC - 0.6 - V/oC — / ΔT Coefficient D J V = 600 V, V = 0 V - - 1 N IDSS Zero Gate Voltage Drain Current VDS = 480 V, TGS= 125oC - - 10 μA -C DS C I Gate to Body Leakage Current V = ±25 V, V = 0 V - - ±10 μA h GSS GS DS a n On Characteristics n e VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250 μA 3 - 5 V l U RDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 3.25 A - 1.05 1.25 Ω n i g Forward Transconductance V = 20 V, I = 3.25 A - 7.3 - S F FS DS D E T Dynamic Characteristics T M CCiss IOnuptuptu Ct aCpaapcaitcaitnacnece VDS = 25 V, VGS = 0 V, -- 57500 79300 ppFF II oss f = 1 MHz M Crss Reverse Transfer Capacitance - 7 10 pF O Qg(tot) Total Gate Charge at 10V VDS = 480 V, ID = 6.5 A, - 13 17 nC SF Qgs Gate to Source Gate Charge VGS = 10 V - 3 - nC E Q Gate to Drain “Miller” Charge (Note 4) - 5.6 - nC T gd Switching Characteristics t Turn-On Delay Time - 17.5 45 ns d(on) tr Turn-On Rise Time VDD = 300 V, ID = 6.5 A, - 30 70 ns V = 10 V, R = 25 Ω t Turn-Off Delay Time GS G - 40 90 ns d(off) tf Turn-Off Fall Time (Note 4) - 25 60 ns Drain-Source Diode Characteristics I Maximum Continuous Drain to Source Diode Forward Current - - 6.5 A S I Maximum Pulsed Drain to Source Diode Forward Current - - 26 A SM V Drain to Source Diode Forward Voltage V = 0 V, I = 6.5 A - - 1.4 V SD GS SD trr Reverse Recovery Time VGS = 0 V, ISD = 6.5 A, - 250 - ns Qrr Reverse Recovery Charge dIF/dt = 100 A/μs - 1.4 - μC Notes: 1: Repetitive rating: pulse-width limited by maximum junction temperature. 2: L = 13 mH, IAS = 6.5 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25°C. 3: ISD ≤ 6.5 A, di/dt ≤ 200 A/μs, VDD ≤ BVDSS, starting TJ = 25°C. 4: Essentially independent of operating temperature typical characteristics. ©2010 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D Typical Performance Characteristics P 7 N 6 0 Figure 1. On-Regio n Characteristics Figure 2. Transfer Characteristics N 20 100 Z VGS = 15.0 V / F 10 10.0 V D 8.0 V P 7.0 V F I, Drain Current[A]D 1 66..50 VV I, Drain Current[A]D 101 150oC -55o2C5oC 7N60NZ — N *Notes: * Notes : - 12.. 2T5C0 =μ s2 5PouClse Test 12.. V25D0Sμ =s 2P0uVlse Test Cha 0.1 0.1 n 0.1 1 10 20 4 5 6 7 8 n VDS, Drain-Source Voltage[V] VGS, Gate-Source Voltage[V] el U Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage n i Drain Current and Gate Voltage Variation vs. Source Current F E and Temperature T T 2.0 100 M I I M 1.8 []ΩR ,()DSonSource On-Resistance111...246 VGS = 10V VGS = 20V verse Drain Current [A]10 150oC 25oC OSFET Drain-1.0 I, ReS N1.o VteGsS: = 0V 0.8 * Note : TJ = 25oC 1 2. 250μs Pulse Test 0 2 4 6 8 10 12 14 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Body Diode Forward Voltage [V] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics 5000 10 VDS = 120V 1000 Ciss ge [V] 8 VVDDSS == 340800VV a ces [pF] 100 Coss urce Volt 6 n o a S pacit CCiossss = = C Cgdss + + C Cggdd (Cds = shorted) Crss Gate- 4 Ca 10 Crss = Cgd , S G V 2 * Note: 12.. Vf =G S1 M= H0Vz * Note : ID = 6.5A 1 0 0.1 1 10 30 0 2 4 6 8 10 12 14 VDS, Drain-Source Voltage [V] Qg, Total Gate Charge [nC] ©2010 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D Typical Performance Characteristics P (Continued) 7 N 6 0 Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation N vs. Temperature vs Temperature Z / 1.2 3.0 F D e g P zed] wn Volta 1.1 zed] sistance22..05 F7N6 BV, [NormaliDSSDrain-Source Breakdo 01..90 * N1o. VteGsS : = 0V R, [NormaliDS(on)Drain-Source On-Re011...505 * N12o.. VItDeG s=S : 3=. 2150AV 0NZ — N-Cha 0.8 2. ID = 250uA 0-100 -50 0 50 100 150 nn e -100 -5T0J, Juncti0on Temp5e0rature [o1C0]0 150 TJ, Junction Temperature [oC] l U n i Figure 9. Maximum Safe Operating Area Figure 10. Maximum Safe Operating Area F E - FDPF7N60NZ / FDPF7N60NZT - FDP7N60NZ T T 100 100 M I I 10μs 30μs M O urrent [A] 10 10m1sm1s00μs urrent [A] 10 10m1sm1s00μs SFET C C n 1 n 1 I, Drai D Oisp Leirmatitioedn biny TRh DisS (Aonre)a DC I, DraiD Oisp Leirmaittieodn biny TRh DisS (Aonre)a DC 0.1 * Notes : 0.1 * Notes : 1. TC = 25oC 1. TC = 25oC 2. TJ = 150oC 2. TJ = 150oC 3. Single Pulse 3. Single Pulse 0.01 0.01 1 10 100 1000 1 10 100 1000 VDS, Drain-Sou rce Voltage [V] VDS, Drain-Source Voltage [V] Figure 11. Maximum Drain Current vs. Case Temperature 8 6 A] nt [ e urr 4 C n ai Dr I, D 2 0 25 50 75 100 125 150 TC, Case Temperature [oC] ©2010 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D Typical Performance Characteristics P (Continued) 7 N 6 0 N Figure 12. Transient Thermal Response Curve Z - FDPF7N60NZ / FDPF7N60NZT / F D 5 P o Z(t), Thermal Response [C/W] ][θThermal Response ZJCθJCo Z(t), Thermal Response [C/W] θJC0.00.111 000000......100205521 Single pulse * N132o... ZTDtPeθJusDJMtMC y :-( tFT) aC=c =3tot .1P8rt,oD2 CDM/ =W*t 1Z /Mθt2JaCx(t.) F7N60NZ — N-Chann 10-5 10-4 10-3 10-2 10-1 100 101 102 103 e l tR1,e Rcetacntagnuglualra Pr Puulslsee D Duurraattiioonn [[sseecc]] U n i F E T T M I I M O S Figure 13. Transient Thermal Response Curve F E - FDP7N60NZ T W] 5 C/ o][ponse [e ZθJC 1 0.5 Thermal Resal Respons 0.1 00000...0..0012125 PDM t1t2 Z(t), ThermθJC 0.01 Single pulse * N132o... ZDTteθJusJMtC y :-( tFT) aC=c =0to .P8r,5D DoMC =*/t W1Z/θt 2JMCa(tx). 0.001 10-5 10-4 10-3 10-2 10-1 1 10 102 103 tR1, eRcetcatnagnugulalar rP Puulslsee DDuurraattiioonn [[sseecc] ] ©2010 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D P 7 N 6 0 N Z / F D P F 7 N 6 0 N Z — N - C IG = const. h a n n e l U Figure 14. Gate Charge Test Circuit & Waveform n i F E T T M I I VVDDSS RRLL VVDDSS 9900%% MO S VVGGSS VVDDDD F E RR GG T 1100%% VV V1100GVVS DDUUTT GGSS tt tt tt dd((oonn)) rr dd((ooffff)) tt ff tt tt oonn ooffff Figure 15. Resistive Switching Test Circuit & Waveforms V GS Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms ©2010 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

F D P 7 N 6 0 N Z / F DDUUTT ++ D P F 7 VV DDSS N 6 0 __ N Z — IISSDD N LLL - C h a n DDrriivveerr n RR e GG l SSaammee TTyyppee U aass DDUUTT VVDDDD n i F E VV GGSS ••ddvv//ddttccoonnttrroolllleedd bbyy RR T GG T ••II ccoonnttrroolllleedd bbyy ppuullssee ppeerriioodd M SSDD I I M O S F E T GGGaaattteee PPPuuulllssseee WWWiiidddttthhh VVGGSS DDD ===------GGG------aaa------ttt---eee------ PPP------uuu------lll---sss---eee------ ---PPP------eee------rrr---iiiooo------ddd--- 1100VV (( DDrriivveerr )) II ,, BBooddyy DDiiooddee FFoorrwwaarrdd CCuurrrreenntt FFMM II SSDD (( DDUUTT )) ddii//ddtt II RRMM BBooddyy DDiiooddee RReevveerrssee CCuurrrreenntt VV DDSS (( DDUUTT )) BBooddyy DDiiooddee RReeccoovveerryyddvv//ddtt VV VV SSDD DDDD BBooddyy DDiiooddee FFoorrwwaarrdd VVoollttaaggee DDrroopp Figure 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms ©2010 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com FDP7N60NZ / FDPF7N60NZ Rev. C2

SUPPLIER"B"PACKAGE SHAPE (cid:145)(cid:23)(cid:17)(cid:19)(cid:19) 3.50 10.67 SUPPLIER"A"PACKAGE 9.65 E SHAPE 3.40 2.50 16.30 IFPRESENT,SEENOTE"D" 13.90 E 16.51 9.40 15.42 8.13 E 1 2 3 2.46 4.10 C 2.70 14.04 2.13 12.70 2.06 FRONTVIEWS 4.70 1.62 1.62 4.00 1.42H 2.67 1.10 2.40 "A1" 8.65 1.00 SEENOTE"F" 7.59 0.55 (cid:24)(cid:131) (cid:24)(cid:131) OPTIONAL 6.69 (cid:22)(cid:131) (cid:22)(cid:131) 6.06 CHAMFER E 14.30 11.50 NOTE"I" BOTTOMVIEW NOTES: A)REFERENCEJEDEC,TO-220,VARIATIONAB B)ALLDIMENSIONSAREINMILLIMETERS. C)DIMENSIONSCOMMONTOALLPACKAGE SUPPLIERSEXCEPTWHERENOTED. 3 2 1 D)LOCATIONOFMOLDEDFEATUREMAYVARY (LOWERLEFTCORNER,LOWERCENTER ANDCENTEROFTHEPACKAGE) EDOESNOTCOMPLYJEDECSTANDARDVALUE. F)"A1"DIMENSIONSASBELOW: SINGLEGAUGE=0.51-0.61 DUALGAUGE=1.10-1.45 G)DRAWINGFILENAME:TO220B03REV9 HPRESENCEISSUPPLIERDEPENDENT I)SUPPLIERDEPENDENTMOLDLOCKINGHOLES INHEATSINK. 0.60 0.36 2.85 BACKVIEW 2.10 SIDEVIEW

10.36 2.66 A B B 9.96 2.42 3.28 3.40 7.00 3.08 0.70 3.20 SEE NOTE "F" SEE NOTE "F" 6.88 6.48 1 X 45° 16.07 B 15.67 16.00 15.60 (3.23) B 3 1 1.47 2.96 2.14 1.24 2.56 0.90 10.05 0.70 9.45 0.50 M A 30° 0.45 0.60 0.25 B 0.45 2.54 2.54 4.90 B 4.50 NOTES: A. EXCEPT WHERE NOTED CONFORMS TO EIAJ SC91A. B DOES NOT COMPLY EIAJ STD. VALUE. C. ALL DIMENSIONS ARE IN MILLIMETERS. D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS. E. DIMENSION AND TOLERANCE AS PER ASME Y14.5-1994. F. OPTION 1 - WITH SUPPORT PIN HOLE. OPTION 2 - NO SUPPORT PIN HOLE. G. DRAWING FILE NAME: TO220M03REV5

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: FDPF7N60NZ FDPF7N60NZT