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F D N P 8 8 May 2008 9 6 FDP8896 tmM N-Channel PowerTrench® MOSFET 30V, 92A, 5.9mΩ General Description Features This N-Channel MOSFET has been designed specifically to (cid:127) r = 5.9mΩ, V = 10V, I = 35A DS(ON) GS D improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM (cid:127) rDS(ON) = 7.0mΩ, VGS = 4.5V, ID = 35A controllers. It has been optimized for low gate charge, low r and fast switching speed. (cid:127) High performance trench technology for extremely low DS(ON) r DS(ON) (cid:127) Low gate charge Applications (cid:127) High power and current handling capability • DC/DC converters • RoHS Compliant (FLANGE) D DRAIN SOURCE DRAIN GATE G TO-220AB S FDP SERIES MOSFET Maximum Ratings TC = 25°C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage 30 V DSS V Gate to Source Voltage ±20 V GS Drain Current Continuous (T = 25oC, V = 10V) (Note 1) 92 A C GS I Continuous (T = 25oC, V = 4.5V) (Note 1) 85 A D C GS Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W) 16 A Pulsed Figure 4 A E Single Pulse Avalanche Energy (Note 2) 74 mJ AS Power dissipation 80 W P D Derate above 25oC 0.53 W/oC T , T Operating and Storage Temperature -55 to 175 oC J STG Thermal Characteristics RθJC Thermal Resistance Junction to Case TO-220 1.88 oC/W RθJA Thermal Resistance Junction to Ambient TO-220 ( Note 3) 62 oC/W Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDP8896 FDP8896 TO-220AB Tube N/A 50 units ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F Electrical Characteristics T = 25°C unless otherwise noted D C P Symbol Parameter Test Conditions Min Typ Max Units 8 8 Off Characteristics 9 6 B Drain to Source Breakdown Voltage I = 250µA, V = 0V 30 - - V VDSS D GS V = 24V - - 1 I Zero Gate Voltage Drain Current DS µA DSS V = 0V T = 150oC - - 250 GS C I Gate to Source Leakage Current V = ±20V - - ±100 nA GSS GS On Characteristics V Gate to Source Threshold Voltage V = V , I = 250µA 1.2 - 2.5 V GS(TH) GS DS D I = 35A, V = 10V - 0.0050 0.0059 D GS I = 35A, V = 4.5V - 0.0060 0.0070 r Drain to Source On Resistance D GS Ω DS(ON) I = 35A, V = 10V, D GS - 0.0078 0.0094 T = 175oC J Dynamic Characteristics C Input Capacitance - 2525 - pF ISS V = 15V, V = 0V, C Output Capacitance DS GS - 490 - pF OSS f = 1MHz C Reverse Transfer Capacitance - 300 - pF RSS R Gate Resistance V = 0.5V, f = 1MHz - 2.3 - Ω G GS Q Total Gate Charge at 10V V = 0V to 10V - 48 67 nC g(TOT) GS Q Total Gate Charge at 5V V = 0V to 5V - 25 36 nC g(5) GS V = 15V Q Threshold Gate Charge V = 0V to 1V DD - 2.3 3.0 nC g(TH) GS I = 35A Q Gate to Source Gate Charge D - 8 - nC gs I = 1.0mA g Q Gate Charge Threshold to Plateau - 5.7 - nC gs2 Q Gate to Drain “Miller” Charge - 9.5 - nC gd Switching Characteristics (V = 10V) GS t Turn-On Time - - 168 ns ON t Turn-On Delay Time - 9 - ns d(ON) tr Rise Time VDD = 15V, ID = 35A - 103 - ns td(OFF) Turn-Off Delay Time VGS = 4.5V, RGS = 6.2Ω - 56 - ns t Fall Time - 44 - ns f t Turn-Off Time - - 150 ns OFF Drain-Source Diode Characteristics I = 35A - - 1.25 V V Source to Drain Diode Voltage SD SD I = 20A - - 1.0 V SD t Reverse Recovery Time I = 35A, dI /dt = 100A/µs - - 27 ns rr SD SD Q Reverse Recovered Charge I = 35A, dI /dt = 100A/µs - - 12 nC RR SD SD Notes: 1: Package current limitation is 80A. 2: Starting TJ = 25°C, L = 36µH, IAS = 64A, VDD = 27V, VGS = 10V. 3: Pulse width = 100s. 4 ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F Typical Characteristics D T = 25°C unless otherwise noted C P 8 1.2 8 100 9 CURRENT LIMITED 6 R 1.0 BY PACKAGE LIE 80 ULTIP 0.8 NT (A) VGS = 10V SSIPATION M 00..46 RAIN CURRE 4600 VGS = 4.5V DI D R , D WE 0.2 I 20 O P 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs Temperature Case Temperature 2 DUTY CYCLE - DESCENDING ORDER 1 0.5 0.2 0.1 0.05 E DC 0.02 ZEAN 0.01 ORMALIL IMPED 0.1 PDM NA Z, θJCTHERM t1t2 NOTES: DUTY FACTOR: D = t1/t2 SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TC = 25oC FOR TEMPERATURES TRANSCONDUCTANCE MAY LIMIT CURRENT ABOVE 25oC DERATE PEAK A) IN THIS REGION CURRENT AS FOLLOWS: T ( REN I = I25 175 - TC UR VGS = 4.5V 150 C K A E P , M D I 100 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F Typical Characteristics T = 25°C unless otherwise noted D C P 8 1000 500 8 If R = 0 9 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) 6 10µs If R ≠ 0 A) tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] A) 100 NT ( 100 AIN CURRENT ( 10 OPERAARTEIAO NM AINY TBHEIS 100µs ANCHE CURRE 10 STARTING TJ = 25oC DR LIMITED BY rDS(ON) 1ms AL I, D 1 SINGLE PULSE 10ms , AVAS TTJC == M25AoXC RATED DC I STARTING TJ = 150oC 0.1 1 1 10 60 0.01 0.1 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 160 160 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V VDD = 15V VGS = 5V A)120 A) 120 NT ( NT ( VGS = 4V RRE TJ = 25oC RRE CU 80 CU 80 N N RAI RAI VGS = 3V D D I, D 40 I, D 40 TC = 25oC TJ = 175oC TJ = -55oC DPUUTLYS EC YDCULREA T=I O0.N5% = 8M0AµXs 0 0 1.5 2.0 2.5 3.0 3.5 4 0 0.25 0.5 0.75 1.0 1.25 1.5 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 14 1.6 PULSE DURATION = 80µs PULSE DURATION = 80µs ID = 35A DUTY CYCLE = 0.5% MAX E DUTY CYCLE = 0.5% MAX E 12 RC 1.4 , DRAIN TO SOURCDS(ON)ΩON RESISTANCE (m)180 MALIZED DRAIN TO SOUON RESISTANCE11..02 r 6 R 0.8 ID = 1A NO VGS = 10V, ID = 35A 4 0.6 2 4 6 8 10 -80 -40 0 40 80 120 160 200 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On Voltage and Drain Current Resistance vs Junction Temperature ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F Typical Characteristics T = 25°C unless otherwise noted D C P 8 8 1.2 1.2 VGS = VDS, ID = 250µA ID = 250µA 96 E C R MALIZED GATEHOLD VOLTAGE 01..80 D DRAIN TO SOUDOWN VOLTAGE 1.1 NORHRES ALIZEREAK 1.0 T 0.6 MB R O N 0.4 0.9 -80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source Junction Temperature Breakdown Voltage vs Junction Temperature 5000 10 CISS = CGS + CGD V) VDD = 15V GE ( 8 A CE (pF) 1000 COSS ≅ CDS + CGD E VOLT 6 N C A R CIT CRSS = CGD OU C, CAPA ATE TO S 4 WAVEFORMS IN , GGS 2 DESCIDE =N 3D5INAG ORDER: VGS = 0V, f = 1MHz V ID = 16A 100 0 0 10 20 30 40 50 0.1 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Current ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F D P 8 Test Circuits and Waveforms 8 9 6 VDS BVDSS L tP VDS VRAERQYU ItRP ETDO POEBATKA IINAS RG +VDD IAS VDD VGS - DUT tP 0V IAS 0.01Ω 0 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) L VDS VGS VGS = 10V VGS + Qg(5) VDD Qgs2 VGS = 5V - DUT Ig(REF) VGS = 1V 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr tf VDS 90% 90% + VGS VDD 10% 10% - 0 DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 10% 0 Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F PSPICE Electrical Model D P .SUBCKT FDP8896 2 1 3 ; rev November 2003 8 8 Ca 12 8 2.3e-9 LDRAIN 9 Cb 15 14 2.3e-9 DPLCAP 5 DRAIN 6 Cin 6 8 2.3e-9 2 10 RLDRAIN Dbody 7 5 DbodyMOD RSLC1 51 DBREAK Dbreak 5 11 DbreakMOD RSLC2 + Dplcap 10 5 DplcapMOD 551 ESLC 11 - Ebreak 11 7 17 18 33 50 + - EEdgss 1143 88 56 88 11 ESG 68 RDRAIN EBREAK 1178 DBODY Esg 6 10 6 8 1 + EVTHRES 16 - Evthres 6 21 19 8 1 LGATE EVTEMP + 189 - 21 MWEAK Evtemp 20 6 18 22 1 GATE RGATE + 18 - 6 1 9 20 22 MMED It 8 17 1 RLGATE MSTRO LSOURCE Lgate 1 9 5.5e-9 CIN 8 7 SOU3RCE Ldrain 2 5 1.0e-9 RSOURCE Lsource 3 7 2.7e-9 RLSOURCE S1A S2A RRLLdgraatein 1 2 9 5 5 150 12 183 1143 15 17 RBREAK 18 RLsource 3 7 27 S1B S2B RVTEMP Mmed 16 6 8 8 MmedMOD CA 13++ CB+ 14 IT -19 MMwsteroa k1 61 66 281 8 8 M 8s MtrowMeOakDM OD EGS 68 EDS 58 + VBAT -- - 8 Rbreak 17 18 RbreakMOD 1 22 Rdrain 50 16 RdrainMOD 2.3e-3 RVTHRES Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7 + CJO=8.8e-10 M=0.57 TT=1e-16 XTI=2.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4) .MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.68 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7) .MODEL RdrainMOD RES (TC1=1e-3 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8.8e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F SABER Electrical Model D P rev November 2003 8 template FDP8896 n2,n1,n3 =m_temp 8 electrical n2,n1,n3 9 number m_temp=25 6 { var i iscl dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=2.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4) m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.68,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 DRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) 2 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) 10 RLDRAIN sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) RSLC1 c.ca n12 n8 = 2.3e-9 51 RSLC2 c.cb n15 n14 = 2.3e-9 c.cin n6 n8 = 2.3e-9 ISCL 50 DBREAK dp.dbody n7 n5 = model=dbodymod - ddpp..ddpblrceaapk nn150 n n151 == mmooddeell==ddpblrceaapkmmoodd ESG+68 EVTHRES RDR1A6IN 11 DBODY spe.ebreak n11 n7 n17 n18 = 33 LGATE EVTEMP + 189 - 21 MWEAK ssppee..eedgss nn1143 nn88 nn56 nn88 == 11 GA1TE 9RGATE20+ 1282 - 6 MMED EBREA+K spe.esg n6 n10 n6 n8 = 1 RLGATE MSTRO 1178 LSOURCE ssppee..eevvtthermeps nn62 0n 2n16 nn1198 nn82 2= = 1 1 CIN 8 - 7 SOU3RCE RSOURCE RLSOURCE i.it n8 n17 = 1 S1A S2A l.lgate n1 n9 = 5.5e-9 12 13 14 15 17 RBREAK 18 8 13 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.7e-9 S1B S2B RVTEMP res.rlgate n1 n9 = 55 CA 13++ CB+ 14 IT -19 res.rldrain n2 n5 = 10 EGS 68 EDS 58 + VBAT res.rlsource n3 n7 = 27 -- - 8 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp RVTHRES m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7 res.rdrain n50 n16 = 2.3e-3, tc1=1e-3,tc2=8e-6 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8.8e-6 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } } ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

F PSPICE Thermal Model D th JUNCTION P REV 23 November 2003 8 8 FDP8896T 9 6 CTHERM1 TH 6 9e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2e-3 RTHERM1 CTHERM1 CTHERM4 4 3 3e-3 CTHERM5 3 2 7e-3 CTHERM6 2 TL 8e-2 6 RTHERM1 TH 6 3.0e-2 RTHERM2 6 5 1.0e-1 RTHERM3 5 4 1.8e-1 RTHERM2 CTHERM2 RTHERM4 4 3 2.8e-1 RTHERM5 3 2 4.5e-1 RTHERM6 2 TL 4.6e-1 5 SABER Thermal Model SABER thermal model FDP8896T template thermal_model th tl RTHERM3 CTHERM3 thermal_c th, tl { ctherm.ctherm1 th 6 =9e-4 ctherm.ctherm2 6 5 =1e-3 4 ctherm.ctherm3 5 4 =2e-3 ctherm.ctherm4 4 3 =3e-3 ctherm.ctherm5 3 2 =7e-3 RTHERM4 CTHERM4 ctherm.ctherm6 2 tl =8e-2 rtherm.rtherm1 th 6 =3.0e-2 rtherm.rtherm2 6 5 =1.0e-1 3 rtherm.rtherm3 5 4 =1.8e-1 rtherm.rtherm4 4 3 =2.8e-1 rtherm.rtherm5 3 2 =4.5e-1 RTHERM5 CTHERM5 rtherm.rtherm6 2 tl =4.6e-1 } 2 RTHERM6 CTHERM6 tl CASE ©2008 Fairchild Semiconductor Corporation FDP8896 Rev. A2

TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. ACEx® FPS™ PDP-SPM™ The Power Franchise® Build it Now™ F-PFS™ Power-SPM™ CorePLUS™ FRFET® PowerTrench® tm CorePOWER™ Global Power ResourceSM Programmable Active Droop™ TinyBoost™ CROSSVOLT™ Green FPS™ QFET® TinyBuck™ CTL™ Green FPS™ e-Series™ QS™ TinyLogic® Current Transfer Logic™ GTO™ Quiet Series™ TINYOPTO™ EcoSPARK® IntelliMAX™ RapidConfigure™ TinyPower™ EfficentMax™ ISOPLANAR™ Saving our world 1mW at a time™ TinyPWM™ EZSWITCH™ * MegaBuck™ SmartMax™ TinyWire™ ™ MICROCOUPLER™ SMART START™ µSerDes™ MicroFET™ SPM® ® MicroPak™ STEALTH™ Fairchild® MillerDrive™ SuperFET™ UHC® Fairchild Semiconductor® MotionMax™ SuperSOT™-3 Ultra FRFET™ FACT Quiet Series™ Motion-SPM™ SuperSOT™-6 UniFET™ FACT® OPTOLOGIC® SuperSOT™-8 VCX™ FAST® OPTOPLANAR® SuperMOS™ VisualMax™ FastvCore™ ® ® FlashWriter® * tm * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, 2. A critical component in any component of a life support, (a) are intended for surgical implant into the body or (b) device, or system whose failure to perform can be reasonably support or sustain life, and (c) whose failure to perform when expected to cause the failure of the life support device or properly used in accordance with instructions for use provided system, or to affect its safety or effectiveness. in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition This datasheet contains the design specifications for product development. Advance Information Formative or In Design Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be pub- Preliminary First Production lished at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves No Identification Needed Full Production the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that is discontinued by Obsolete Not In Production Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 @2008 Fairchild Semiconductor Corporation FDP8896 Rev.A2

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