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F D M S 8 October 2015 6 3 5 FDMS86350 0 N N-Channel PowerTrench® MOSFET -C h 80 V, 130 A, 2.4 mΩ a n n Features General Description e l (cid:132) Max r = 2.4 mΩ at V = 10 V, I = 25 A This N-Channel MOSFET is produced using Fairchild P DS(on) GS D Semiconductor‘s advanced Power Trench® process that has o (cid:132) Max rDS(on) = 3.2 mΩ at VGS = 8 V, ID = 22 A been especially tailored to minimize the on-state resistance and w e (cid:132) Advanced Package and Silicon combination for low r yet maintain superior switching performance. r DS(on) T and high efficiency Applications re (cid:132) MSL1 robust package design n c (cid:132) Primary MOSFET h (cid:132) 100% UIL tested ® (cid:132) RoHS Compliant (cid:132) Synchronous Rectifier M (cid:132) Load Switch O S (cid:132) Motor Control Switch F E T Bottom Top Pin 1 S S D Pin 1 S S G S D S D D D D D G D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage 80 V DS V Gate to Source Voltage ±20 V GS Drain Current -Continuous T = 25 °C 130 C I -Continuous T = 25 °C (Note 1a) 25 A D A -Pulsed (Note 4) 300 E Single Pulse Avalanche Energy (Note 3) 864 mJ AS Power Dissipation T = 25 °C 156 P C W D Power Dissipation T = 25 °C (Note 1a) 2.7 A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 0.8 θJC °C/W R Thermal Resistance, Junction to Ambient (Note 1a) 45 θJA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS86350 FDMS86350 Power 56 13 ’’ 12 mm 3000 units ©2013 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS86350 Rev. 1.2

F Electrical Characteristics TJ = 25 °C unless otherwise noted D M Symbol Parameter Test Conditions Min Typ Max Units S 8 Off Characteristics 6 3 BV Drain to Source Breakdown Voltage I = 250 μA, V = 0 V 80 V 5 DSS D GS 0 ΔBVDSS Breakdown Voltage Temperature I = 250 μA, referenced to 25 °C 45 mV/°C N ΔT Coefficient D J - C I Zero Gate Voltage Drain Current V = 64 V, V = 0 V 1 μA DSS DS GS h I Gate to Source Leakage Current V = ±20 V, V = 0 V ±100 nA a GSS GS DS n On Characteristics n e VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 2.5 3.8 4.5 V l P ΔV Gate to Source Threshold Voltage o ΔTGS(th) Temperature Coefficient ID = 250 μA, referenced to 25 °C -12 mV/°C w J e VGS = 10 V, ID = 25 A 2.0 2.4 rT rDS(on) Static Drain to Source On Resistance VGS = 8 V, ID = 22 A 2.5 3.2 mΩ re VGS = 10 V, ID = 25 A, TJ = 125 °C 3.1 3.8 n c gFS Forward Transconductance VDS = 5 V, ID = 25 A 70 S h ® Dynamic Characteristics M Ciss Input Capacitance 8030 10680 pF O V = 40 V, V = 0 V, C Output Capacitance DS GS 1370 1825 pF S oss f = 1 MHz F Crss Reverse Transfer Capacitance 31 50 pF E R Gate Resistance 0.1 1.1 3 Ω T g Switching Characteristics t Turn-On Delay Time 50 80 ns d(on) tr Rise Time VDD = 40 V, ID = 25 A, 34 55 ns td(off) Turn-Off Delay Time VGS = 10 V, RGEN = 6 Ω 40 65 ns t Fall Time 11 20 ns f Q Total Gate Charge V = 0 V to 10 V 110 155 nC g GS Qg Total Gate Charge VGS = 0 V to 8 V VDD = 40 V, 90 127 nC Qgs Gate to Source Charge ID = 25 A 46 nC Q Gate to Drain “Miller” Charge 23 nC gd Drain-Source Diode Characteristics I Diode Continuous Forward Current T = 25 °C 130 A S C I Diode Pulse Current T = 25 °C 300 A S, pulse C V = 0 V, I = 2.1 A (Note 2) 0.71 1.2 V Source to Drain Diode Forward Voltage GS S V SD V = 0 V, I = 25 A (Note 2) 0.79 1.3 GS S t Reverse Recovery Time 63 101 ns rr I = 25 A, di/dt = 100 A/μs Q Reverse Recovery Charge F 62 100 nC rr Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 45 °C/W when mounted on a b. 115 °C/W when mounted on a 1 in2 pad of 2 oz copper. minimum pad of 2 oz copper. GDFDSSFSS GDFDSSFSS 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 864 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 24 A, VDD = 80 V, VGS = 10 V, 100% test at L = 0.1 mH, IAS = 74 A. 4. Pulse Id limited by junction temperature, td <= 100 μs, please refer to SOA curve for more details. ©2013 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMS86350 Rev. 1.2

F D M Typical Characteristics TJ = 25 °C unless otherwise noted S 8 6 300 5 3 5 250 VGS = 10 V PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs NCE VGS = 6 V 0 N A 4 T (A) 200 VGS = 8 V ESIST VGS = 6.5 V -Ch I, DRAIN CURREND110550000 VGS = 7 V VGS = 6.5 VVGS = 6 V NORMALIZEDDRAIN TO SOURCE ON-R 0123 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs VGS = 7 VVGS =V G8 SV = 10 V annel PowerTr 0 1 2 3 4 5 0 50 100 150 200 250 300 e n VDS, DRAIN TO SO URCE VOLTAGE (V) ID, DRAIN C URRENT (A) c h Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance ® vs Drain Current and Gate Voltage M O S 1.8 10 F E PULSE DURATION = 80 μs E STANC 1.6 IVDG =S 2=5 1 A0 V ()E mΩ 8 DUTY CYCLE = 0.5% MAX T NORMALIZED AIN TO SOURCE ON-RESI 0111....8024 rDRAIN TO ,DS(on)SOURCE ON-RESISTANC 246 ID =T 2J5 = A 125 ToJC = 25 oC R D 0.6 0 -75 -50 -25 0 25 50 75 100 125 150 5 6 7 8 9 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 300 500 PULSE DURATION = 80 μs A) 250 DUTY CYCLE = 0.5% MAX T ( 100 VGS = 0 V N A) VDS = 5 V RE T (200 UR 10 N C RRE150 AIN 1 TJ = 150 oC U R N C TJ = 150 oC E D I, DRAID10500 TJ = 25 oC REVERS 0.00.11 TJ = 25 oC TJ = -55 oC I, S TJ = -55 oC 0 0.001 3 4 5 6 7 8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2013 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMS86350 Rev. 1.2

F D M Typical Characteristics TJ = 25 °C unless otherwise noted S 8 6 10 10000 3 5 E (V) ID = 25 A VDD = 40 V Ciss 0 N G 8 A - T C OL VDD = 30 V VDD = 50 V pF)1000 Coss h O SOURCE V 46 PACITANCE ( 100 annel P E T CA o AT 2 w V, GGS 0 10 fV =G S1 =M 0H Vz Crss erT r 0 20 40 60 80 100 120 0.1 1 10 80 e Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) nc h Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain ® to Source Voltage M O 100 200 S RθJC = 0.8 oC/W F NT (A) T (A) 160 ET E N R E CUR TJ = 25 oC URR 120 VGS = 10 V E 10 C AVALANCH TJ = 125 oCTJ = 100 oC , IDRAIN D 4800 Limited by Package VGS = 8 V , S A I 1 0 0.01 0.1 1 10 100 1000 25 50 75 100 125 150 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 1000 20000 W)10000 SINGLE PULSE ENT (A) 100 10 μs OWER ( RTCθJ =C 2=5 0 o.C8 oC/W R P R T U 10 THIS AREA IS N N C LIMITED BY rDS(on) 100 μs SIE I, DRAID 1 STRJIθN J=CG M=L AE0X .P8 R UoCAL/STWEED CURVE BENT TO 110 m mss EAK TRAN1000 TC = 25 oC MEASURED DATA DC , P)K 0.1 P 0.1 1 10 100 300 P( 100 10-5 10-4 10-3 10-2 10-1 1 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Operating Area Power Dissipation ©2013 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMS86350 Rev. 1.2

F D M Typical Characteristics TJ = 25 °C unless otherwise noted S 8 2 6 NT DUTY CYCLE-DESCENDING ORDER 35 NSIE 1 0 N A D EFFECTIVE TRAL RESISTANCE 0.1 D = 000000......210005521 PDM t1t2 -Channel ZERM NOTES: P MALITHE SINGLE PULSE RZθθJJCC( =t) 0=. 8r( °t)C x/W RθJC ow OR Peak TJ = PDM x ZθJC(t) + TC e r(t), N 0.0110-5 10-4 10-3 10-2 Du1t0y- 1Cycle, D = t1 / t2 1 rTren t, RECTANGULAR PULSE DURATION (sec) c h Figure 13. Junction-to-Case Transient Thermal Response Curve ® M O S F E T ©2013 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMS86350 Rev. 1.2

5.10 A 4.90 4.42 PKG 3.81 CL B 8 5 8 7 6 5 1.14 KEEP OUT AREA 3.65 PKG CL 6.25 5.90 4.79 6.61 1.27 PIN #1 1 4 IDICATOR TOP VIEW 1 2 3 4 1.27 0.61 SEE DETAIL A 3.81 5.10 LAND PATTERN SIDE VIEW RECOMMENDATION 3.81 0.10 C A B 1.27 0.47 (0.38) (8X) 0.37 1 4 (0.35) 0.65 0.55 NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA, PIN #1 B) ALL DIMENSIONS ARE IN MILLIMETERS. INDICATOR 4.66 4.46 C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER 8 5 ASME Y14.5M-2009. 0.70 E) IT IS RECOMMENDED TO HAVE NO TRACES 4.33 4.13 OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08JREV3. BOTTOM VIEW 0.10 C 1.10 0.90 0.08 C C 0.25 0.05 0.15 0.00 SEATING PLANE SCALE: 2:1

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