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F D M S 8 July 2014 6 2 FDMS86202 0 2 ® N N-Channel Shielded Gate PowerTrench MOSFET - C 120 V, 64 A, 7.2 mΩ h a Features General Description n n e (cid:132) Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild l Semiconductor’s advanced PowerTrench® process that S (cid:132) Max rDS(on) = 7.2 mΩ at VGS = 10 V, ID = 13.5 A incorporates Shielded Gate technology. This process has been hi optimized for the on-state resistance and yet maintain superior e (cid:132) Max rDS(on) = 10.3 mΩ at VGS = 6 V, ID = 11.5 A switching performance. ld e (cid:132) Advanced Package and Silicon combination for low r DS(on) d and high efficiency Application G (cid:132) MSL1 robust package design a (cid:132) DC-DC Conversion t e (cid:132) 100% UIL tested P o (cid:132) RoHS Compliant w e r T r e n c Top Bottom h Pin 1 ® S S D Pin 1 S M S O G S D S F S D E D T D D D G D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol Parameter Ratings Units V Drain to Source Voltage 120 V DS V Gate to Source Voltage ±20 V GS Drain Current -Continuous T = 25 °C 64 C I -Continuous T = 25 °C (Note 1a) 13.5 A D A -Pulsed (Note 4) 240 E Single Pulse Avalanche Energy (Note 3) 600 mJ AS Power Dissipation T = 25 °C 156 P C W D Power Dissipation T = 25 °C (Note 1a) 2.7 A T , T Operating and Storage Junction Temperature Range -55 to +150 °C J STG Thermal Characteristics R Thermal Resistance, Junction to Case 0.8 θJC °C/W R Thermal Resistance, Junction to Ambient (Note 1a) 45 θJA Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FDMS86202 FDMS86202 Power 56 13 ’’ 12 mm 3000 units ©2013 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDMS86202 Rev. C3

F Electrical Characteristics T = 25 °C unless otherwise noted D J M Symbol Parameter Test Conditions Min Typ Max Units S 8 Off Characteristics 6 2 BV Drain to Source Breakdown Voltage I = 250 μA, V = 0 V 120 V 0 DSS D GS 2 ΔBVDSS Breakdown Voltage Temperature I = 250 μA, referenced to 25 °C 103 mV/°C N ΔTJ Coefficient D -C IDSS Zero Gate Voltage Drain Current VDS = 96 V, VGS = 0 V 1 μA h a I Gate to Source Leakage Current V = ±20 V, V = 0 V ±100 nA GSS GS DS n n On Characteristics e l V Gate to Source Threshold Voltage V = V , I = 250 μA 2.0 3.1 4.0 V S GS(th) GS DS D h ΔVGS(th) Gate to Source Threshold Voltage I = 250 μA, referenced to 25 °C -10 mV/°C ie ΔTJ Temperature Coefficient D ld V = 10 V, I = 13.5 A 6.0 7.2 e GS D d rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 11.5 A 8.1 10.3 mΩ G VGS = 10 V, ID = 13.5 A,TJ = 125 °C 10.9 13.2 a t gFS Forward Transconductance VDS = 5 V, ID = 13.5 A 44 S e P Dynamic Characteristics o w Ciss Input Capacitance 3195 4250 pF e Coss Output Capacitance Vf =D S1 =M 6H0z V, VGS = 0 V, 449 600 pF rT r Crss Reverse Transfer Capacitance 17 30 pF e n Rg Gate Resistance 0.1 0.9 2.7 Ω c h Switching Characteristics ® M t Turn-On Delay Time 21 33 ns d(on) O tr Rise Time VDD = 60 V, ID = 13.5 A, 6 13 ns S td(off) Turn-Off Delay Time VGS = 10 V, RGEN = 6 Ω 27 44 ns FE tf Fall Time 5 11 ns T Q Total Gate Charge V = 0 V to 10 V 45 64 nC g GS Qg Total Gate Charge VGS = 0 V to 6 V VDD = 60 V, 29 41 nC Qgs Gate to Source Charge ID = 13.5 A 14.3 nC Q Gate to Drain “Miller” Charge 8.7 nC gd Drain-Source Diode Characteristics V = 0 V, I = 2.1 A (Note 2) 0.69 1.2 V Source to Drain Diode Forward Voltage GS S V SD V = 0 V, I = 13.5 A (Note 2) 0.76 1.3 GS S t Reverse Recovery Time 73 118 ns rr I = 13.5 A, di/dt = 100 A/μs Q Reverse Recovery Charge F 117 187 nC rr Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a)45 °C/W when mounted on a b)115 °C/W when mounted on a 1 in2 pad of 2 oz copper minimum pad of 2 oz copper. GDDSS GDDSS FSFS FSFS 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 600 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 20 A, VDD = 120 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 65 A. 4. Pulse Id limited by junction temperature, td ≤ 100 μs, please refer to SOA curve for more details. ©2013 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDMS86202 Rev. C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J S 8 6 2 240 5 0 VGS = 10 V PULSE DURATION = 80 μs CE V = 5 V 2 A)180 VGS = 8 V DUTY CYCLE = 0.5% MAX STAN 4 GS N-C T ( VGS = 7 V ESI VGS = 6 V h DRAIN CURREN16200 VGS = 6 V NORMALIZEDO SOURCE ON-R 23 VGS = 8 V VGS = 7 V annel Shi I, D VGS = 5 V AIN T 1 PULSE DURATION = 80 μs VGS = 10 V eld R DUTY CYCLE = 0.5% MAX e 0 D 0 d 0 1 2 3 4 5 0 60 120 180 240 G VDS, DRAIN TO SO URCE VOLTAGE (V) ID, DRAIN CURR ENT (A) a t e Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance P vs Drain Current and Gate Voltage o w e r T 2.4 40 r e STANCE 22..02 VIDG =S 1=3 1.50 AV ()E mΩ 30 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs nch® NORMALIZED O SOURCE ON-RESI 11111.....02468 rDRAIN TO ,DS(on)RCE ON-RESISTANC 1200 ID = 1T3J. =5 1A25 oC MOSFET N T 0.8 OU RAI 0.6 S TJ = 25 oC D 0.4 0 -75 -50 -25 0 25 50 75 100 125 150 4 5 6 7 8 9 10 TJ, JUNCTION TEM PERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to vs Junction Temperature Source Voltage 240 300 PDUULTSYE C DYUCRLEA T=I O0.N5 %= 8M0A μXs T (A) 100 VGS = 0 V N A)180 RE 10 T ( VDS = 10 V UR URREN120 RAIN C 1 TJ = 150 oC RAIN C TJ = 150 oC TJ = 25 oC ERSE D 0.1 TJ = 25 oC D 60 V I, D TJ = -55 oC I, RES 0.01 TJ = -55 oC 0 0.001 2 3 4 5 6 7 8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOU RCE VOLTAGE (V) VSD, BODY DIODE FOR WARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2013 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDMS86202 Rev. C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J S 8 6 2 10 10000 0 TAGE (V) 8 ID = 13.5 A VDD = 35 V 1000 Ciss 2 N-C OL VDD = 60 V pF) h O SOURCE V 46 VDD = 85 V PACITANCE ( 100 Coss annel S ATE T 2 CA 10 Crss hie G f = 1 MHz l , GS VGS = 0 V de V 0 1 d 0 10 20 30 40 50 0.1 1 10 100 G Qg, GATE CH ARGE (nC) VDS, DRAIN TO SOU RCE VOLTAGE (V) a t e Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain P to Source Voltage o w e r 100 T 100 r e n A) A) 80 c NT ( NT ( h® E E ANCHE CURR 10 TJ = 25 oTCJ = 100 oC DRAIN CURR 4600 Limited by Package VGS = 6 VVGS = 10 V MOSFE AVAL TJ = 125 oC , ID 20 T I, AS RθJC = 0.8 oC/W 1 0 25 50 75 100 125 150 0.01 0.1 1 10 100 1000 tAV, TIME IN AVA LANCHE (ms) TC, CASE TEMPERATURE (oC) Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Switching Capability Current vs Case Temperature 1000 50000 W) SINGLE PULSE T (A) 100 10 us OWER (10000 TRCθJ =C 2=5 0 o.C8 oC/W REN T P CUR 10 THIS AREA IS SIEN AIN LIMITED BY rDS(on) 100 us RAN1000 R SINGLE PULSE T I, DD 1 RTTJCθ J ==C M2=5A 0 Xo.C8 R oCA/TWED CMUERAVSEU RBEEDN TD ATTOA 11D0 mC mss , PEAK )PK 0.1 P( 100 0.1 1 10 100 400 10-5 10-4 10-3 10-2 10-1 1 VDS, DRAIN to SOU RCE VOLTAGE (V) t, PULSE WI DTH (sec) Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Operating Area Power Dissipation ©2013 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDMS86202 Rev. C3

F D Typical Characteristics M T = 25 °C unless otherwise noted J S 8 6 2 2 0 T 2 EN 1 DUTY CYCLE-DESCENDING ORDER N SI AN D = 0.5 -C D EFFECTIVE TRAL RESISTANCE 0.1 00000.....21000521 PDM t1t2 hannel S EM NOTES: h MALIZTHER 0.01 SINGLE PULSE ZRθθJJCC( t=) =0 .r8( to)C x/ WRθJC ield NOR DPeuatyk CTyJ c=l eP, DDM =x tZ1 θ/J tC2(t) + TC ed r(t), 0.001 G 10-5 10-4 10-3 10-2 10-1 1 a t e t, RECTANGULAR PULSE DURATION (sec) P o w Figure 13. Junction-to-Case Transient Thermal Response Curve e r T r e n c h ® M O S F E T ©2013 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDMS86202 Rev. C3

5.10 A 4.90 4.42 PKG 3.81 CL B 8 5 8 7 6 5 1.14 KEEP OUT AREA 3.65 PKG CL 6.25 5.90 4.79 6.61 1.27 PIN #1 1 4 IDICATOR TOP VIEW 1 2 3 4 1.27 0.61 SEE DETAIL A 3.81 5.10 LAND PATTERN SIDE VIEW RECOMMENDATION 3.81 0.10 C A B 1.27 0.47 (0.38) (8X) 0.37 1 4 (0.35) 0.65 0.55 NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA, PIN #1 B) ALL DIMENSIONS ARE IN MILLIMETERS. INDICATOR 4.66 4.46 C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER 8 5 ASME Y14.5M-2009. 0.70 E) IT IS RECOMMENDED TO HAVE NO TRACES 4.33 4.13 OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08JREV3. BOTTOM VIEW 0.10 C 1.10 0.90 0.08 C C 0.25 0.05 0.15 0.00 SEATING PLANE SCALE: 2:1

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